* Allocating scratch register
@ 2008-01-09 18:26 Boris Boesler
2008-01-09 22:55 ` Ian Lance Taylor
0 siblings, 1 reply; 4+ messages in thread
From: Boris Boesler @ 2008-01-09 18:26 UTC (permalink / raw)
To: GCC
Hi!
I'm trying to allocate a scratch register: write immediate constant
into scratch register r, write register r into memory
;; write imm into memory
(define_insn_and_split "mov<mode>_imm_by_store"
[(set (match_operand:I8I16 0 "memory_operand" "=m")
(match_operand:I8I16 1 "immediate_operand" " i"))
(clobber (match_scratch:I8I16 2 "=r"))]
""
"#"
""
[(parallel
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))])]
""
)
I found that in a mips back-end. But this pattern is not recognized
during code-generation [char c1; c1 = 1;]:
simple-memory.c:19: error: unrecognizable insn:
(insn 12 11 14 3 (set (mem/c/i:QI (reg/f:SI 105) [0 c1+0 S8])
(const_int 1 [0x1])) -1 (nil)
(nil))
If I remove the clobber command and replace (match_dup 2) by
(reg:I8I16 A15_REGNUM) code will be generated (but not as wanted).
What is wrong with the code above?
Thanks,
Boris
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Allocating scratch register
2008-01-09 18:26 Allocating scratch register Boris Boesler
@ 2008-01-09 22:55 ` Ian Lance Taylor
2008-01-10 16:22 ` Boris Boesler
0 siblings, 1 reply; 4+ messages in thread
From: Ian Lance Taylor @ 2008-01-09 22:55 UTC (permalink / raw)
To: Boris Boesler; +Cc: GCC
Boris Boesler <baembel@gmx.de> writes:
> I'm trying to allocate a scratch register: write immediate constant
> into scratch register r, write register r into memory
>
> ;; write imm into memory
> (define_insn_and_split "mov<mode>_imm_by_store"
> [(set (match_operand:I8I16 0 "memory_operand" "=m")
> (match_operand:I8I16 1 "immediate_operand" " i"))
> (clobber (match_scratch:I8I16 2 "=r"))]
> ""
> "#"
> ""
> [(parallel
> [(set (match_dup 2) (match_dup 1))
> (set (match_dup 0) (match_dup 2))])]
> ""
> )
>
> I found that in a mips back-end. But this pattern is not recognized
> during code-generation [char c1; c1 = 1;]:
> simple-memory.c:19: error: unrecognizable insn:
> (insn 12 11 14 3 (set (mem/c/i:QI (reg/f:SI 105) [0 c1+0 S8])
> (const_int 1 [0x1])) -1 (nil)
> (nil))
>
> If I remove the clobber command and replace (match_dup 2) by
> (reg:I8I16 A15_REGNUM) code will be generated (but not as wanted).
>
> What is wrong with the code above?
There is nothing wrong with that code, but nothing is going to make
the compiler use it. Moves are special. If you need a scratch
register to do a move, then you need to look at the
TARGET_SECONDARY_RELOAD hook.
But if the problem is only that you need a register to store a
constant into memory, then you should be able to do that using
register constraints on your mov<mode> insn.
Ian
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Allocating scratch register
2008-01-09 22:55 ` Ian Lance Taylor
@ 2008-01-10 16:22 ` Boris Boesler
2008-01-10 16:47 ` Paul Brook
0 siblings, 1 reply; 4+ messages in thread
From: Boris Boesler @ 2008-01-10 16:22 UTC (permalink / raw)
To: GCC; +Cc: Ian Lance Taylor
Hi!
Am 09.01.2008 um 23:54 schrieb Ian Lance Taylor:
> Boris Boesler <baembel@gmx.de> writes:
>
>> I'm trying to allocate a scratch register: write immediate constant
>> into scratch register r, write register r into memory
...
>> What is wrong with the code above?
>
> There is nothing wrong with that code, but nothing is going to make
> the compiler use it. Moves are special.
Yes, I can remember that constraints in a mov-insn can not be
resolved by other/additional mov-insns.
Ok, I rewrote my insns; there was a "mov<mode>"-insn with mode \in
{QI, HI, SI}:
(define_insn_and_split "movqi"
[(set (match_operand:QI 0 "reg_mem_operand" "=mr")
(match_operand:QI 1 "rim_operand" " mir"))
(clobber (match_scratch:QI 2 "=r"))
]
""
"#"
"&& reload_completed"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
"")
;; help insns
(define_insn "mov<mode>_reg_by_store"
[(set (match_operand:I8I16 0 "memory_operand" "= m")
(match_operand:I8I16 1 "register_operand" " rAx"))]
""
"bla bla bla")
(define_insn "mov<mode>_reg_imm"
[(set (match_operand:I8I16 0 "register_operand" "=rAx, rAx, rAx")
(match_operand:I8I16 1 "immediate_operand" " I, i, rAx"))]
""
"some other bla bla bla")
These insns handle byte-accesses as expected. But now a previous
tests fail for something like ashift:SI(reg:SI, const_int:QI 5):
p.c:36: error: unrecognizable insn:
(insn 114 18 115 (set (scratch:QI)
(const_int 5 [0x5])) -1 (nil)
(nil))
I do not understand why this happens does not happen in my byte-
access example. So I added the two insns (I8I16 = {QI, HI}):
(define_insn "mov<mode>_to_scratch"
[(set (match_scratch:I8I16 0 "=r,r")
(match_operand:I8I16 1 "reg_imm_operand" " r,i"))]
""
"again bla bla bla")
(define_insn "mov<mode>_from_scratch"
[(set (match_operand:I8I16 0 "register_operand" "=r")
(match_scratch:I8I16 1 " r"))]
""
"even more bla bla bla")
But now the compiler says:
p.c:36: error: insn does not satisfy its constraints:
(insn 114 18 115 (set (scratch:QI)
(const_int 5 [0x5])) 79 {movqi_to_scratch} (nil)
(nil))
p.c:36: internal compiler error: in final_scan_insn, at final.c:2382
The two insns in the dump file .shorten are:
(insn 114 18 115 (set (scratch:QI)
(const_int 5 [0x5])) 79 {movqi_to_scratch} (nil)
(nil))
(insn 115 114 19 (set (reg:QI 31 R31)
(scratch:QI)) 81 {movqi_from_scratch} (nil)
(nil))
I can't see what's wrong. I guess I don't understand that scratch-
stuff in gcc?
Thanks,
Boris
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Allocating scratch register
2008-01-10 16:22 ` Boris Boesler
@ 2008-01-10 16:47 ` Paul Brook
0 siblings, 0 replies; 4+ messages in thread
From: Paul Brook @ 2008-01-10 16:47 UTC (permalink / raw)
To: gcc; +Cc: Boris Boesler, Ian Lance Taylor
> Yes, I can remember that constraints in a mov-insn can not be
> resolved by other/additional mov-insns.
I think you're doing this the wrong way. You don't have a i->m mov
instruction, so why are you pretending you do?
Why aren't you doing this the same way as pretty much every other target?
i.e.:
(define_insn "*movqi_insn"
[(set (match_operand:QI 0 "reg_mem_operand" "=r,m")
(match_operand:QI 1 "rim_operand" " mi,r"))
""
"mov %0,%1"
)
(define_expand "movqi"
[(set (match...) (match...)]
""
"
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (QImode, operands[1]);
"
)
Plus the appropriate *_RELOAD_CLASS macros to keep reload happy.
Paul
^ permalink raw reply [flat|nested] 4+ messages in thread
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2008-01-09 18:26 Allocating scratch register Boris Boesler
2008-01-09 22:55 ` Ian Lance Taylor
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2008-01-10 16:47 ` Paul Brook
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