* regrename and odd behaviour with early clobber operands
@ 2011-08-16 6:40 Ramana Radhakrishnan
2011-08-16 15:25 ` Richard Sandiford
0 siblings, 1 reply; 3+ messages in thread
From: Ramana Radhakrishnan @ 2011-08-16 6:40 UTC (permalink / raw)
To: gcc
[-- Attachment #1: Type: text/plain, Size: 4544 bytes --]
Hi,
The attached testcase fails with -mvectorize-with-neon-quad and
-mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -funroll-all-loops on
arm-linux-gnueabi.
The problem essentially is that regrename wants to rename reg 103
(i.e. q10 printed as d20 in the RTL dumps ) in the following
instruction sequence. I will continue to use d20 in my description
below as it helps reference bits of the dumps.
(insn 122 161 169 3 (set (reg:V4SI 103 d20 [322])
(unspec:V4SI [
(reg:V4SI 99 d18 [316])
(reg:V4SI 103 d20 [323])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 99 d18 [316])
(reg:V4SI 103 d20 [320]))
(nil)))
(insn 123 139 140 3 (set (reg:V8HI 107 d22 [324])
(vec_concat:V8HI (truncate:V4HI (reg:V4SI 115 d26 [314]))
(truncate:V4HI (reg:V4SI 103 d20 [322])))) /tmp/x.c:16
1775 {vec_pack_trunc_v4si}
(nil))
(insn 140 123 141 3 (set (reg:V8HI 103 d20 [341])
(vec_concat:V8HI (truncate:V4HI (reg:V4SI 111 d24 [331]))
(truncate:V4HI (reg:V4SI 99 d18 [339])))) /tmp/x.c:16 1775
{vec_pack_trunc_v4si}
(nil))
(insn 141 140 143 3 (set (reg:V16QI 99 d18 [342])
(vec_concat:V16QI (truncate:V8QI (reg:V8HI 107 d22 [324]))
(truncate:V8QI (reg:V8HI 103 d20 [341])))) /tmp/x.c:16
1774 {vec_pack_trunc_v8hi}
(nil))
And this is because it thinks d20 is in one chain from
Register d20 (4): 122 [VFP_REGS] 123 [VFP_REGS] 141 [VFP_REGS]
as well as in a chain from :
Register d20 (4): 140 [VFP_REGS] 141 [VFP_REGS]
and it then goes ahead and renames d20 in insn 122, 123 and 141 and
ignores the fact that the use in insn 141 was essentially the def in
insn 140 and not the def from insn 122.
I can't see how it is right to construct essentially 2 chains for the
same register that have overlapping live ranges without an intervening
conditional branch and since regrename sort of works inside a bb .
Ideally the chain for 122 should have been terminated at the end of
123 rather than allowing this to remain open and have the use in insn
141 available for use in both chains starting at 122 and 140 . What
I'm not sure is which part of regrename makes sure that this part of
the comment for Stage 5 is ensured.
`and earlier
chains they would overlap with must have been closed at
the previous insn at the latest, as such operands cannot
possibly overlap with any input operands. */'
I suspect this is by using some of the conflicts info in each chain
but a quick read couldn't help me figure out where this was being done
and how we were ensuring that such an early clobber case was being
handled cleanly.
I must point out that the pattern for vec_pack_trunc in this case does
have an early clobber in the destination to prevent overlapping source
and destination registers as a vec_pack_trunc as on neon something
like this for 128 bit vectors can only be done with 2 operations .
While this isn't a wrong representation in the backend I we should get
better code without that early clobber and by just using
reg_overlap_mentioned_p as in the patch below .
However I'm not convinced that the regrename behaviour is correct and
I think it's still something worth bringing up as it possibly makes
the regrename.c behaviour latent atleast on the arm port and it might
be worth figuring out this odd behaviour.
Thanks in advance for any help in this area.
cheers
Ramana
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 24dd941..1825612 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5631,14 +5631,19 @@
; the semantics of the instructions require.
(define_insn "vec_pack_trunc_<mode>"
- [(set (match_operand:<V_narrow_pack> 0 "register_operand" "=&w")
+ [(set (match_operand:<V_narrow_pack> 0 "register_operand" "=w")
(vec_concat:<V_narrow_pack>
(truncate:<V_narrow>
(match_operand:VN 1 "register_operand" "w"))
(truncate:<V_narrow>
(match_operand:VN 2 "register_operand" "w"))))]
"TARGET_NEON && !BYTES_BIG_ENDIAN"
- "vmovn.i<V_sz_elem>\t%e0, %q1\;vmovn.i<V_sz_elem>\t%f0, %q2"
+ {
+ if (reg_overlap_mentioned_p (operands[0], operands[1]))
+ return "vmovn.i<V_sz_elem>\t%e0, %q1\;vmovn.i<V_sz_elem>\t%f0, %q2";
+ else
+ return "vmovn.i<V_sz_elem>\t%f0, %q2\;vmovn.i<V_sz_elem>\t%e0, %q1";
+ }
[(set_attr "neon_type" "neon_shift_1")
(set_attr "length" "8")]
)
[-- Attachment #2: x.c --]
[-- Type: text/x-csrc, Size: 929 bytes --]
/* #include <stdint.h> */
/* #include <string.h> */
/* #include <stdlib.h> */
/* #include <stdio.h> */
typedef int int32_t;
typedef signed char int8_t;
typedef unsigned int uint32_t;
__attribute__ ((noinline)) void f883b (int8_t * result,
int32_t * __restrict arg1,
uint32_t * __restrict arg2)
{
int idx;
for (idx=48;idx<80;idx += 1) {
result[idx] = arg1[idx] >> (arg2[idx] & 7);
}
}
int8_t result[96];
int32_t arg1[96];
uint32_t arg2[96];
int main (void)
{
int i;
int correct[] = {48,24,12,6,3,1,0,0,56,28,14,7,3,1,0,0,64,32,16,8,4,2,1,0,72,36,18,9,4,2,1,0};
for (i=0; i < 96; i++)
{
arg2[i] = arg1[i] = i;
__asm__ volatile ("");
}
f883b(result, arg1, arg2);
for (i=48; i < 80; i++)
if (result[i] != correct[i-48])
{
/* fprintf (stderr, "result [%d] = %d, correct[%d - 48] = %d\n", i, result[i], i, correct[i-48]); */
abort ();
}
return 0;
}
[-- Attachment #3: x.c.203r.rnreg --]
[-- Type: application/octet-stream, Size: 106494 bytes --]
;; Function f883b (f883b, funcdef_no=0, decl_uid=4784, cgraph_uid=0)
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
Basic block 2:
Creating chain ip (0) at insn 80
Creating chain r5 (1) at insn 85
Creating chain r4 (2) at insn 94
Creating chain r3 (3) at insn 79
Creating chain r8 (4) at insn 81
Creating chain r7 (5) at insn 90
Closing chain r8 (4) at insn 89 (terminate_dead, superset)
Closing chain r7 (5) at insn 98 (terminate_dead, superset)
Closing chain ip (0) at insn 104 (terminate_dead, superset)
Register ip (1): 80 [GENERAL_REGS] 351 [GENERAL_REGS] 354 [GENERAL_REGS] 355 [GENERAL_REGS] 356 [GENERAL_REGS] 98 [GENERAL_REGS] 98 [GENERAL_REGS] 104 [GENERAL_REGS]
Register r7 (1): 90 [GENERAL_REGS] 98 [GENERAL_REGS]
Register r8 (1): 81 [GENERAL_REGS] 89 [GENERAL_REGS]
Register ip in insn 80; no available better choice
Register r7 in insn 90; no available better choice
Register r8 in insn 81; no available better choice
Basic block 3:
Creating chain r8 (0) at insn 117
Creating chain r7 (1) at insn 126
Creating chain r6 (2) at insn 134
Creating chain d16 (3) at insn 111
Creating chain d26 (4) at insn 110
Creating chain r9 (5) at insn 115
Closing chain d26 (4) at insn 112 (terminate_write, superset)
Creating chain d26 (6) at insn 112
Creating chain ip (7) at insn 124
Closing chain r8 (0) at insn 118 (terminate_dead, superset)
Creating chain d20 (8) at insn 118
Creating chain sl (9) at insn 132
Closing chain d20 (8) at insn 120 (terminate_write, superset)
Creating chain d20 (10) at insn 120
Creating chain r8 (11) at insn 146
Closing chain r7 (1) at insn 127 (terminate_dead, superset)
Creating chain d28 (12) at insn 127
Closing chain d26 (6) at insn 113 (terminate_write, superset)
Creating chain d26 (13) at insn 113
Closing chain d28 (12) at insn 129 (terminate_write, superset)
Creating chain d28 (14) at insn 129
Creating chain r7 (15) at insn 154
Closing chain r6 (2) at insn 135 (terminate_dead, superset)
Creating chain d22 (16) at insn 135
Closing chain d20 (10) at insn 121 (terminate_write, superset)
Creating chain d20 (17) at insn 121
Closing chain d22 (16) at insn 137 (terminate_write, superset)
Creating chain d22 (18) at insn 137
Creating chain r6 (19) at insn 163
Closing chain d28 (14) at insn 130 (terminate_write, superset)
Creating chain d28 (20) at insn 130
Creating chain d24 (21) at insn 108
Creating chain r2 (22) at insn 171
Creating chain r5 (23) at insn 144
Closing chain d22 (18) at insn 138 (terminate_write, superset)
Creating chain d22 (24) at insn 138
Creating chain d18 (25) at insn 116
Closing chain d26 (13) at insn 114 (terminate_write, superset)
Creating chain d26 (26) at insn 114
Creating chain r4 (27) at insn 152
Closing chain ip (7) at insn 125 (terminate_dead, superset)
Closing chain d24 (21) at insn 125 (terminate_write, superset)
Creating chain d24 (28) at insn 125
Creating chain ip (29) at insn 161
Closing chain d20 (17) at insn 122 (terminate_write, superset)
Creating chain d20 (30) at insn 122
Creating chain r1 (31) at insn 169
Closing chain d18 (25) at insn 133 (terminate_write, superset)
Creating chain d18 (32) at insn 133
Creating chain r0 (33) at insn 179
Closing chain d24 (28) at insn 131 (terminate_write, superset)
Creating chain d24 (34) at insn 131
Closing chain d18 (32) at insn 139 (terminate_write, superset)
Creating chain d18 (35) at insn 139
Creating chain d22 (36) at insn 123
Creating chain d20 (37) at insn 140
Creating chain d18 (38) at insn 141
Closing chain d24 (34) at insn 147 (terminate_write, superset)
Creating chain d24 (39) at insn 147
Closing chain d24 (39) at insn 149 (terminate_write, superset)
Creating chain d24 (40) at insn 149
Closing chain d20 (37) at insn 155 (terminate_write, superset)
Closing chain d20 (30) at insn 155 (terminate_write, superset)
Creating chain d20 (41) at insn 155
Closing chain d20 (41) at insn 157 (terminate_write, superset)
Creating chain d20 (42) at insn 157
Closing chain d26 (26) at insn 164 (terminate_write, superset)
Creating chain d26 (43) at insn 164
Closing chain d24 (40) at insn 150 (terminate_write, superset)
Creating chain d24 (44) at insn 150
Closing chain d26 (43) at insn 166 (terminate_write, superset)
Creating chain d26 (45) at insn 166
Closing chain r2 (22) at insn 172 (terminate_dead, superset)
Closing chain d22 (36) at insn 172 (terminate_write, superset)
Closing chain d22 (24) at insn 172 (terminate_write, superset)
Creating chain d22 (46) at insn 172
Closing chain d20 (42) at insn 158 (terminate_write, superset)
Creating chain d20 (47) at insn 158
Closing chain d16 (3) at insn 174 (terminate_write, superset)
Creating chain d16 (48) at insn 174
Closing chain d26 (45) at insn 167 (terminate_write, superset)
Creating chain d26 (49) at insn 167
Closing chain d22 (46) at insn 145 (terminate_write, superset)
Creating chain d22 (50) at insn 145
Closing chain d16 (48) at insn 175 (terminate_write, superset)
Creating chain d16 (51) at insn 175
Closing chain d18 (38) at insn 153 (terminate_write, superset)
Closing chain d18 (35) at insn 153 (terminate_write, superset)
Creating chain d18 (52) at insn 153
Closing chain d24 (44) at insn 151 (terminate_write, superset)
Creating chain d24 (53) at insn 151
Closing chain ip (29) at insn 162 (terminate_dead, superset)
Closing chain d22 (50) at insn 162 (terminate_write, superset)
Creating chain d22 (54) at insn 162
Closing chain d18 (52) at insn 159 (terminate_write, superset)
Creating chain d18 (55) at insn 159
Closing chain r1 (31) at insn 170 (terminate_dead, superset)
Closing chain d20 (47) at insn 170 (terminate_write, superset)
Creating chain d20 (56) at insn 170
Closing chain d22 (54) at insn 168 (terminate_write, superset)
Creating chain d22 (57) at insn 168
Closing chain d16 (51) at insn 176 (terminate_write, superset)
Creating chain d16 (58) at insn 176
Creating chain d20 (59) at insn 160
Creating chain d18 (60) at insn 177
Creating chain d16 (61) at insn 178
Closing chain r0 (33) at insn 180 (terminate_dead, superset)
Register r0 (1): 179 [GENERAL_REGS] 180 [CORE_REGS]
Register d16 (4): 175 [VFP_REGS] 176 [VFP_REGS]
Register d22 (4): 162 [VFP_REGS] 168 [VFP_REGS]
Register d20 (4): 158 [VFP_REGS] 159 [VFP_REGS]
Register r1 (1): 169 [GENERAL_REGS] 170 [CORE_REGS]
Register d18 (4): 153 [VFP_REGS] 159 [VFP_REGS]
Register d22 (4): 145 [VFP_REGS] 151 [VFP_REGS]
Register ip (1): 161 [GENERAL_REGS] 162 [CORE_REGS]
Register d24 (4): 150 [VFP_REGS] 151 [VFP_REGS]
Register d18 (4): 139 [VFP_REGS] 140 [VFP_REGS] 143 [VFP_REGS]
Register d18 (4): 141 [VFP_REGS] 143 [VFP_REGS]
Register d16 (4): 174 [VFP_REGS] 175 [VFP_REGS]
Register d22 (4): 172 [VFP_REGS] 174 [VFP_REGS]
Register d26 (4): 166 [VFP_REGS] 167 [VFP_REGS]
Register d16 (4): 111 [VFP_REGS] 112 [VFP_REGS] 120 [VFP_REGS] 129 [VFP_REGS] 137 [VFP_REGS] 149 [VFP_REGS] 157 [VFP_REGS] 166 [VFP_REGS] 174 [VFP_REGS]
Register d20 (4): 157 [VFP_REGS] 158 [VFP_REGS]
Register d22 (4): 138 [VFP_REGS] 139 [VFP_REGS] 141 [VFP_REGS]
Register d22 (4): 123 [VFP_REGS] 141 [VFP_REGS]
Register r2 (1): 171 [GENERAL_REGS] 172 [CORE_REGS]
Register d26 (4): 164 [VFP_REGS] 166 [VFP_REGS]
Register d24 (4): 149 [VFP_REGS] 150 [VFP_REGS]
Register d26 (4): 114 [VFP_REGS] 123 [VFP_REGS]
Register d20 (4): 155 [VFP_REGS] 157 [VFP_REGS]
Register d20 (4): 122 [VFP_REGS] 123 [VFP_REGS] 141 [VFP_REGS]
Register d20 (4): 140 [VFP_REGS] 141 [VFP_REGS]
Register d24 (4): 147 [VFP_REGS] 149 [VFP_REGS]
Register d24 (4): 131 [VFP_REGS] 140 [VFP_REGS]
Register d18 (4): 133 [VFP_REGS] 139 [VFP_REGS]
Register d24 (4): 125 [VFP_REGS] 131 [VFP_REGS]
Register d18 (4): 116 [VFP_REGS] 122 [VFP_REGS]
Register d20 (4): 121 [VFP_REGS] 122 [VFP_REGS]
Register d24 (4): 108 [VFP_REGS] 114 [VFP_REGS]
Register ip (1): 124 [GENERAL_REGS] 125 [CORE_REGS]
Register d26 (4): 113 [VFP_REGS] 114 [VFP_REGS]
Register d22 (4): 137 [VFP_REGS] 138 [VFP_REGS]
Register d28 (4): 129 [VFP_REGS] 130 [VFP_REGS]
Register d22 (4): 135 [VFP_REGS] 137 [VFP_REGS]
Register d20 (4): 120 [VFP_REGS] 121 [VFP_REGS]
Register r6 (1): 134 [GENERAL_REGS] 135 [CORE_REGS]
Register d28 (4): 127 [VFP_REGS] 129 [VFP_REGS]
Register d26 (4): 112 [VFP_REGS] 113 [VFP_REGS]
Register r7 (1): 126 [GENERAL_REGS] 127 [CORE_REGS]
Register d20 (4): 118 [VFP_REGS] 120 [VFP_REGS]
Register r8 (1): 117 [GENERAL_REGS] 118 [CORE_REGS]
Register d26 (4): 110 [VFP_REGS] 112 [VFP_REGS]
Register r0 in insn 179; no available better choice
Register d16 in insn 175; no available better choice
Register d22 in insn 162; no available better choice
Register d20 in insn 158; no available better choice
Register r1 in insn 169; no available better choice
Register d18 in insn 153; no available better choice
Register d22 in insn 145, renamed as s0
deferring rescan insn with uid = 145.
deferring rescan insn with uid = 151.
Register ip in insn 161; no available better choice
Register d24 in insn 150; no available better choice
Register d18 in insn 139, renamed as s4
deferring rescan insn with uid = 139.
deferring rescan insn with uid = 140.
deferring rescan insn with uid = 143.
Register d18 in insn 141, renamed as s8
deferring rescan insn with uid = 141.
deferring rescan insn with uid = 143.
Register d16 in insn 174, renamed as s12
deferring rescan insn with uid = 174.
deferring rescan insn with uid = 175.
Register d22 in insn 172, renamed as d30
deferring rescan insn with uid = 172.
deferring rescan insn with uid = 174.
Register d26 in insn 166; no available better choice
Register d16 in insn 111; no available better choice
Register d20 in insn 157; no available better choice
Register d22 in insn 138; no available better choice
Register d22 in insn 123, renamed as d18
deferring rescan insn with uid = 123.
deferring rescan insn with uid = 141.
Register r2 in insn 171; no available better choice
Register d26 in insn 164, renamed as s0
deferring rescan insn with uid = 164.
deferring rescan insn with uid = 166.
Register d24 in insn 149; no available better choice
Register d26 in insn 114, renamed as s12
deferring rescan insn with uid = 114.
deferring rescan insn with uid = 123.
Register d20 in insn 155, renamed as d30
deferring rescan insn with uid = 155.
deferring rescan insn with uid = 157.
Register d20 in insn 122, renamed as d26
deferring rescan insn with uid = 122.
deferring rescan insn with uid = 123.
deferring rescan insn with uid = 141.
Register d20 in insn 140; no available better choice
Register d24 in insn 147, renamed as s0
deferring rescan insn with uid = 147.
deferring rescan insn with uid = 149.
Register d24 in insn 131; no available better choice
Register d18 in insn 133, renamed as s4
deferring rescan insn with uid = 133.
deferring rescan insn with uid = 139.
Register d24 in insn 125, renamed as s8
deferring rescan insn with uid = 125.
deferring rescan insn with uid = 131.
Register d18 in insn 116; no available better choice
Register d20 in insn 121, renamed as d30
deferring rescan insn with uid = 121.
deferring rescan insn with uid = 122.
Register d24 in insn 108, renamed as d20
deferring rescan insn with uid = 108.
deferring rescan insn with uid = 114.
Register ip in insn 124; no available better choice
Register d26 in insn 113, renamed as s12
deferring rescan insn with uid = 113.
deferring rescan insn with uid = 114.
Register d22 in insn 137; no available better choice
Register d28 in insn 129; no available better choice
Register d22 in insn 135, renamed as d26
deferring rescan insn with uid = 135.
deferring rescan insn with uid = 137.
Register d20 in insn 120, renamed as s0
deferring rescan insn with uid = 120.
deferring rescan insn with uid = 121.
Register r6 in insn 134; no available better choice
Register d28 in insn 127, renamed as d24
deferring rescan insn with uid = 127.
deferring rescan insn with uid = 129.
Register d26 in insn 112, renamed as s4
deferring rescan insn with uid = 112.
deferring rescan insn with uid = 113.
Register r7 in insn 126; no available better choice
Register d20 in insn 118, renamed as s8
deferring rescan insn with uid = 118.
deferring rescan insn with uid = 120.
Register r8 in insn 117, renamed as sl
deferring rescan insn with uid = 117.
deferring rescan insn with uid = 118.
Register d26 in insn 110, renamed as d18
deferring rescan insn with uid = 110.
deferring rescan insn with uid = 112.
Basic block 4:
Creating chain r1 (0) at insn 185
Creating chain r2 (1) at insn 186
Creating chain r3 (2) at insn 76
Basic block 5:
Creating chain r4 (0) at insn 190
Creating chain ip (1) at insn 337
Creating chain r5 (2) at insn 192
Creating chain sl (3) at insn 238
Closing chain r4 (0) at insn 191 (terminate_write, superset)
Creating chain r4 (4) at insn 191
Creating chain r8 (5) at insn 253
Creating chain r7 (6) at insn 268
Creating chain r6 (7) at insn 283
Closing chain r5 (2) at insn 193 (terminate_dead, superset)
Closing chain r4 (4) at insn 193 (terminate_write, superset)
Creating chain r4 (8) at insn 193
Closing chain r4 (8) at insn 195 (terminate_dead, superset)
Creating chain r9 (9) at insn 233
Creating chain r5 (10) at insn 298
Creating chain fp (11) at insn 235
Creating chain r4 (12) at insn 313
Closing chain r9 (9) at insn 234 (terminate_write, superset)
Creating chain r9 (13) at insn 234
Creating chain r3 (14) at insn 328
Closing chain r9 (13) at insn 236 (terminate_write, superset)
Creating chain r9 (15) at insn 236
Closing chain ip (1) at insn 237 (terminate_dead, superset)
Closing chain r9 (15) at insn 237 (terminate_dead, superset)
Creating chain ip (16) at insn 248
Creating chain r9 (17) at insn 250
Closing chain ip (16) at insn 249 (terminate_write, superset)
Creating chain ip (18) at insn 249
Closing chain ip (18) at insn 251 (terminate_write, superset)
Creating chain ip (19) at insn 251
Closing chain ip (19) at insn 252 (terminate_dead, superset)
Closing chain sl (3) at insn 252 (terminate_dead, superset)
Creating chain ip (20) at insn 263
Creating chain sl (21) at insn 265
Closing chain ip (20) at insn 264 (terminate_write, superset)
Creating chain ip (22) at insn 264
Closing chain ip (22) at insn 266 (terminate_write, superset)
Creating chain ip (23) at insn 266
Closing chain ip (23) at insn 267 (terminate_dead, superset)
Closing chain r8 (5) at insn 267 (terminate_dead, superset)
Creating chain ip (24) at insn 278
Creating chain r8 (25) at insn 280
Closing chain ip (24) at insn 279 (terminate_write, superset)
Creating chain ip (26) at insn 279
Closing chain ip (26) at insn 281 (terminate_write, superset)
Creating chain ip (27) at insn 281
Closing chain ip (27) at insn 282 (terminate_dead, superset)
Closing chain r7 (6) at insn 282 (terminate_dead, superset)
Creating chain ip (28) at insn 293
Creating chain r7 (29) at insn 295
Closing chain ip (28) at insn 294 (terminate_write, superset)
Creating chain ip (30) at insn 294
Closing chain ip (30) at insn 296 (terminate_write, superset)
Creating chain ip (31) at insn 296
Closing chain ip (31) at insn 297 (terminate_dead, superset)
Closing chain r6 (7) at insn 297 (terminate_dead, superset)
Creating chain ip (32) at insn 308
Creating chain r6 (33) at insn 310
Closing chain ip (32) at insn 309 (terminate_write, superset)
Creating chain ip (34) at insn 309
Closing chain ip (34) at insn 311 (terminate_write, superset)
Creating chain ip (35) at insn 311
Closing chain ip (35) at insn 312 (terminate_dead, superset)
Closing chain r5 (10) at insn 312 (terminate_dead, superset)
Creating chain ip (36) at insn 323
Creating chain r5 (37) at insn 325
Closing chain ip (36) at insn 324 (terminate_write, superset)
Creating chain ip (38) at insn 324
Closing chain ip (38) at insn 326 (terminate_write, superset)
Creating chain ip (39) at insn 326
Closing chain ip (39) at insn 327 (terminate_dead, superset)
Register ip (1): 326 [GENERAL_REGS] 327 [GENERAL_REGS]
Register ip (1): 324 [GENERAL_REGS] 326 [GENERAL_REGS]
Register ip (1): 323 [CORE_REGS] 324 [GENERAL_REGS]
Register r5 (1): 298 [GENERAL_REGS] 312 [GENERAL_REGS]
Register ip (1): 311 [GENERAL_REGS] 312 [GENERAL_REGS]
Register ip (1): 309 [GENERAL_REGS] 311 [GENERAL_REGS]
Register ip (1): 308 [CORE_REGS] 309 [GENERAL_REGS]
Register r6 (1): 283 [GENERAL_REGS] 297 [GENERAL_REGS]
Register ip (1): 296 [GENERAL_REGS] 297 [GENERAL_REGS]
Register ip (1): 294 [GENERAL_REGS] 296 [GENERAL_REGS]
Register ip (1): 293 [CORE_REGS] 294 [GENERAL_REGS]
Register r7 (1): 268 [GENERAL_REGS] 282 [GENERAL_REGS]
Register ip (1): 281 [GENERAL_REGS] 282 [GENERAL_REGS]
Register ip (1): 279 [GENERAL_REGS] 281 [GENERAL_REGS]
Register ip (1): 278 [CORE_REGS] 279 [GENERAL_REGS]
Register r8 (1): 253 [GENERAL_REGS] 267 [GENERAL_REGS]
Register ip (1): 266 [GENERAL_REGS] 267 [GENERAL_REGS]
Register ip (1): 264 [GENERAL_REGS] 266 [GENERAL_REGS]
Register ip (1): 263 [CORE_REGS] 264 [GENERAL_REGS]
Register sl (1): 238 [GENERAL_REGS] 252 [GENERAL_REGS]
Register ip (1): 251 [GENERAL_REGS] 252 [GENERAL_REGS]
Register ip (1): 249 [GENERAL_REGS] 251 [GENERAL_REGS]
Register ip (1): 248 [CORE_REGS] 249 [GENERAL_REGS]
Register r9 (1): 236 [GENERAL_REGS] 237 [GENERAL_REGS]
Register ip (1): 337 [GENERAL_REGS] 237 [GENERAL_REGS]
Register r9 (1): 234 [GENERAL_REGS] 236 [GENERAL_REGS]
Register r9 (1): 233 [CORE_REGS] 234 [GENERAL_REGS]
Register r4 (1): 193 [GENERAL_REGS] 195 [GENERAL_REGS]
Register r4 (1): 191 [GENERAL_REGS] 193 [GENERAL_REGS]
Register r5 (1): 192 [CORE_REGS] 193 [GENERAL_REGS]
Register r4 (1): 190 [CORE_REGS] 191 [GENERAL_REGS]
Register ip in insn 326; no available better choice
Register ip in insn 324; no available better choice
Register ip in insn 323; no available better choice
Register r5 in insn 298; no available better choice
Register ip in insn 311; no available better choice
Register ip in insn 309; no available better choice
Register ip in insn 308; no available better choice
Register r6 in insn 283; no available better choice
Register ip in insn 296; no available better choice
Register ip in insn 294; no available better choice
Register ip in insn 293; no available better choice
Register r7 in insn 268; no available better choice
Register ip in insn 281; no available better choice
Register ip in insn 279; no available better choice
Register ip in insn 278; no available better choice
Register r8 in insn 253; no available better choice
Register ip in insn 266; no available better choice
Register ip in insn 264; no available better choice
Register ip in insn 263; no available better choice
Register sl in insn 238; no available better choice
Register ip in insn 251; no available better choice
Register ip in insn 249; no available better choice
Register ip in insn 248; no available better choice
Register r9 in insn 236; no available better choice
Register ip in insn 337; no available better choice
Register r9 in insn 234; no available better choice
Register r9 in insn 233; no available better choice
Register r4 in insn 193; no available better choice
Register r4 in insn 191, renamed as fp
deferring rescan insn with uid = 191.
deferring rescan insn with uid = 193.
Register r5 in insn 192; no available better choice
Register r4 in insn 190, renamed as r6
deferring rescan insn with uid = 190.
deferring rescan insn with uid = 191.
Basic block 6:
starting the processing of deferred insns
rescanning insn with uid = 108.
deleting insn with uid = 108.
rescanning insn with uid = 110.
deleting insn with uid = 110.
rescanning insn with uid = 112.
deleting insn with uid = 112.
rescanning insn with uid = 113.
deleting insn with uid = 113.
rescanning insn with uid = 114.
deleting insn with uid = 114.
rescanning insn with uid = 117.
deleting insn with uid = 117.
rescanning insn with uid = 118.
deleting insn with uid = 118.
rescanning insn with uid = 120.
deleting insn with uid = 120.
rescanning insn with uid = 121.
deleting insn with uid = 121.
rescanning insn with uid = 122.
deleting insn with uid = 122.
rescanning insn with uid = 123.
deleting insn with uid = 123.
rescanning insn with uid = 125.
deleting insn with uid = 125.
rescanning insn with uid = 127.
deleting insn with uid = 127.
rescanning insn with uid = 129.
deleting insn with uid = 129.
rescanning insn with uid = 131.
deleting insn with uid = 131.
rescanning insn with uid = 133.
deleting insn with uid = 133.
rescanning insn with uid = 135.
deleting insn with uid = 135.
rescanning insn with uid = 137.
deleting insn with uid = 137.
rescanning insn with uid = 139.
deleting insn with uid = 139.
rescanning insn with uid = 140.
deleting insn with uid = 140.
rescanning insn with uid = 141.
deleting insn with uid = 141.
rescanning insn with uid = 143.
deleting insn with uid = 143.
rescanning insn with uid = 145.
deleting insn with uid = 145.
rescanning insn with uid = 147.
deleting insn with uid = 147.
rescanning insn with uid = 149.
deleting insn with uid = 149.
rescanning insn with uid = 151.
deleting insn with uid = 151.
rescanning insn with uid = 155.
deleting insn with uid = 155.
rescanning insn with uid = 157.
deleting insn with uid = 157.
rescanning insn with uid = 164.
deleting insn with uid = 164.
rescanning insn with uid = 166.
deleting insn with uid = 166.
rescanning insn with uid = 172.
deleting insn with uid = 172.
rescanning insn with uid = 174.
deleting insn with uid = 174.
rescanning insn with uid = 175.
deleting insn with uid = 175.
rescanning insn with uid = 190.
deleting insn with uid = 190.
rescanning insn with uid = 191.
deleting insn with uid = 191.
rescanning insn with uid = 193.
deleting insn with uid = 193.
ending the processing of deferred insns
(note 71 0 77 NOTE_INSN_DELETED)
(note 77 71 357 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 357 77 358 2 (parallel [
(set (mem/c:BLK (pre_modify:SI (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -32 [0xffffffffffffffe0]))) [3 A8])
(unspec:BLK [
(reg:SI 4 r4)
] UNSPEC_PUSH_MULT))
(use (reg:SI 5 r5))
(use (reg:SI 6 r6))
(use (reg:SI 7 r7))
(use (reg:SI 8 r8))
(use (reg:SI 9 r9))
(use (reg:SI 10 sl))
(use (reg:SI 11 fp))
]) /tmp/x.c:13 317 {*push_multi}
(expr_list:REG_DEAD (reg:SI 10 sl)
(expr_list:REG_DEAD (reg:SI 9 r9)
(expr_list:REG_DEAD (reg:SI 8 r8)
(expr_list:REG_DEAD (reg:SI 7 r7)
(expr_list:REG_DEAD (reg:SI 5 r5)
(expr_list:REG_DEAD (reg:SI 4 r4)
(expr_list:REG_FRAME_RELATED_EXPR (sequence [
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -32 [0xffffffffffffffe0])))
(set/f (mem/c:SI (reg/f:SI 13 sp) [3 S4 A32])
(reg:SI 4 r4))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [3 S4 A32])
(reg:SI 5 r5))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [3 S4 A32])
(reg:SI 6 r6))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 12 [0xc])) [3 S4 A32])
(reg:SI 7 r7))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 16 [0x10])) [3 S4 A32])
(reg:SI 8 r8))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 20 [0x14])) [3 S4 A32])
(reg:SI 9 r9))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 24 [0x18])) [3 S4 A32])
(reg:SI 10 sl))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 28 [0x1c])) [3 S4 A32])
(reg:SI 11 fp))
])
(nil)))))))))
(note 358 357 75 2 NOTE_INSN_PROLOGUE_END)
(note 75 358 82 2 NOTE_INSN_FUNCTION_BEG)
(note 82 75 83 2 NOTE_INSN_DELETED)
(note 83 82 86 2 NOTE_INSN_DELETED)
(note 86 83 91 2 NOTE_INSN_DELETED)
(note 91 86 92 2 NOTE_INSN_DELETED)
(note 92 91 95 2 NOTE_INSN_DELETED)
(note 95 92 101 2 NOTE_INSN_DELETED)
(note 101 95 102 2 NOTE_INSN_DELETED)
(note 102 101 103 2 NOTE_INSN_DELETED)
(note 103 102 80 2 NOTE_INSN_DELETED)
(insn 80 103 85 2 (set (reg/f:SI 12 ip [orig:227 D.6457 ] [227])
(plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(const_int 80 [0x50]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 85 80 94 2 (set (reg/f:SI 5 r5 [292])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 192 [0xc0]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 94 85 79 2 (set (reg/f:SI 4 r4 [299])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 192 [0xc0]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 79 94 351 2 (set (reg/f:SI 3 r3 [orig:223 vect_p.31 ] [223])
(plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(const_int 48 [0x30]))) 4 {*arm_addsi3}
(nil))
(insn 351 79 352 2 (set (reg:CC 24 cc)
(compare:CC (reg/f:SI 12 ip [orig:227 D.6457 ] [227])
(reg/f:SI 5 r5 [292]))) /tmp/x.c:10 206 {*arm_cmpsi_insn}
(nil))
(insn 352 351 353 2 (cond_exec (gtu (reg:CC 24 cc)
(const_int 0 [0]))
(set (reg:SI 6 r6 [294])
(const_int 0 [0]))) /tmp/x.c:10 3177 {*p *arm_movsi_vfp}
(nil))
(insn 353 352 354 2 (cond_exec (leu (reg:CC 24 cc)
(const_int 0 [0]))
(set (reg:SI 6 r6 [294])
(const_int 1 [0x1]))) /tmp/x.c:10 3177 {*p *arm_movsi_vfp}
(expr_list:REG_DEAD (reg:CC 24 cc)
(nil)))
(insn 354 353 355 2 (set (reg:CC 24 cc)
(compare:CC (reg/f:SI 12 ip [orig:227 D.6457 ] [227])
(reg/f:SI 4 r4 [299]))) /tmp/x.c:10 206 {*arm_cmpsi_insn}
(nil))
(insn 355 354 356 2 (cond_exec (gtu (reg:CC 24 cc)
(const_int 0 [0]))
(set (reg:SI 12 ip [301])
(const_int 0 [0]))) /tmp/x.c:10 3177 {*p *arm_movsi_vfp}
(nil))
(insn 356 355 81 2 (cond_exec (leu (reg:CC 24 cc)
(const_int 0 [0]))
(set (reg:SI 12 ip [301])
(const_int 1 [0x1]))) /tmp/x.c:10 3177 {*p *arm_movsi_vfp}
(expr_list:REG_DEAD (reg:CC 24 cc)
(nil)))
(insn 81 356 90 2 (set (reg/f:SI 8 r8 [289])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 320 [0x140]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 90 81 89 2 (set (reg/f:SI 7 r7 [296])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 320 [0x140]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 89 90 98 2 (parallel [
(set (reg:SI 6 r6 [295])
(ior:SI (geu:SI (reg/f:SI 3 r3 [orig:223 vect_p.31 ] [223])
(reg/f:SI 8 r8 [289]))
(reg:SI 6 r6 [294])))
(clobber (reg:CC 24 cc))
]) /tmp/x.c:10 269 {*cond_arith}
(expr_list:REG_DEAD (reg/f:SI 8 r8 [289])
(expr_list:REG_UNUSED (reg:CC 24 cc)
(nil))))
(insn 98 89 104 2 (parallel [
(set (reg:SI 12 ip [302])
(ior:SI (geu:SI (reg/f:SI 3 r3 [orig:223 vect_p.31 ] [223])
(reg/f:SI 7 r7 [296]))
(reg:SI 12 ip [301])))
(clobber (reg:CC 24 cc))
]) /tmp/x.c:10 269 {*cond_arith}
(expr_list:REG_DEAD (reg/f:SI 7 r7 [296])
(expr_list:REG_UNUSED (reg:CC 24 cc)
(nil))))
(insn 104 98 105 2 (parallel [
(set (reg:CC_NOOV 24 cc)
(compare:CC_NOOV (and:SI (reg:SI 6 r6 [295])
(reg:SI 12 ip [302]))
(const_int 0 [0])))
(clobber (scratch:SI))
]) 78 {*andsi3_compare0_scratch}
(expr_list:REG_DEAD (reg:SI 12 ip [302])
(expr_list:REG_DEAD (reg:SI 6 r6 [295])
(nil))))
(jump_insn 105 104 106 2 (set (pc)
(if_then_else (eq (reg:CC_NOOV 24 cc)
(const_int 0 [0]))
(label_ref 183)
(pc))) 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC_NOOV 24 cc)
(expr_list:REG_BR_PROB (const_int 2000 [0x7d0])
(nil)))
-> 183)
(note 106 105 117 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 117 106 126 3 (set (reg/f:SI 10 sl [319])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 208 [0xd0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 126 117 134 3 (set (reg/f:SI 7 r7 [328])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 224 [0xe0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 134 126 111 3 (set (reg/f:SI 6 r6 [336])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 240 [0xf0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 111 134 110 3 (set (reg:V4SI 95 d16 [313])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
])) /tmp/x.c:16 754 {*neon_movv4si}
(expr_list:REG_EQUIV (const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
])
(nil)))
(insn 110 111 115 3 (set (reg:V4SI 99 d18 [310])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 5 r5 [292]) [2 MEM[(uint32_t *)arg2_13(D) + 192B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 5 r5 [292])
(nil)))
(insn 115 110 112 3 (set (reg/f:SI 9 r9 [317])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 208 [0xd0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 112 115 124 3 (set (reg:V4SI 67 s4 [312])
(and:V4SI (reg:V4SI 99 d18 [310])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 115 d26 [310])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 124 112 118 3 (set (reg/f:SI 12 ip [326])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 224 [0xe0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 118 124 132 3 (set (reg:V4SI 71 s8 [318])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 10 sl [319]) [2 MEM[(uint32_t *)arg2_13(D) + 208B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 8 r8 [319])
(nil)))
(insn 132 118 120 3 (set (reg/f:SI 10 sl [334])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 240 [0xf0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 120 132 146 3 (set (reg:V4SI 63 s0 [320])
(and:V4SI (reg:V4SI 71 s8 [318])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 103 d20 [318])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 146 120 127 3 (set (reg/f:SI 8 r8 [347])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 256 [0x100]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 127 146 113 3 (set (reg:V4SI 111 d24 [327])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 7 r7 [328]) [2 MEM[(uint32_t *)arg2_13(D) + 224B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 7 r7 [328])
(nil)))
(insn 113 127 129 3 (set (reg:V4SI 75 s12 [315])
(neg:V4SI (reg:V4SI 67 s4 [312]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 129 113 154 3 (set (reg:V4SI 119 d28 [329])
(and:V4SI (reg:V4SI 111 d24 [327])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 119 d28 [327])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 154 129 135 3 (set (reg/f:SI 7 r7 [355])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 272 [0x110]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 135 154 121 3 (set (reg:V4SI 115 d26 [335])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 6 r6 [336]) [2 MEM[(uint32_t *)arg2_13(D) + 240B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 6 r6 [336])
(nil)))
(insn 121 135 137 3 (set (reg:V4SI 123 d30 [323])
(neg:V4SI (reg:V4SI 63 s0 [320]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 137 121 163 3 (set (reg:V4SI 107 d22 [337])
(and:V4SI (reg:V4SI 115 d26 [335])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 107 d22 [335])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 163 137 130 3 (set (reg/f:SI 6 r6 [364])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 288 [0x120]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 130 163 108 3 (set (reg:V4SI 119 d28 [332])
(neg:V4SI (reg:V4SI 119 d28 [329]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 108 130 171 3 (set (reg:V4SI 103 d20 [308])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 4 r4 [299]) [2 MEM[(int32_t *)arg1_8(D) + 192B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 4 r4 [299])
(nil)))
(insn 171 108 144 3 (set (reg/f:SI 2 r2 [372])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 304 [0x130]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 144 171 138 3 (set (reg/f:SI 5 r5 [345])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 256 [0x100]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 138 144 116 3 (set (reg:V4SI 107 d22 [340])
(neg:V4SI (reg:V4SI 107 d22 [337]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 116 138 114 3 (set (reg:V4SI 99 d18 [316])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 9 r9 [317]) [2 MEM[(int32_t *)arg1_8(D) + 208B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 114 116 152 3 (set (reg:V4SI 75 s12 [314])
(unspec:V4SI [
(reg:V4SI 103 d20 [308])
(reg:V4SI 75 s12 [315])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 111 d24 [308])
(reg:V4SI 115 d26 [312]))
(nil)))
(insn 152 114 125 3 (set (reg/f:SI 4 r4 [353])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 272 [0x110]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 125 152 161 3 (set (reg:V4SI 71 s8 [325])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 12 ip [326]) [2 MEM[(int32_t *)arg1_8(D) + 224B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 12 ip [326])
(nil)))
(insn 161 125 122 3 (set (reg/f:SI 12 ip [362])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 288 [0x120]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 122 161 169 3 (set (reg:V4SI 115 d26 [322])
(unspec:V4SI [
(reg:V4SI 99 d18 [316])
(reg:V4SI 123 d30 [323])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 99 d18 [316])
(reg:V4SI 103 d20 [320]))
(nil)))
(insn 169 122 133 3 (set (reg/f:SI 1 r1 [370])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 304 [0x130]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 133 169 179 3 (set (reg:V4SI 67 s4 [333])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 10 sl [334]) [2 MEM[(int32_t *)arg1_8(D) + 240B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 179 133 131 3 (set (reg/f:SI 0 r0 [379])
(plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(const_int 64 [0x40]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 131 179 139 3 (set (reg:V4SI 111 d24 [331])
(unspec:V4SI [
(reg:V4SI 71 s8 [325])
(reg:V4SI 119 d28 [332])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 111 d24 [325])
(reg:V4SI 119 d28 [329]))
(nil)))
(insn 139 131 123 3 (set (reg:V4SI 67 s4 [339])
(unspec:V4SI [
(reg:V4SI 67 s4 [333])
(reg:V4SI 107 d22 [340])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 99 d18 [333])
(reg:V4SI 107 d22 [337]))
(nil)))
(insn 123 139 140 3 (set (reg:V8HI 99 d18 [324])
(vec_concat:V8HI (truncate:V4HI (reg:V4SI 75 s12 [314]))
(truncate:V4HI (reg:V4SI 115 d26 [322])))) /tmp/x.c:16 1775 {vec_pack_trunc_v4si}
(nil))
(insn 140 123 141 3 (set (reg:V8HI 103 d20 [341])
(vec_concat:V8HI (truncate:V4HI (reg:V4SI 111 d24 [331]))
(truncate:V4HI (reg:V4SI 67 s4 [339])))) /tmp/x.c:16 1775 {vec_pack_trunc_v4si}
(nil))
(insn 141 140 143 3 (set (reg:V16QI 71 s8 [342])
(vec_concat:V16QI (truncate:V8QI (reg:V8HI 99 d18 [324]))
(truncate:V8QI (reg:V8HI 115 d26 [341])))) /tmp/x.c:16 1774 {vec_pack_trunc_v8hi}
(nil))
(insn 143 141 147 3 (set (mem:V16QI (reg/f:SI 3 r3 [orig:223 vect_p.31 ] [223]) [0 MEM[(int8_t *)result_4(D) + 48B]+0 S16 A8])
(unspec:V16QI [
(reg:V16QI 71 s8 [342])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 772 {*movmisalignv16qi_neon_store}
(expr_list:REG_DEAD (reg/f:SI 3 r3 [orig:223 vect_p.31 ] [223])
(nil)))
(insn 147 143 149 3 (set (reg:V4SI 63 s0 [346])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 8 r8 [347]) [2 MEM[(uint32_t *)arg2_13(D) + 256B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 149 147 155 3 (set (reg:V4SI 111 d24 [348])
(and:V4SI (reg:V4SI 63 s0 [346])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 111 d24 [346])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 155 149 157 3 (set (reg:V4SI 123 d30 [354])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 7 r7 [355]) [2 MEM[(uint32_t *)arg2_13(D) + 272B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 157 155 164 3 (set (reg:V4SI 103 d20 [356])
(and:V4SI (reg:V4SI 123 d30 [354])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 103 d20 [354])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 164 157 150 3 (set (reg:V4SI 63 s0 [363])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 6 r6 [364]) [2 MEM[(uint32_t *)arg2_13(D) + 288B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 150 164 166 3 (set (reg:V4SI 111 d24 [351])
(neg:V4SI (reg:V4SI 111 d24 [348]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 166 150 172 3 (set (reg:V4SI 115 d26 [365])
(and:V4SI (reg:V4SI 63 s0 [363])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 115 d26 [363])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 172 166 158 3 (set (reg:V4SI 123 d30 [371])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 2 r2 [372]) [2 MEM[(uint32_t *)arg2_13(D) + 304B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 2 r2 [372])
(nil)))
(insn 158 172 174 3 (set (reg:V4SI 103 d20 [359])
(neg:V4SI (reg:V4SI 103 d20 [356]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 174 158 167 3 (set (reg:V4SI 75 s12 [373])
(and:V4SI (reg:V4SI 123 d30 [371])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 107 d22 [371])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 167 174 145 3 (set (reg:V4SI 115 d26 [368])
(neg:V4SI (reg:V4SI 115 d26 [365]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 145 167 175 3 (set (reg:V4SI 63 s0 [344])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 5 r5 [345]) [2 MEM[(int32_t *)arg1_8(D) + 256B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 175 145 153 3 (set (reg:V4SI 95 d16 [376])
(neg:V4SI (reg:V4SI 75 s12 [373]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 153 175 151 3 (set (reg:V4SI 99 d18 [352])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 4 r4 [353]) [2 MEM[(int32_t *)arg1_8(D) + 272B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 151 153 162 3 (set (reg:V4SI 111 d24 [350])
(unspec:V4SI [
(reg:V4SI 63 s0 [344])
(reg:V4SI 111 d24 [351])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 107 d22 [344])
(reg:V4SI 111 d24 [348]))
(nil)))
(insn 162 151 159 3 (set (reg:V4SI 107 d22 [361])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 12 ip [362]) [2 MEM[(int32_t *)arg1_8(D) + 288B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 12 ip [362])
(nil)))
(insn 159 162 170 3 (set (reg:V4SI 99 d18 [358])
(unspec:V4SI [
(reg:V4SI 99 d18 [352])
(reg:V4SI 103 d20 [359])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 99 d18 [352])
(reg:V4SI 103 d20 [356]))
(nil)))
(insn 170 159 168 3 (set (reg:V4SI 103 d20 [369])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 1 r1 [370]) [2 MEM[(int32_t *)arg1_8(D) + 304B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 1 r1 [370])
(nil)))
(insn 168 170 176 3 (set (reg:V4SI 107 d22 [367])
(unspec:V4SI [
(reg:V4SI 107 d22 [361])
(reg:V4SI 115 d26 [368])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 107 d22 [361])
(reg:V4SI 115 d26 [365]))
(nil)))
(insn 176 168 160 3 (set (reg:V4SI 95 d16 [375])
(unspec:V4SI [
(reg:V4SI 103 d20 [369])
(reg:V4SI 95 d16 [376])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 103 d20 [369])
(reg:V4SI 95 d16 [373]))
(nil)))
(insn 160 176 177 3 (set (reg:V8HI 103 d20 [360])
(vec_concat:V8HI (truncate:V4HI (reg:V4SI 111 d24 [350]))
(truncate:V4HI (reg:V4SI 99 d18 [358])))) /tmp/x.c:16 1775 {vec_pack_trunc_v4si}
(nil))
(insn 177 160 178 3 (set (reg:V8HI 99 d18 [377])
(vec_concat:V8HI (truncate:V4HI (reg:V4SI 107 d22 [367]))
(truncate:V4HI (reg:V4SI 95 d16 [375])))) /tmp/x.c:16 1775 {vec_pack_trunc_v4si}
(nil))
(insn 178 177 180 3 (set (reg:V16QI 95 d16 [378])
(vec_concat:V16QI (truncate:V8QI (reg:V8HI 103 d20 [360]))
(truncate:V8QI (reg:V8HI 99 d18 [377])))) /tmp/x.c:16 1774 {vec_pack_trunc_v8hi}
(nil))
(insn 180 178 346 3 (set (mem:V16QI (reg/f:SI 0 r0 [379]) [0 MEM[(int8_t *)result_4(D) + 64B]+0 S16 A8])
(unspec:V16QI [
(reg:V16QI 95 d16 [378])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 772 {*movmisalignv16qi_neon_store}
(expr_list:REG_DEAD (reg/f:SI 0 r0 [379])
(nil)))
(jump_insn 346 180 347 3 (set (pc)
(label_ref 202)) 230 {*arm_jump}
(nil)
-> 202)
(barrier 347 346 183)
(code_label 183 347 184 4 2 "" [1 uses])
(note 184 183 185 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 185 184 186 4 (set (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 188 [0xbc]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 186 185 76 4 (set (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 188 [0xbc]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 76 186 197 4 (set (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 48 [0x30])) /tmp/x.c:15 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const_int 48 [0x30])
(nil)))
(code_label 197 76 187 5 4 "" [1 uses])
(note 187 197 335 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(note 335 187 336 5 NOTE_INSN_DELETED)
(note 336 335 190 5 NOTE_INSN_DELETED)
(insn 190 336 337 5 (set (reg:SI 6 r6 [orig:381 MEM[base: D.6528_147, offset: 0B] ] [381])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 4 [0x4])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 4 [0x4])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 337 190 192 5 (set (reg:SI 12 ip [387])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 1 [0x1]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 192 337 238 5 (set (reg:SI 5 r5 [orig:383 MEM[base: D.6527_146, offset: 0B] ] [383])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 4 [0x4])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 4 [0x4])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 238 192 191 5 (set (reg/v:SI 10 sl [orig:398 idx ] [398])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 2 [0x2]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 191 238 253 5 (set (reg:SI 11 fp [380])
(and:SI (reg:SI 6 r6 [orig:381 MEM[base: D.6528_147, offset: 0B] ] [381])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 253 191 268 5 (set (reg/v:SI 8 r8 [orig:405 idx ] [405])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 3 [0x3]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 268 253 283 5 (set (reg/v:SI 7 r7 [orig:412 idx ] [412])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 4 [0x4]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 283 268 193 5 (set (reg/v:SI 6 r6 [orig:419 idx ] [419])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 5 [0x5]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 193 283 195 5 (set (reg:SI 4 r4 [382])
(ashiftrt:SI (reg:SI 5 r5 [orig:383 MEM[base: D.6527_146, offset: 0B] ] [383])
(reg:SI 11 fp [380]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(expr_list:REG_DEAD (reg:SI 5 r5 [orig:383 MEM[base: D.6527_146, offset: 0B] ] [383])
(nil)))
(insn 195 193 233 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 3 r3 [orig:235 idx ] [235])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 4 r4 [382])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 4 r4 [382])
(nil)))
(insn 233 195 298 5 (set (reg:SI 9 r9 [orig:394 MEM[base: D.6528_147, offset: 0B] ] [394])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 8 [0x8])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 8 [0x8])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 298 233 235 5 (set (reg/v:SI 5 r5 [orig:426 idx ] [426])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 6 [0x6]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 235 298 313 5 (set (reg:SI 11 fp [orig:396 MEM[base: D.6527_146, offset: 0B] ] [396])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 8 [0x8])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 8 [0x8])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 313 235 234 5 (set (reg/v:SI 4 r4 [orig:433 idx ] [433])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 7 [0x7]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 234 313 328 5 (set (reg:SI 9 r9 [395])
(and:SI (reg:SI 9 r9 [orig:394 MEM[base: D.6528_147, offset: 0B] ] [394])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 328 234 329 5 (set (reg/v:SI 3 r3 [orig:235 idx ] [235])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 8 [0x8]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 329 328 236 5 (set (reg:CC 24 cc)
(compare:CC (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 80 [0x50]))) /tmp/x.c:15 206 {*arm_cmpsi_insn}
(nil))
(insn 236 329 237 5 (set (reg:SI 9 r9 [397])
(ashiftrt:SI (reg:SI 11 fp [orig:396 MEM[base: D.6527_146, offset: 0B] ] [396])
(reg:SI 9 r9 [395]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 237 236 248 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg:SI 12 ip [387])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 9 r9 [397])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:SI 12 ip [387])
(expr_list:REG_DEAD (reg:QI 9 r9 [397])
(nil))))
(insn 248 237 250 5 (set (reg:SI 12 ip [orig:401 MEM[base: D.6528_147, offset: 0B] ] [401])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 12 [0xc])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 12 [0xc])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 250 248 249 5 (set (reg:SI 9 r9 [orig:403 MEM[base: D.6527_146, offset: 0B] ] [403])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 12 [0xc])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 12 [0xc])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 249 250 251 5 (set (reg:SI 12 ip [402])
(and:SI (reg:SI 12 ip [orig:401 MEM[base: D.6528_147, offset: 0B] ] [401])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 251 249 252 5 (set (reg:SI 12 ip [404])
(ashiftrt:SI (reg:SI 9 r9 [orig:403 MEM[base: D.6527_146, offset: 0B] ] [403])
(reg:SI 12 ip [402]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 252 251 263 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 10 sl [orig:398 idx ] [398])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [404])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [404])
(expr_list:REG_DEAD (reg/v:SI 10 sl [orig:398 idx ] [398])
(nil))))
(insn 263 252 265 5 (set (reg:SI 12 ip [orig:408 MEM[base: D.6528_147, offset: 0B] ] [408])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 16 [0x10])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 16 [0x10])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 265 263 264 5 (set (reg:SI 10 sl [orig:410 MEM[base: D.6527_146, offset: 0B] ] [410])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 16 [0x10])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 16 [0x10])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 264 265 266 5 (set (reg:SI 12 ip [409])
(and:SI (reg:SI 12 ip [orig:408 MEM[base: D.6528_147, offset: 0B] ] [408])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 266 264 267 5 (set (reg:SI 12 ip [411])
(ashiftrt:SI (reg:SI 10 sl [orig:410 MEM[base: D.6527_146, offset: 0B] ] [410])
(reg:SI 12 ip [409]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 267 266 278 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 8 r8 [orig:405 idx ] [405])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [411])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [411])
(expr_list:REG_DEAD (reg/v:SI 8 r8 [orig:405 idx ] [405])
(nil))))
(insn 278 267 280 5 (set (reg:SI 12 ip [orig:415 MEM[base: D.6528_147, offset: 0B] ] [415])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 20 [0x14])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 20 [0x14])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 280 278 279 5 (set (reg:SI 8 r8 [orig:417 MEM[base: D.6527_146, offset: 0B] ] [417])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 20 [0x14])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 20 [0x14])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 279 280 281 5 (set (reg:SI 12 ip [416])
(and:SI (reg:SI 12 ip [orig:415 MEM[base: D.6528_147, offset: 0B] ] [415])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 281 279 282 5 (set (reg:SI 12 ip [418])
(ashiftrt:SI (reg:SI 8 r8 [orig:417 MEM[base: D.6527_146, offset: 0B] ] [417])
(reg:SI 12 ip [416]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 282 281 293 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 7 r7 [orig:412 idx ] [412])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [418])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [418])
(expr_list:REG_DEAD (reg/v:SI 7 r7 [orig:412 idx ] [412])
(nil))))
(insn 293 282 295 5 (set (reg:SI 12 ip [orig:422 MEM[base: D.6528_147, offset: 0B] ] [422])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 24 [0x18])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 24 [0x18])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 295 293 294 5 (set (reg:SI 7 r7 [orig:424 MEM[base: D.6527_146, offset: 0B] ] [424])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 24 [0x18])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 24 [0x18])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 294 295 296 5 (set (reg:SI 12 ip [423])
(and:SI (reg:SI 12 ip [orig:422 MEM[base: D.6528_147, offset: 0B] ] [422])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 296 294 297 5 (set (reg:SI 12 ip [425])
(ashiftrt:SI (reg:SI 7 r7 [orig:424 MEM[base: D.6527_146, offset: 0B] ] [424])
(reg:SI 12 ip [423]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 297 296 308 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 6 r6 [orig:419 idx ] [419])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [425])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [425])
(expr_list:REG_DEAD (reg/v:SI 6 r6 [orig:419 idx ] [419])
(nil))))
(insn 308 297 310 5 (set (reg:SI 12 ip [orig:429 MEM[base: D.6528_147, offset: 0B] ] [429])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 28 [0x1c])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 28 [0x1c])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 310 308 309 5 (set (reg:SI 6 r6 [orig:431 MEM[base: D.6527_146, offset: 0B] ] [431])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 28 [0x1c])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 28 [0x1c])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 309 310 311 5 (set (reg:SI 12 ip [430])
(and:SI (reg:SI 12 ip [orig:429 MEM[base: D.6528_147, offset: 0B] ] [429])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 311 309 312 5 (set (reg:SI 12 ip [432])
(ashiftrt:SI (reg:SI 6 r6 [orig:431 MEM[base: D.6527_146, offset: 0B] ] [431])
(reg:SI 12 ip [430]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 312 311 323 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 5 r5 [orig:426 idx ] [426])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [432])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [432])
(expr_list:REG_DEAD (reg/v:SI 5 r5 [orig:426 idx ] [426])
(nil))))
(insn 323 312 325 5 (set (reg:SI 12 ip [orig:434 MEM[base: D.6528_147, offset: 0B] ] [434])
(mem:SI (pre_modify:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 32 [0x20]))) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_INC (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(nil)))
(insn 325 323 324 5 (set (reg:SI 5 r5 [orig:436 MEM[base: D.6527_146, offset: 0B] ] [436])
(mem:SI (pre_modify:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 32 [0x20]))) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_INC (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(nil)))
(insn 324 325 326 5 (set (reg:SI 12 ip [435])
(and:SI (reg:SI 12 ip [orig:434 MEM[base: D.6528_147, offset: 0B] ] [434])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 326 324 327 5 (set (reg:SI 12 ip [437])
(ashiftrt:SI (reg:SI 5 r5 [orig:436 MEM[base: D.6527_146, offset: 0B] ] [436])
(reg:SI 12 ip [435]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 327 326 330 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 4 r4 [orig:433 idx ] [433])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [437])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [437])
(nil)))
(jump_insn 330 327 202 5 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 197)
(pc))) /tmp/x.c:15 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 9688 [0x25d8])
(nil)))
-> 197)
(code_label 202 330 203 6 1 "" [1 uses])
(note 203 202 359 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(note 359 203 360 6 NOTE_INSN_EPILOGUE_BEG)
(jump_insn 360 359 361 6 (unspec_volatile [
(return)
] VUNSPEC_EPILOGUE) /tmp/x.c:18 313 {*epilogue_insns}
(nil)
-> return)
(barrier 361 360 348)
(note 348 361 349 NOTE_INSN_DELETED)
(note 349 348 0 NOTE_INSN_DELETED)
;; Function main (main, funcdef_no=1, decl_uid=4794, cgraph_uid=1) (executed once)
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
Basic block 2:
Creating chain sp (0) at insn 325
Creating chain r0 (1) at insn 12
Creating chain r1 (2) at insn 13
Creating chain r2 (3) at insn 14
Cannot rename chain r2 (3) at insn 15 (mark_all_read)
Cannot rename chain r1 (2) at insn 15 (mark_all_read)
Cannot rename chain r0 (1) at insn 15 (mark_all_read)
Closing chain r2 (3) at insn 15 (terminate_dead, superset)
Closing chain r1 (2) at insn 15 (terminate_dead, superset)
Closing chain r0 (1) at insn 15 (terminate_write, superset)
Creating chain r0 (4) at insn 78
Creating chain r1 (5) at insn 80
Creating chain r2 (6) at insn 3
Creating chain r3 (7) at insn 4
Register r0 (1): 12 [CORE_REGS]
Register r1 (1): 13 [CORE_REGS]
Register r2 (1): 14 [GENERAL_REGS]
Basic block 3:
Creating chain lr (0) at insn 306
Creating chain ip (1) at insn 305
Closing chain lr (0) at insn 211 (terminate_dead, superset)
Closing chain ip (1) at insn 211 (terminate_dead, superset)
Creating chain lr (2) at insn 214
Creating chain ip (3) at insn 213
Closing chain lr (2) at insn 225 (terminate_dead, superset)
Closing chain ip (3) at insn 225 (terminate_dead, superset)
Creating chain ip (4) at insn 228
Creating chain lr (5) at insn 227
Closing chain lr (5) at insn 239 (terminate_dead, superset)
Closing chain ip (4) at insn 239 (terminate_dead, superset)
Creating chain ip (6) at insn 242
Creating chain lr (7) at insn 241
Closing chain lr (7) at insn 253 (terminate_dead, superset)
Closing chain ip (6) at insn 253 (terminate_dead, superset)
Creating chain ip (8) at insn 256
Creating chain lr (9) at insn 255
Closing chain lr (9) at insn 267 (terminate_dead, superset)
Closing chain ip (8) at insn 267 (terminate_dead, superset)
Creating chain ip (10) at insn 270
Creating chain lr (11) at insn 269
Closing chain lr (11) at insn 281 (terminate_dead, superset)
Closing chain ip (10) at insn 281 (terminate_dead, superset)
Creating chain ip (12) at insn 284
Creating chain lr (13) at insn 283
Closing chain lr (13) at insn 295 (terminate_dead, superset)
Closing chain ip (12) at insn 295 (terminate_dead, superset)
Creating chain r3 (14) at insn 297
Creating chain r2 (15) at insn 298
Register ip (1): 284 [GENERAL_REGS] 293 [CORE_REGS] 295 [CORE_REGS]
Register lr (1): 283 [GENERAL_REGS] 293 [CORE_REGS] 295 [CORE_REGS]
Register ip (1): 270 [GENERAL_REGS] 279 [CORE_REGS] 281 [CORE_REGS]
Register lr (1): 269 [GENERAL_REGS] 279 [CORE_REGS] 281 [CORE_REGS]
Register ip (1): 256 [GENERAL_REGS] 265 [CORE_REGS] 267 [CORE_REGS]
Register lr (1): 255 [GENERAL_REGS] 265 [CORE_REGS] 267 [CORE_REGS]
Register ip (1): 242 [GENERAL_REGS] 251 [CORE_REGS] 253 [CORE_REGS]
Register lr (1): 241 [GENERAL_REGS] 251 [CORE_REGS] 253 [CORE_REGS]
Register ip (1): 228 [GENERAL_REGS] 237 [CORE_REGS] 239 [CORE_REGS]
Register lr (1): 227 [GENERAL_REGS] 237 [CORE_REGS] 239 [CORE_REGS]
Register ip (1): 213 [GENERAL_REGS] 223 [CORE_REGS] 225 [CORE_REGS]
Register lr (1): 214 [GENERAL_REGS] 223 [CORE_REGS] 225 [CORE_REGS]
Register ip (1): 305 [GENERAL_REGS] 209 [CORE_REGS] 211 [CORE_REGS]
Register lr (1): 306 [GENERAL_REGS] 209 [GENERAL_REGS] 211 [GENERAL_REGS]
Register ip in insn 284; no available better choice
Register lr in insn 283; no available better choice
Register ip in insn 270, renamed as r4
deferring rescan insn with uid = 270.
deferring rescan insn with uid = 279.
deferring rescan insn with uid = 281.
Register lr in insn 269, renamed as r5
deferring rescan insn with uid = 269.
deferring rescan insn with uid = 279.
deferring rescan insn with uid = 281.
Register ip in insn 256; no available better choice
Register lr in insn 255; no available better choice
Register ip in insn 242, renamed as r4
deferring rescan insn with uid = 242.
deferring rescan insn with uid = 251.
deferring rescan insn with uid = 253.
Register lr in insn 241, renamed as r5
deferring rescan insn with uid = 241.
deferring rescan insn with uid = 251.
deferring rescan insn with uid = 253.
Register ip in insn 228; no available better choice
Register lr in insn 227; no available better choice
Register ip in insn 213, renamed as r4
deferring rescan insn with uid = 213.
deferring rescan insn with uid = 223.
deferring rescan insn with uid = 225.
Register lr in insn 214, renamed as r5
deferring rescan insn with uid = 214.
deferring rescan insn with uid = 223.
deferring rescan insn with uid = 225.
Register ip in insn 305; no available better choice
Register lr in insn 306; no available better choice
Basic block 4:
Creating chain r0 (0) at insn 39
Creating chain r1 (1) at insn 40
Creating chain r2 (2) at insn 41
Cannot rename chain r2 (2) at insn 42 (mark_all_read)
Cannot rename chain r1 (1) at insn 42 (mark_all_read)
Cannot rename chain r0 (0) at insn 42 (mark_all_read)
Closing chain r2 (2) at insn 42 (terminate_dead, superset)
Closing chain r1 (1) at insn 42 (terminate_dead, superset)
Closing chain r0 (0) at insn 42 (terminate_dead, superset)
Creating chain r3 (3) at insn 43
Creating chain r2 (4) at insn 45
Creating chain ip (5) at insn 48
Register r0 (1): 39 [CORE_REGS]
Register r1 (1): 40 [CORE_REGS]
Register r2 (1): 41 [CORE_REGS]
Basic block 5:
Creating chain r5 (0) at insn 52
Creating chain r0 (1) at insn 197
Creating chain r4 (2) at insn 53
Creating chain r1 (3) at insn 198
Basic block 6:
Basic block 7:
Creating chain r0 (0) at insn 88
Creating chain r1 (1) at insn 89
Closing chain r1 (1) at insn 90 (terminate_dead, superset)
Closing chain r0 (0) at insn 90 (terminate_dead, superset)
Register r0 (1): 88 [GENERAL_REGS] 90 [GENERAL_REGS]
Register r1 (1): 89 [CORE_REGS] 90 [GENERAL_REGS]
Register r0 in insn 88; no available better choice
Register r1 in insn 89; no available better choice
Basic block 8:
Basic block 9:
Creating chain r0 (0) at insn 69
Cannot rename chain r0 (0) at insn 72 (mark_all_read)
Basic block 10:
Creating chain r0 (0) at insn 104
Creating chain r1 (1) at insn 105
Closing chain r1 (1) at insn 106 (terminate_dead, superset)
Closing chain r0 (0) at insn 106 (terminate_dead, superset)
Register r0 (1): 104 [GENERAL_REGS] 106 [GENERAL_REGS]
Register r1 (1): 105 [CORE_REGS] 106 [GENERAL_REGS]
Register r0 in insn 104, renamed as lr
deferring rescan insn with uid = 104.
deferring rescan insn with uid = 106.
Register r1 in insn 105, renamed as r0
deferring rescan insn with uid = 105.
deferring rescan insn with uid = 106.
Basic block 11:
Creating chain r0 (0) at insn 120
Creating chain r1 (1) at insn 121
Closing chain r1 (1) at insn 122 (terminate_dead, superset)
Closing chain r0 (0) at insn 122 (terminate_dead, superset)
Register r0 (1): 120 [GENERAL_REGS] 122 [GENERAL_REGS]
Register r1 (1): 121 [CORE_REGS] 122 [GENERAL_REGS]
Register r0 in insn 120, renamed as lr
deferring rescan insn with uid = 120.
deferring rescan insn with uid = 122.
Register r1 in insn 121; no available better choice
Basic block 12:
Creating chain r0 (0) at insn 136
Creating chain r1 (1) at insn 137
Closing chain r1 (1) at insn 138 (terminate_dead, superset)
Closing chain r0 (0) at insn 138 (terminate_dead, superset)
Register r0 (1): 136 [GENERAL_REGS] 138 [GENERAL_REGS]
Register r1 (1): 137 [CORE_REGS] 138 [GENERAL_REGS]
Register r0 in insn 136; no available better choice
Register r1 in insn 137, renamed as lr
deferring rescan insn with uid = 137.
deferring rescan insn with uid = 138.
Basic block 13:
Creating chain r0 (0) at insn 152
Creating chain r1 (1) at insn 153
Closing chain r1 (1) at insn 154 (terminate_dead, superset)
Closing chain r0 (0) at insn 154 (terminate_dead, superset)
Register r0 (1): 152 [GENERAL_REGS] 154 [GENERAL_REGS]
Register r1 (1): 153 [CORE_REGS] 154 [GENERAL_REGS]
Register r0 in insn 152; no available better choice
Register r1 in insn 153; no available better choice
Basic block 14:
Creating chain r0 (0) at insn 168
Creating chain r1 (1) at insn 169
Closing chain r1 (1) at insn 170 (terminate_dead, superset)
Closing chain r0 (0) at insn 170 (terminate_dead, superset)
Register r0 (1): 168 [GENERAL_REGS] 170 [GENERAL_REGS]
Register r1 (1): 169 [CORE_REGS] 170 [GENERAL_REGS]
Register r0 in insn 168, renamed as lr
deferring rescan insn with uid = 168.
deferring rescan insn with uid = 170.
Register r1 in insn 169, renamed as r0
deferring rescan insn with uid = 169.
deferring rescan insn with uid = 170.
Basic block 15:
Creating chain r0 (0) at insn 184
Creating chain r1 (1) at insn 185
Closing chain r1 (1) at insn 186 (terminate_dead, superset)
Closing chain r0 (0) at insn 186 (terminate_dead, superset)
Register r0 (1): 184 [GENERAL_REGS] 186 [GENERAL_REGS]
Register r1 (1): 185 [CORE_REGS] 186 [GENERAL_REGS]
Register r0 in insn 184, renamed as lr
deferring rescan insn with uid = 184.
deferring rescan insn with uid = 186.
Register r1 in insn 185; no available better choice
Basic block 16:
Basic block 17:
starting the processing of deferred insns
rescanning insn with uid = 104.
deleting insn with uid = 104.
rescanning insn with uid = 105.
deleting insn with uid = 105.
rescanning insn with uid = 106.
deleting insn with uid = 106.
rescanning insn with uid = 120.
deleting insn with uid = 120.
rescanning insn with uid = 122.
deleting insn with uid = 122.
rescanning insn with uid = 137.
deleting insn with uid = 137.
rescanning insn with uid = 138.
deleting insn with uid = 138.
rescanning insn with uid = 168.
deleting insn with uid = 168.
rescanning insn with uid = 169.
deleting insn with uid = 169.
rescanning insn with uid = 170.
deleting insn with uid = 170.
rescanning insn with uid = 184.
deleting insn with uid = 184.
rescanning insn with uid = 186.
deleting insn with uid = 186.
rescanning insn with uid = 213.
deleting insn with uid = 213.
rescanning insn with uid = 214.
deleting insn with uid = 214.
rescanning insn with uid = 223.
deleting insn with uid = 223.
rescanning insn with uid = 225.
deleting insn with uid = 225.
rescanning insn with uid = 241.
deleting insn with uid = 241.
rescanning insn with uid = 242.
deleting insn with uid = 242.
rescanning insn with uid = 251.
deleting insn with uid = 251.
rescanning insn with uid = 253.
deleting insn with uid = 253.
rescanning insn with uid = 269.
deleting insn with uid = 269.
rescanning insn with uid = 270.
deleting insn with uid = 270.
rescanning insn with uid = 279.
deleting insn with uid = 279.
rescanning insn with uid = 281.
deleting insn with uid = 281.
ending the processing of deferred insns
(note 1 0 5 NOTE_INSN_DELETED)
(note 5 1 324 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 324 5 325 2 (parallel [
(set (mem/c:BLK (pre_modify:SI (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -12 [0xfffffffffffffff4]))) [3 A8])
(unspec:BLK [
(reg:SI 4 r4)
] UNSPEC_PUSH_MULT))
(use (reg:SI 5 r5))
(use (reg:SI 14 lr))
]) /tmp/x.c:25 317 {*push_multi}
(expr_list:REG_DEAD (reg:SI 14 lr)
(expr_list:REG_DEAD (reg:SI 5 r5)
(expr_list:REG_DEAD (reg:SI 4 r4)
(expr_list:REG_FRAME_RELATED_EXPR (sequence [
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -12 [0xfffffffffffffff4])))
(set/f (mem/c:SI (reg/f:SI 13 sp) [3 S4 A32])
(reg:SI 4 r4))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [3 S4 A32])
(reg:SI 5 r5))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [3 S4 A32])
(reg:SI 14 lr))
])
(nil))))))
(insn/f 325 324 326 2 (set (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -132 [0xffffffffffffff7c]))) /tmp/x.c:25 4 {*arm_addsi3}
(nil))
(note 326 325 2 2 NOTE_INSN_PROLOGUE_END)
(note 2 326 9 2 NOTE_INSN_FUNCTION_BEG)
(note 9 2 12 2 NOTE_INSN_DELETED)
(insn 12 9 13 2 (set (reg:SI 0 r0)
(reg/f:SI 13 sp)) /tmp/x.c:27 634 {*arm_movsi_vfp}
(nil))
(insn 13 12 14 2 (set (reg:SI 1 r1)
(symbol_ref:SI ("*.LANCHOR0") [flags 0x182])) /tmp/x.c:27 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (symbol_ref:SI ("*.LANCHOR0") [flags 0x182])
(nil)))
(insn 14 13 15 2 (set (reg:SI 2 r2)
(const_int 128 [0x80])) /tmp/x.c:27 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const_int 128 [0x80])
(nil)))
(call_insn 15 14 78 2 (parallel [
(set (reg:SI 0 r0)
(call (mem:SI (symbol_ref:SI ("memcpy") [flags 0x41] <function_decl 0xb7063b80 memcpy>) [0 memcpy S4 A32])
(const_int 0 [0])))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
]) /tmp/x.c:27 243 {*call_value_symbol}
(expr_list:REG_DEAD (reg:SI 2 r2)
(expr_list:REG_DEAD (reg:SI 1 r1)
(expr_list:REG_UNUSED (reg:SI 0 r0)
(expr_list:REG_EH_REGION (const_int 0 [0])
(nil)))))
(expr_list:REG_DEP_TRUE (use (reg:SI 2 r2))
(expr_list:REG_DEP_TRUE (use (reg:SI 1 r1))
(expr_list:REG_DEP_TRUE (use (reg:SI 0 r0))
(nil)))))
(insn 78 15 80 2 (set (reg/f:SI 0 r0 [170])
(symbol_ref:SI ("arg1") [flags 0x80] <var_decl 0xb7224f60 arg1>)) 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (symbol_ref:SI ("arg1") [flags 0x80] <var_decl 0xb7224f60 arg1>)
(nil)))
(insn 80 78 3 2 (set (reg/f:SI 1 r1 [171])
(symbol_ref:SI ("arg2") [flags 0x80] <var_decl 0xb723d120 arg2>)) 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (symbol_ref:SI ("arg2") [flags 0x80] <var_decl 0xb723d120 arg2>)
(nil)))
(insn 3 80 4 2 (set (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 0 [0])) /tmp/x.c:27 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const_int 0 [0])
(nil)))
(insn 4 3 29 2 (set (reg/v:SI 3 r3 [orig:137 i ] [137])
(reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])) /tmp/x.c:29 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const_int 0 [0])
(nil)))
(code_label 29 4 17 3 15 "" [1 uses])
(note 17 29 21 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 21 17 25 3 (set (mem:SI (plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 3 r3 [orig:137 i ] [137])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 25 21 26 3 (set (mem:SI (plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 3 r3 [orig:137 i ] [137])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 26 25 306 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 306 26 305 3 (set (reg:SI 14 lr [175])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 4 [0x4]))) 4 {*arm_addsi3}
(nil))
(insn 305 306 209 3 (set (reg:SI 12 ip [174])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 1 [0x1]))) /tmp/x.c:29 4 {*arm_addsi3}
(nil))
(insn 209 305 211 3 (set (mem:SI (plus:SI (reg/f:SI 0 r0 [170])
(reg:SI 14 lr [175])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg:SI 12 ip [174])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 211 209 212 3 (set (mem:SI (plus:SI (reg/f:SI 1 r1 [171])
(reg:SI 14 lr [175])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg:SI 12 ip [174])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 14 lr [175])
(expr_list:REG_DEAD (reg:SI 12 ip [174])
(nil))))
(insn 212 211 214 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 214 212 213 3 (set (reg:SI 5 r5 [orig:183 ivtmp.139 ] [183])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 8 [0x8]))) 4 {*arm_addsi3}
(nil))
(insn 213 214 223 3 (set (reg:SI 4 r4 [orig:182 i ] [182])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 2 [0x2]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 14 lr [orig:183 ivtmp.139 ] [183])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 223 213 225 3 (set (mem:SI (plus:SI (reg:SI 5 r5 [orig:183 ivtmp.139 ] [183])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg:SI 4 r4 [orig:182 i ] [182])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 225 223 226 3 (set (mem:SI (plus:SI (reg:SI 5 r5 [orig:183 ivtmp.139 ] [183])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg:SI 4 r4 [orig:182 i ] [182])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 14 lr [orig:183 ivtmp.139 ] [183])
(expr_list:REG_DEAD (reg/v:SI 12 ip [orig:182 i ] [182])
(nil))))
(insn 226 225 228 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 228 226 227 3 (set (reg:SI 12 ip [orig:187 ivtmp.139 ] [187])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 12 [0xc]))) 4 {*arm_addsi3}
(nil))
(insn 227 228 237 3 (set (reg/v:SI 14 lr [orig:186 i ] [186])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 3 [0x3]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 12 ip [orig:187 ivtmp.139 ] [187])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 237 227 239 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:187 ivtmp.139 ] [187])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:186 i ] [186])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 239 237 240 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:187 ivtmp.139 ] [187])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:186 i ] [186])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 14 lr [orig:186 i ] [186])
(expr_list:REG_DEAD (reg:SI 12 ip [orig:187 ivtmp.139 ] [187])
(nil))))
(insn 240 239 242 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 242 240 241 3 (set (reg:SI 4 r4 [orig:191 ivtmp.139 ] [191])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 16 [0x10]))) 4 {*arm_addsi3}
(nil))
(insn 241 242 251 3 (set (reg:SI 5 r5 [orig:190 i ] [190])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 4 [0x4]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 12 ip [orig:191 ivtmp.139 ] [191])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 251 241 253 3 (set (mem:SI (plus:SI (reg:SI 4 r4 [orig:191 ivtmp.139 ] [191])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg:SI 5 r5 [orig:190 i ] [190])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 253 251 254 3 (set (mem:SI (plus:SI (reg:SI 4 r4 [orig:191 ivtmp.139 ] [191])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg:SI 5 r5 [orig:190 i ] [190])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 14 lr [orig:190 i ] [190])
(expr_list:REG_DEAD (reg:SI 12 ip [orig:191 ivtmp.139 ] [191])
(nil))))
(insn 254 253 256 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 256 254 255 3 (set (reg:SI 12 ip [orig:195 ivtmp.139 ] [195])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 20 [0x14]))) 4 {*arm_addsi3}
(nil))
(insn 255 256 265 3 (set (reg/v:SI 14 lr [orig:194 i ] [194])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 5 [0x5]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 12 ip [orig:195 ivtmp.139 ] [195])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 265 255 267 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:195 ivtmp.139 ] [195])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:194 i ] [194])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 267 265 268 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:195 ivtmp.139 ] [195])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:194 i ] [194])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 14 lr [orig:194 i ] [194])
(expr_list:REG_DEAD (reg:SI 12 ip [orig:195 ivtmp.139 ] [195])
(nil))))
(insn 268 267 270 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 270 268 269 3 (set (reg:SI 4 r4 [orig:199 ivtmp.139 ] [199])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 24 [0x18]))) 4 {*arm_addsi3}
(nil))
(insn 269 270 279 3 (set (reg:SI 5 r5 [orig:198 i ] [198])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 6 [0x6]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 12 ip [orig:199 ivtmp.139 ] [199])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 279 269 281 3 (set (mem:SI (plus:SI (reg:SI 4 r4 [orig:199 ivtmp.139 ] [199])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg:SI 5 r5 [orig:198 i ] [198])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 281 279 282 3 (set (mem:SI (plus:SI (reg:SI 4 r4 [orig:199 ivtmp.139 ] [199])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg:SI 5 r5 [orig:198 i ] [198])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 14 lr [orig:198 i ] [198])
(expr_list:REG_DEAD (reg:SI 12 ip [orig:199 ivtmp.139 ] [199])
(nil))))
(insn 282 281 284 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 284 282 283 3 (set (reg:SI 12 ip [orig:203 ivtmp.139 ] [203])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 28 [0x1c]))) 4 {*arm_addsi3}
(nil))
(insn 283 284 293 3 (set (reg/v:SI 14 lr [orig:202 i ] [202])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 7 [0x7]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 12 ip [orig:203 ivtmp.139 ] [203])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 293 283 295 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:203 ivtmp.139 ] [203])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:202 i ] [202])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 295 293 296 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:203 ivtmp.139 ] [203])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:202 i ] [202])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 14 lr [orig:202 i ] [202])
(expr_list:REG_DEAD (reg:SI 12 ip [orig:203 ivtmp.139 ] [203])
(nil))))
(insn 296 295 297 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 297 296 298 3 (set (reg/v:SI 3 r3 [orig:137 i ] [137])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 8 [0x8]))) /tmp/x.c:29 4 {*arm_addsi3}
(nil))
(insn 298 297 299 3 (set (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 32 [0x20]))) 4 {*arm_addsi3}
(nil))
(insn 299 298 300 3 (set (reg:CC 24 cc)
(compare:CC (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 96 [0x60]))) /tmp/x.c:29 206 {*arm_cmpsi_insn}
(nil))
(jump_insn 300 299 206 3 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 29)
(pc))) /tmp/x.c:29 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 9896 [0x26a8])
(nil)))
-> 29)
(note 206 300 39 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 39 206 40 4 (set (reg:SI 0 r0)
(symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)) /tmp/x.c:35 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)
(nil)))
(insn 40 39 41 4 (set (reg:SI 1 r1)
(symbol_ref:SI ("arg1") [flags 0x80] <var_decl 0xb7224f60 arg1>)) /tmp/x.c:35 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (symbol_ref:SI ("arg1") [flags 0x80] <var_decl 0xb7224f60 arg1>)
(nil)))
(insn 41 40 42 4 (set (reg:SI 2 r2)
(symbol_ref:SI ("arg2") [flags 0x80] <var_decl 0xb723d120 arg2>)) /tmp/x.c:35 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (symbol_ref:SI ("arg2") [flags 0x80] <var_decl 0xb723d120 arg2>)
(nil)))
(call_insn 42 41 43 4 (parallel [
(call (mem:SI (symbol_ref:SI ("f883b") [flags 0x3] <function_decl 0xb7223e80 f883b>) [0 f883b S4 A32])
(const_int 0 [0]))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
]) /tmp/x.c:35 242 {*call_symbol}
(expr_list:REG_DEAD (reg:SI 2 r2)
(expr_list:REG_DEAD (reg:SI 1 r1)
(expr_list:REG_DEAD (reg:SI 0 r0)
(expr_list:REG_EH_REGION (const_int 0 [0])
(nil)))))
(expr_list:REG_DEP_TRUE (use (reg:SI 2 r2))
(expr_list:REG_DEP_TRUE (use (reg:SI 1 r1))
(expr_list:REG_DEP_TRUE (use (reg:SI 0 r0))
(nil)))))
(insn 43 42 45 4 (set (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const:SI (plus:SI (symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)
(const_int 47 [0x2f])))) 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const:SI (plus:SI (symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)
(const_int 47 [0x2f])))
(nil)))
(insn 45 43 48 4 (set (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(plus:SI (reg/f:SI 13 sp)
(const_int -4 [0xfffffffffffffffc]))) 4 {*arm_addsi3}
(expr_list:REG_EQUAL (plus:SI (reg/f:SI 13 sp)
(const_int -4 [0xfffffffffffffffc]))
(nil)))
(insn 48 45 61 4 (set (reg/f:SI 12 ip [orig:151 D.6566 ] [151])
(plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 32 [0x20]))) /tmp/x.c:24 4 {*arm_addsi3}
(expr_list:REG_EQUIV (const:SI (plus:SI (symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)
(const_int 79 [0x4f])))
(nil)))
(code_label 61 48 49 5 17 "" [1 uses])
(note 49 61 52 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 52 49 197 5 (set (reg:SI 5 r5 [orig:167 MEM[base: D.6563_36, offset: 0B] ] [167])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 1 [0x1])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 197 52 53 5 (set (reg:SI 0 r0 [172])
(plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 1 [0x1]))) 4 {*arm_addsi3}
(nil))
(insn 53 197 198 5 (set (reg:SI 4 r4 [orig:168 MEM[base: D.6564_37, offset: 0B] ] [168])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 4 [0x4])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 4 [0x4])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 198 53 54 5 (set (reg:SI 1 r1 [173])
(plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 4 [0x4]))) 4 {*arm_addsi3}
(nil))
(insn 54 198 55 5 (set (reg:CC 24 cc)
(compare:CC (reg:SI 5 r5 [orig:167 MEM[base: D.6563_36, offset: 0B] ] [167])
(reg:SI 4 r4 [orig:168 MEM[base: D.6564_37, offset: 0B] ] [168]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(nil))
(jump_insn 55 54 315 5 (set (pc)
(if_then_else (eq (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref 59)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 9996 [0x270c])
(nil)))
-> 59)
(code_label 315 55 56 6 41 "" [7 uses])
(note 56 315 57 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(call_insn 57 56 58 6 (parallel [
(call (mem:SI (symbol_ref:SI ("abort") [flags 0x41] <function_decl 0xb72bb400 abort>) [0 __builtin_abort S4 A32])
(const_int 0 [0]))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
]) /tmp/x.c:41 242 {*call_symbol}
(expr_list:REG_NORETURN (const_int 0 [0])
(expr_list:REG_EH_REGION (const_int 0 [0])
(nil)))
(nil))
(barrier 58 57 59)
(code_label 59 58 60 7 16 "" [1 uses])
(note 60 59 88 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(insn 88 60 89 7 (set (reg:SI 0 r0 [orig:210 MEM[base: D.6563_36, offset: 0B] ] [210])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 0 r0 [172])
(const_int 1 [0x1])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 89 88 90 7 (set (reg:SI 1 r1 [orig:211 MEM[base: D.6564_37, offset: 0B] ] [211])
(mem:SI (plus:SI (reg:SI 1 r1 [173])
(const_int 4 [0x4])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(nil))
(insn 90 89 91 7 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:210 MEM[base: D.6563_36, offset: 0B] ] [210])
(reg:SI 1 r1 [orig:211 MEM[base: D.6564_37, offset: 0B] ] [211]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:211 MEM[base: D.6564_37, offset: 0B] ] [211])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:210 MEM[base: D.6563_36, offset: 0B] ] [210])
(nil))))
(jump_insn 91 90 314 7 (set (pc)
(if_then_else (eq (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 99)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 9996 [0x270c])
(nil)))
-> 99)
(note 314 91 316 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(jump_insn 316 314 317 8 (set (pc)
(label_ref 315)) 230 {*arm_jump}
(nil)
-> 315)
(barrier 317 316 319)
(code_label 319 317 64 9 42 "" [1 uses])
(note 64 319 69 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(insn 69 64 72 9 (set (reg/i:SI 0 r0)
(const_int 0 [0])) /tmp/x.c:45 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const_int 0 [0])
(nil)))
(insn 72 69 327 9 (use (reg/i:SI 0 r0)) /tmp/x.c:45 -1
(nil))
(note 327 72 328 9 NOTE_INSN_EPILOGUE_BEG)
(jump_insn 328 327 329 9 (unspec_volatile [
(return)
] VUNSPEC_EPILOGUE) /tmp/x.c:45 313 {*epilogue_insns}
(nil)
-> return)
(barrier 329 328 99)
(code_label 99 329 96 10 20 "" [1 uses])
(note 96 99 104 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(insn 104 96 105 10 (set (reg:SI 14 lr [orig:214 MEM[base: D.6563_36, offset: 0B] ] [214])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 3 [0x3])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 105 104 106 10 (set (reg:SI 0 r0 [orig:215 MEM[base: D.6564_37, offset: 0B] ] [215])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 12 [0xc])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 12 [0xc])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 106 105 107 10 (set (reg:CC 24 cc)
(compare:CC (reg:SI 14 lr [orig:214 MEM[base: D.6563_36, offset: 0B] ] [214])
(reg:SI 0 r0 [orig:215 MEM[base: D.6564_37, offset: 0B] ] [215]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:215 MEM[base: D.6564_37, offset: 0B] ] [215])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:214 MEM[base: D.6563_36, offset: 0B] ] [214])
(nil))))
(jump_insn 107 106 112 10 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 112 107 120 11 [bb 11] NOTE_INSN_BASIC_BLOCK)
(insn 120 112 121 11 (set (reg:SI 14 lr [orig:218 MEM[base: D.6563_36, offset: 0B] ] [218])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 4 [0x4])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 121 120 122 11 (set (reg:SI 1 r1 [orig:219 MEM[base: D.6564_37, offset: 0B] ] [219])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 16 [0x10])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 16 [0x10])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 122 121 123 11 (set (reg:CC 24 cc)
(compare:CC (reg:SI 14 lr [orig:218 MEM[base: D.6563_36, offset: 0B] ] [218])
(reg:SI 1 r1 [orig:219 MEM[base: D.6564_37, offset: 0B] ] [219]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:219 MEM[base: D.6564_37, offset: 0B] ] [219])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:218 MEM[base: D.6563_36, offset: 0B] ] [218])
(nil))))
(jump_insn 123 122 128 11 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 128 123 136 12 [bb 12] NOTE_INSN_BASIC_BLOCK)
(insn 136 128 137 12 (set (reg:SI 0 r0 [orig:222 MEM[base: D.6563_36, offset: 0B] ] [222])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 5 [0x5])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 137 136 138 12 (set (reg:SI 14 lr [orig:223 MEM[base: D.6564_37, offset: 0B] ] [223])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 20 [0x14])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 20 [0x14])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 138 137 139 12 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:222 MEM[base: D.6563_36, offset: 0B] ] [222])
(reg:SI 14 lr [orig:223 MEM[base: D.6564_37, offset: 0B] ] [223]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:223 MEM[base: D.6564_37, offset: 0B] ] [223])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:222 MEM[base: D.6563_36, offset: 0B] ] [222])
(nil))))
(jump_insn 139 138 144 12 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 144 139 152 13 [bb 13] NOTE_INSN_BASIC_BLOCK)
(insn 152 144 153 13 (set (reg:SI 0 r0 [orig:226 MEM[base: D.6563_36, offset: 0B] ] [226])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 6 [0x6])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 153 152 154 13 (set (reg:SI 1 r1 [orig:227 MEM[base: D.6564_37, offset: 0B] ] [227])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 24 [0x18])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 24 [0x18])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 154 153 155 13 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:226 MEM[base: D.6563_36, offset: 0B] ] [226])
(reg:SI 1 r1 [orig:227 MEM[base: D.6564_37, offset: 0B] ] [227]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:227 MEM[base: D.6564_37, offset: 0B] ] [227])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:226 MEM[base: D.6563_36, offset: 0B] ] [226])
(nil))))
(jump_insn 155 154 160 13 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 160 155 168 14 [bb 14] NOTE_INSN_BASIC_BLOCK)
(insn 168 160 169 14 (set (reg:SI 14 lr [orig:230 MEM[base: D.6563_36, offset: 0B] ] [230])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 7 [0x7])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 169 168 170 14 (set (reg:SI 0 r0 [orig:231 MEM[base: D.6564_37, offset: 0B] ] [231])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 28 [0x1c])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 28 [0x1c])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 170 169 171 14 (set (reg:CC 24 cc)
(compare:CC (reg:SI 14 lr [orig:230 MEM[base: D.6563_36, offset: 0B] ] [230])
(reg:SI 0 r0 [orig:231 MEM[base: D.6564_37, offset: 0B] ] [231]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:231 MEM[base: D.6564_37, offset: 0B] ] [231])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:230 MEM[base: D.6563_36, offset: 0B] ] [230])
(nil))))
(jump_insn 171 170 176 14 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 176 171 184 15 [bb 15] NOTE_INSN_BASIC_BLOCK)
(insn 184 176 185 15 (set (reg:SI 14 lr [orig:232 MEM[base: D.6563_36, offset: 0B] ] [232])
(sign_extend:SI (mem:QI (pre_modify:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 8 [0x8]))) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(expr_list:REG_INC (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(nil)))
(insn 185 184 186 15 (set (reg:SI 1 r1 [orig:233 MEM[base: D.6564_37, offset: 0B] ] [233])
(mem:SI (pre_modify:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 32 [0x20]))) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_INC (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(nil)))
(insn 186 185 187 15 (set (reg:CC 24 cc)
(compare:CC (reg:SI 14 lr [orig:232 MEM[base: D.6563_36, offset: 0B] ] [232])
(reg:SI 1 r1 [orig:233 MEM[base: D.6564_37, offset: 0B] ] [233]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:233 MEM[base: D.6564_37, offset: 0B] ] [233])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:232 MEM[base: D.6563_36, offset: 0B] ] [232])
(nil))))
(jump_insn 187 186 192 15 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 192 187 190 16 [bb 16] NOTE_INSN_BASIC_BLOCK)
(insn 190 192 191 16 (set (reg:CC 24 cc)
(compare:CC (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(reg/f:SI 12 ip [orig:151 D.6566 ] [151]))) /tmp/x.c:37 206 {*arm_cmpsi_insn}
(expr_list:REG_EQUAL (compare:CC (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const:SI (plus:SI (symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)
(const_int 79 [0x4f]))))
(nil)))
(jump_insn 191 190 318 16 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 61)
(pc))) /tmp/x.c:37 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 9687 [0x25d7])
(nil)))
-> 61)
(note 318 191 320 17 [bb 17] NOTE_INSN_BASIC_BLOCK)
(jump_insn 320 318 321 17 (set (pc)
(label_ref 319)) 230 {*arm_jump}
(nil)
-> 319)
(barrier 321 320 322)
(note 322 321 0 NOTE_INSN_DELETED)
[-- Attachment #4: x.c.202r.ce3 --]
[-- Type: application/octet-stream, Size: 76090 bytes --]
;; Function f883b (f883b, funcdef_no=0, decl_uid=4784, cgraph_uid=0)
;; 2 loops found
;;
;; Loop 0
;; header 0, latch 1
;; depth 0, outer -1
;; nodes: 0 1 2 3 4 5 6
;;
;; Loop 1
;; header 5, latch 5
;; depth 1, outer 0
;; nodes: 5
;; 2 succs { 4 3 }
;; 3 succs { 6 }
;; 4 succs { 5 }
;; 5 succs { 5 6 }
;; 6 succs { 1 }
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
IF-CASE-1 found, start 2, then 3
========== no more changes
1 possible IF blocks searched.
0 IF blocks converted.
0 true changes made.
starting the processing of deferred insns
ending the processing of deferred insns
(note 71 0 77 NOTE_INSN_DELETED)
(note 77 71 357 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 357 77 358 2 (parallel [
(set (mem/c:BLK (pre_modify:SI (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -32 [0xffffffffffffffe0]))) [3 A8])
(unspec:BLK [
(reg:SI 4 r4)
] UNSPEC_PUSH_MULT))
(use (reg:SI 5 r5))
(use (reg:SI 6 r6))
(use (reg:SI 7 r7))
(use (reg:SI 8 r8))
(use (reg:SI 9 r9))
(use (reg:SI 10 sl))
(use (reg:SI 11 fp))
]) /tmp/x.c:13 -1
(expr_list:REG_DEAD (reg:SI 10 sl)
(expr_list:REG_DEAD (reg:SI 9 r9)
(expr_list:REG_DEAD (reg:SI 8 r8)
(expr_list:REG_DEAD (reg:SI 7 r7)
(expr_list:REG_DEAD (reg:SI 5 r5)
(expr_list:REG_DEAD (reg:SI 4 r4)
(expr_list:REG_FRAME_RELATED_EXPR (sequence [
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -32 [0xffffffffffffffe0])))
(set/f (mem/c:SI (reg/f:SI 13 sp) [3 S4 A32])
(reg:SI 4 r4))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [3 S4 A32])
(reg:SI 5 r5))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [3 S4 A32])
(reg:SI 6 r6))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 12 [0xc])) [3 S4 A32])
(reg:SI 7 r7))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 16 [0x10])) [3 S4 A32])
(reg:SI 8 r8))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 20 [0x14])) [3 S4 A32])
(reg:SI 9 r9))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 24 [0x18])) [3 S4 A32])
(reg:SI 10 sl))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 28 [0x1c])) [3 S4 A32])
(reg:SI 11 fp))
])
(nil)))))))))
(note 358 357 75 2 NOTE_INSN_PROLOGUE_END)
(note 75 358 82 2 NOTE_INSN_FUNCTION_BEG)
(note 82 75 83 2 NOTE_INSN_DELETED)
(note 83 82 86 2 NOTE_INSN_DELETED)
(note 86 83 91 2 NOTE_INSN_DELETED)
(note 91 86 92 2 NOTE_INSN_DELETED)
(note 92 91 95 2 NOTE_INSN_DELETED)
(note 95 92 101 2 NOTE_INSN_DELETED)
(note 101 95 102 2 NOTE_INSN_DELETED)
(note 102 101 103 2 NOTE_INSN_DELETED)
(note 103 102 80 2 NOTE_INSN_DELETED)
(insn 80 103 85 2 (set (reg/f:SI 12 ip [orig:227 D.6457 ] [227])
(plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(const_int 80 [0x50]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 85 80 94 2 (set (reg/f:SI 5 r5 [292])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 192 [0xc0]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 94 85 79 2 (set (reg/f:SI 4 r4 [299])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 192 [0xc0]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 79 94 351 2 (set (reg/f:SI 3 r3 [orig:223 vect_p.31 ] [223])
(plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(const_int 48 [0x30]))) 4 {*arm_addsi3}
(nil))
(insn 351 79 352 2 (set (reg:CC 24 cc)
(compare:CC (reg/f:SI 12 ip [orig:227 D.6457 ] [227])
(reg/f:SI 5 r5 [292]))) /tmp/x.c:10 206 {*arm_cmpsi_insn}
(nil))
(insn 352 351 353 2 (cond_exec (gtu (reg:CC 24 cc)
(const_int 0 [0]))
(set (reg:SI 6 r6 [294])
(const_int 0 [0]))) /tmp/x.c:10 3177 {*p *arm_movsi_vfp}
(nil))
(insn 353 352 354 2 (cond_exec (leu (reg:CC 24 cc)
(const_int 0 [0]))
(set (reg:SI 6 r6 [294])
(const_int 1 [0x1]))) /tmp/x.c:10 3177 {*p *arm_movsi_vfp}
(expr_list:REG_DEAD (reg:CC 24 cc)
(nil)))
(insn 354 353 355 2 (set (reg:CC 24 cc)
(compare:CC (reg/f:SI 12 ip [orig:227 D.6457 ] [227])
(reg/f:SI 4 r4 [299]))) /tmp/x.c:10 206 {*arm_cmpsi_insn}
(nil))
(insn 355 354 356 2 (cond_exec (gtu (reg:CC 24 cc)
(const_int 0 [0]))
(set (reg:SI 12 ip [301])
(const_int 0 [0]))) /tmp/x.c:10 3177 {*p *arm_movsi_vfp}
(nil))
(insn 356 355 81 2 (cond_exec (leu (reg:CC 24 cc)
(const_int 0 [0]))
(set (reg:SI 12 ip [301])
(const_int 1 [0x1]))) /tmp/x.c:10 3177 {*p *arm_movsi_vfp}
(expr_list:REG_DEAD (reg:CC 24 cc)
(nil)))
(insn 81 356 90 2 (set (reg/f:SI 8 r8 [289])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 320 [0x140]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 90 81 89 2 (set (reg/f:SI 7 r7 [296])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 320 [0x140]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 89 90 98 2 (parallel [
(set (reg:SI 6 r6 [295])
(ior:SI (geu:SI (reg/f:SI 3 r3 [orig:223 vect_p.31 ] [223])
(reg/f:SI 8 r8 [289]))
(reg:SI 6 r6 [294])))
(clobber (reg:CC 24 cc))
]) /tmp/x.c:10 269 {*cond_arith}
(expr_list:REG_DEAD (reg/f:SI 8 r8 [289])
(expr_list:REG_UNUSED (reg:CC 24 cc)
(nil))))
(insn 98 89 104 2 (parallel [
(set (reg:SI 12 ip [302])
(ior:SI (geu:SI (reg/f:SI 3 r3 [orig:223 vect_p.31 ] [223])
(reg/f:SI 7 r7 [296]))
(reg:SI 12 ip [301])))
(clobber (reg:CC 24 cc))
]) /tmp/x.c:10 269 {*cond_arith}
(expr_list:REG_DEAD (reg/f:SI 7 r7 [296])
(expr_list:REG_UNUSED (reg:CC 24 cc)
(nil))))
(insn 104 98 105 2 (parallel [
(set (reg:CC_NOOV 24 cc)
(compare:CC_NOOV (and:SI (reg:SI 6 r6 [295])
(reg:SI 12 ip [302]))
(const_int 0 [0])))
(clobber (scratch:SI))
]) 78 {*andsi3_compare0_scratch}
(expr_list:REG_DEAD (reg:SI 12 ip [302])
(expr_list:REG_DEAD (reg:SI 6 r6 [295])
(nil))))
(jump_insn 105 104 106 2 (set (pc)
(if_then_else (eq (reg:CC_NOOV 24 cc)
(const_int 0 [0]))
(label_ref 183)
(pc))) 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC_NOOV 24 cc)
(expr_list:REG_BR_PROB (const_int 2000 [0x7d0])
(nil)))
-> 183)
(note 106 105 117 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 117 106 126 3 (set (reg/f:SI 8 r8 [319])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 208 [0xd0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 126 117 134 3 (set (reg/f:SI 7 r7 [328])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 224 [0xe0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 134 126 111 3 (set (reg/f:SI 6 r6 [336])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 240 [0xf0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 111 134 110 3 (set (reg:V4SI 95 d16 [313])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
])) /tmp/x.c:16 754 {*neon_movv4si}
(expr_list:REG_EQUIV (const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
])
(nil)))
(insn 110 111 115 3 (set (reg:V4SI 115 d26 [310])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 5 r5 [292]) [2 MEM[(uint32_t *)arg2_13(D) + 192B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 5 r5 [292])
(nil)))
(insn 115 110 112 3 (set (reg/f:SI 9 r9 [317])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 208 [0xd0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 112 115 124 3 (set (reg:V4SI 115 d26 [312])
(and:V4SI (reg:V4SI 115 d26 [310])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 115 d26 [310])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 124 112 118 3 (set (reg/f:SI 12 ip [326])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 224 [0xe0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 118 124 132 3 (set (reg:V4SI 103 d20 [318])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 8 r8 [319]) [2 MEM[(uint32_t *)arg2_13(D) + 208B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 8 r8 [319])
(nil)))
(insn 132 118 120 3 (set (reg/f:SI 10 sl [334])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 240 [0xf0]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 120 132 146 3 (set (reg:V4SI 103 d20 [320])
(and:V4SI (reg:V4SI 103 d20 [318])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 103 d20 [318])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 146 120 127 3 (set (reg/f:SI 8 r8 [347])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 256 [0x100]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 127 146 113 3 (set (reg:V4SI 119 d28 [327])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 7 r7 [328]) [2 MEM[(uint32_t *)arg2_13(D) + 224B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 7 r7 [328])
(nil)))
(insn 113 127 129 3 (set (reg:V4SI 115 d26 [315])
(neg:V4SI (reg:V4SI 115 d26 [312]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 129 113 154 3 (set (reg:V4SI 119 d28 [329])
(and:V4SI (reg:V4SI 119 d28 [327])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 119 d28 [327])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 154 129 135 3 (set (reg/f:SI 7 r7 [355])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 272 [0x110]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 135 154 121 3 (set (reg:V4SI 107 d22 [335])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 6 r6 [336]) [2 MEM[(uint32_t *)arg2_13(D) + 240B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 6 r6 [336])
(nil)))
(insn 121 135 137 3 (set (reg:V4SI 103 d20 [323])
(neg:V4SI (reg:V4SI 103 d20 [320]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 137 121 163 3 (set (reg:V4SI 107 d22 [337])
(and:V4SI (reg:V4SI 107 d22 [335])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 107 d22 [335])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 163 137 130 3 (set (reg/f:SI 6 r6 [364])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 288 [0x120]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 130 163 108 3 (set (reg:V4SI 119 d28 [332])
(neg:V4SI (reg:V4SI 119 d28 [329]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 108 130 171 3 (set (reg:V4SI 111 d24 [308])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 4 r4 [299]) [2 MEM[(int32_t *)arg1_8(D) + 192B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 4 r4 [299])
(nil)))
(insn 171 108 144 3 (set (reg/f:SI 2 r2 [372])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 304 [0x130]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 144 171 138 3 (set (reg/f:SI 5 r5 [345])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 256 [0x100]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 138 144 116 3 (set (reg:V4SI 107 d22 [340])
(neg:V4SI (reg:V4SI 107 d22 [337]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 116 138 114 3 (set (reg:V4SI 99 d18 [316])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 9 r9 [317]) [2 MEM[(int32_t *)arg1_8(D) + 208B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 114 116 152 3 (set (reg:V4SI 115 d26 [314])
(unspec:V4SI [
(reg:V4SI 111 d24 [308])
(reg:V4SI 115 d26 [315])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 111 d24 [308])
(reg:V4SI 115 d26 [312]))
(nil)))
(insn 152 114 125 3 (set (reg/f:SI 4 r4 [353])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 272 [0x110]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 125 152 161 3 (set (reg:V4SI 111 d24 [325])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 12 ip [326]) [2 MEM[(int32_t *)arg1_8(D) + 224B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 12 ip [326])
(nil)))
(insn 161 125 122 3 (set (reg/f:SI 12 ip [362])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 288 [0x120]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 122 161 169 3 (set (reg:V4SI 103 d20 [322])
(unspec:V4SI [
(reg:V4SI 99 d18 [316])
(reg:V4SI 103 d20 [323])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 99 d18 [316])
(reg:V4SI 103 d20 [320]))
(nil)))
(insn 169 122 133 3 (set (reg/f:SI 1 r1 [370])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 304 [0x130]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 133 169 179 3 (set (reg:V4SI 99 d18 [333])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 10 sl [334]) [2 MEM[(int32_t *)arg1_8(D) + 240B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 179 133 131 3 (set (reg/f:SI 0 r0 [379])
(plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(const_int 64 [0x40]))) /tmp/x.c:16 4 {*arm_addsi3}
(nil))
(insn 131 179 139 3 (set (reg:V4SI 111 d24 [331])
(unspec:V4SI [
(reg:V4SI 111 d24 [325])
(reg:V4SI 119 d28 [332])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 111 d24 [325])
(reg:V4SI 119 d28 [329]))
(nil)))
(insn 139 131 123 3 (set (reg:V4SI 99 d18 [339])
(unspec:V4SI [
(reg:V4SI 99 d18 [333])
(reg:V4SI 107 d22 [340])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 99 d18 [333])
(reg:V4SI 107 d22 [337]))
(nil)))
(insn 123 139 140 3 (set (reg:V8HI 107 d22 [324])
(vec_concat:V8HI (truncate:V4HI (reg:V4SI 115 d26 [314]))
(truncate:V4HI (reg:V4SI 103 d20 [322])))) /tmp/x.c:16 1775 {vec_pack_trunc_v4si}
(nil))
(insn 140 123 141 3 (set (reg:V8HI 103 d20 [341])
(vec_concat:V8HI (truncate:V4HI (reg:V4SI 111 d24 [331]))
(truncate:V4HI (reg:V4SI 99 d18 [339])))) /tmp/x.c:16 1775 {vec_pack_trunc_v4si}
(nil))
(insn 141 140 143 3 (set (reg:V16QI 99 d18 [342])
(vec_concat:V16QI (truncate:V8QI (reg:V8HI 107 d22 [324]))
(truncate:V8QI (reg:V8HI 103 d20 [341])))) /tmp/x.c:16 1774 {vec_pack_trunc_v8hi}
(nil))
(insn 143 141 147 3 (set (mem:V16QI (reg/f:SI 3 r3 [orig:223 vect_p.31 ] [223]) [0 MEM[(int8_t *)result_4(D) + 48B]+0 S16 A8])
(unspec:V16QI [
(reg:V16QI 99 d18 [342])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 772 {*movmisalignv16qi_neon_store}
(expr_list:REG_DEAD (reg/f:SI 3 r3 [orig:223 vect_p.31 ] [223])
(nil)))
(insn 147 143 149 3 (set (reg:V4SI 111 d24 [346])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 8 r8 [347]) [2 MEM[(uint32_t *)arg2_13(D) + 256B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 149 147 155 3 (set (reg:V4SI 111 d24 [348])
(and:V4SI (reg:V4SI 111 d24 [346])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 111 d24 [346])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 155 149 157 3 (set (reg:V4SI 103 d20 [354])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 7 r7 [355]) [2 MEM[(uint32_t *)arg2_13(D) + 272B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 157 155 164 3 (set (reg:V4SI 103 d20 [356])
(and:V4SI (reg:V4SI 103 d20 [354])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 103 d20 [354])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 164 157 150 3 (set (reg:V4SI 115 d26 [363])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 6 r6 [364]) [2 MEM[(uint32_t *)arg2_13(D) + 288B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 150 164 166 3 (set (reg:V4SI 111 d24 [351])
(neg:V4SI (reg:V4SI 111 d24 [348]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 166 150 172 3 (set (reg:V4SI 115 d26 [365])
(and:V4SI (reg:V4SI 115 d26 [363])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 115 d26 [363])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 172 166 158 3 (set (reg:V4SI 107 d22 [371])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 2 r2 [372]) [2 MEM[(uint32_t *)arg2_13(D) + 304B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 2 r2 [372])
(nil)))
(insn 158 172 174 3 (set (reg:V4SI 103 d20 [359])
(neg:V4SI (reg:V4SI 103 d20 [356]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 174 158 167 3 (set (reg:V4SI 95 d16 [373])
(and:V4SI (reg:V4SI 107 d22 [371])
(reg:V4SI 95 d16 [313]))) /tmp/x.c:16 862 {andv4si3}
(expr_list:REG_EQUAL (and:V4SI (reg:V4SI 107 d22 [371])
(const_vector:V4SI [
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
(const_int 7 [0x7])
]))
(nil)))
(insn 167 174 145 3 (set (reg:V4SI 115 d26 [368])
(neg:V4SI (reg:V4SI 115 d26 [365]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 145 167 175 3 (set (reg:V4SI 107 d22 [344])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 5 r5 [345]) [2 MEM[(int32_t *)arg1_8(D) + 256B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 175 145 153 3 (set (reg:V4SI 95 d16 [376])
(neg:V4SI (reg:V4SI 95 d16 [373]))) /tmp/x.c:16 919 {negv4si2}
(nil))
(insn 153 175 151 3 (set (reg:V4SI 99 d18 [352])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 4 r4 [353]) [2 MEM[(int32_t *)arg1_8(D) + 272B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(nil))
(insn 151 153 162 3 (set (reg:V4SI 111 d24 [350])
(unspec:V4SI [
(reg:V4SI 107 d22 [344])
(reg:V4SI 111 d24 [351])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 107 d22 [344])
(reg:V4SI 111 d24 [348]))
(nil)))
(insn 162 151 159 3 (set (reg:V4SI 107 d22 [361])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 12 ip [362]) [2 MEM[(int32_t *)arg1_8(D) + 288B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 12 ip [362])
(nil)))
(insn 159 162 170 3 (set (reg:V4SI 99 d18 [358])
(unspec:V4SI [
(reg:V4SI 99 d18 [352])
(reg:V4SI 103 d20 [359])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 99 d18 [352])
(reg:V4SI 103 d20 [356]))
(nil)))
(insn 170 159 168 3 (set (reg:V4SI 103 d20 [369])
(unspec:V4SI [
(mem:V4SI (reg/f:SI 1 r1 [370]) [2 MEM[(int32_t *)arg1_8(D) + 304B]+0 S16 A32])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 779 {*movmisalignv4si_neon_load}
(expr_list:REG_DEAD (reg/f:SI 1 r1 [370])
(nil)))
(insn 168 170 176 3 (set (reg:V4SI 107 d22 [367])
(unspec:V4SI [
(reg:V4SI 107 d22 [361])
(reg:V4SI 115 d26 [368])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 107 d22 [361])
(reg:V4SI 115 d26 [365]))
(nil)))
(insn 176 168 160 3 (set (reg:V4SI 95 d16 [375])
(unspec:V4SI [
(reg:V4SI 103 d20 [369])
(reg:V4SI 95 d16 [376])
] UNSPEC_ASHIFT_SIGNED)) /tmp/x.c:16 973 {ashlv4si3_signed}
(expr_list:REG_EQUAL (ashiftrt:V4SI (reg:V4SI 103 d20 [369])
(reg:V4SI 95 d16 [373]))
(nil)))
(insn 160 176 177 3 (set (reg:V8HI 103 d20 [360])
(vec_concat:V8HI (truncate:V4HI (reg:V4SI 111 d24 [350]))
(truncate:V4HI (reg:V4SI 99 d18 [358])))) /tmp/x.c:16 1775 {vec_pack_trunc_v4si}
(nil))
(insn 177 160 178 3 (set (reg:V8HI 99 d18 [377])
(vec_concat:V8HI (truncate:V4HI (reg:V4SI 107 d22 [367]))
(truncate:V4HI (reg:V4SI 95 d16 [375])))) /tmp/x.c:16 1775 {vec_pack_trunc_v4si}
(nil))
(insn 178 177 180 3 (set (reg:V16QI 95 d16 [378])
(vec_concat:V16QI (truncate:V8QI (reg:V8HI 103 d20 [360]))
(truncate:V8QI (reg:V8HI 99 d18 [377])))) /tmp/x.c:16 1774 {vec_pack_trunc_v8hi}
(nil))
(insn 180 178 346 3 (set (mem:V16QI (reg/f:SI 0 r0 [379]) [0 MEM[(int8_t *)result_4(D) + 64B]+0 S16 A8])
(unspec:V16QI [
(reg:V16QI 95 d16 [378])
] UNSPEC_MISALIGNED_ACCESS)) /tmp/x.c:16 772 {*movmisalignv16qi_neon_store}
(expr_list:REG_DEAD (reg/f:SI 0 r0 [379])
(nil)))
(jump_insn 346 180 347 3 (set (pc)
(label_ref 202)) 230 {*arm_jump}
(nil)
-> 202)
(barrier 347 346 183)
(code_label 183 347 184 4 2 "" [1 uses])
(note 184 183 185 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 185 184 186 4 (set (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(plus:SI (reg/v/f:SI 1 r1 [orig:287 arg1 ] [287])
(const_int 188 [0xbc]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 186 185 76 4 (set (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(plus:SI (reg/v/f:SI 2 r2 [orig:288 arg2 ] [288])
(const_int 188 [0xbc]))) /tmp/x.c:10 4 {*arm_addsi3}
(nil))
(insn 76 186 197 4 (set (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 48 [0x30])) /tmp/x.c:15 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const_int 48 [0x30])
(nil)))
(code_label 197 76 187 5 4 "" [1 uses])
(note 187 197 335 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(note 335 187 336 5 NOTE_INSN_DELETED)
(note 336 335 190 5 NOTE_INSN_DELETED)
(insn 190 336 337 5 (set (reg:SI 4 r4 [orig:381 MEM[base: D.6528_147, offset: 0B] ] [381])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 4 [0x4])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 4 [0x4])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 337 190 192 5 (set (reg:SI 12 ip [387])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 1 [0x1]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 192 337 238 5 (set (reg:SI 5 r5 [orig:383 MEM[base: D.6527_146, offset: 0B] ] [383])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 4 [0x4])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 4 [0x4])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 238 192 191 5 (set (reg/v:SI 10 sl [orig:398 idx ] [398])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 2 [0x2]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 191 238 253 5 (set (reg:SI 4 r4 [380])
(and:SI (reg:SI 4 r4 [orig:381 MEM[base: D.6528_147, offset: 0B] ] [381])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 253 191 268 5 (set (reg/v:SI 8 r8 [orig:405 idx ] [405])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 3 [0x3]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 268 253 283 5 (set (reg/v:SI 7 r7 [orig:412 idx ] [412])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 4 [0x4]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 283 268 193 5 (set (reg/v:SI 6 r6 [orig:419 idx ] [419])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 5 [0x5]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 193 283 195 5 (set (reg:SI 4 r4 [382])
(ashiftrt:SI (reg:SI 5 r5 [orig:383 MEM[base: D.6527_146, offset: 0B] ] [383])
(reg:SI 4 r4 [380]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(expr_list:REG_DEAD (reg:SI 5 r5 [orig:383 MEM[base: D.6527_146, offset: 0B] ] [383])
(nil)))
(insn 195 193 233 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 3 r3 [orig:235 idx ] [235])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 4 r4 [382])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 4 r4 [382])
(nil)))
(insn 233 195 298 5 (set (reg:SI 9 r9 [orig:394 MEM[base: D.6528_147, offset: 0B] ] [394])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 8 [0x8])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 8 [0x8])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 298 233 235 5 (set (reg/v:SI 5 r5 [orig:426 idx ] [426])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 6 [0x6]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 235 298 313 5 (set (reg:SI 11 fp [orig:396 MEM[base: D.6527_146, offset: 0B] ] [396])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 8 [0x8])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 8 [0x8])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 313 235 234 5 (set (reg/v:SI 4 r4 [orig:433 idx ] [433])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 7 [0x7]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 234 313 328 5 (set (reg:SI 9 r9 [395])
(and:SI (reg:SI 9 r9 [orig:394 MEM[base: D.6528_147, offset: 0B] ] [394])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 328 234 329 5 (set (reg/v:SI 3 r3 [orig:235 idx ] [235])
(plus:SI (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 8 [0x8]))) /tmp/x.c:15 4 {*arm_addsi3}
(nil))
(insn 329 328 236 5 (set (reg:CC 24 cc)
(compare:CC (reg/v:SI 3 r3 [orig:235 idx ] [235])
(const_int 80 [0x50]))) /tmp/x.c:15 206 {*arm_cmpsi_insn}
(nil))
(insn 236 329 237 5 (set (reg:SI 9 r9 [397])
(ashiftrt:SI (reg:SI 11 fp [orig:396 MEM[base: D.6527_146, offset: 0B] ] [396])
(reg:SI 9 r9 [395]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 237 236 248 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg:SI 12 ip [387])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 9 r9 [397])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:SI 12 ip [387])
(expr_list:REG_DEAD (reg:QI 9 r9 [397])
(nil))))
(insn 248 237 250 5 (set (reg:SI 12 ip [orig:401 MEM[base: D.6528_147, offset: 0B] ] [401])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 12 [0xc])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 12 [0xc])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 250 248 249 5 (set (reg:SI 9 r9 [orig:403 MEM[base: D.6527_146, offset: 0B] ] [403])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 12 [0xc])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 12 [0xc])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 249 250 251 5 (set (reg:SI 12 ip [402])
(and:SI (reg:SI 12 ip [orig:401 MEM[base: D.6528_147, offset: 0B] ] [401])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 251 249 252 5 (set (reg:SI 12 ip [404])
(ashiftrt:SI (reg:SI 9 r9 [orig:403 MEM[base: D.6527_146, offset: 0B] ] [403])
(reg:SI 12 ip [402]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 252 251 263 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 10 sl [orig:398 idx ] [398])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [404])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [404])
(expr_list:REG_DEAD (reg/v:SI 10 sl [orig:398 idx ] [398])
(nil))))
(insn 263 252 265 5 (set (reg:SI 12 ip [orig:408 MEM[base: D.6528_147, offset: 0B] ] [408])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 16 [0x10])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 16 [0x10])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 265 263 264 5 (set (reg:SI 10 sl [orig:410 MEM[base: D.6527_146, offset: 0B] ] [410])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 16 [0x10])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 16 [0x10])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 264 265 266 5 (set (reg:SI 12 ip [409])
(and:SI (reg:SI 12 ip [orig:408 MEM[base: D.6528_147, offset: 0B] ] [408])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 266 264 267 5 (set (reg:SI 12 ip [411])
(ashiftrt:SI (reg:SI 10 sl [orig:410 MEM[base: D.6527_146, offset: 0B] ] [410])
(reg:SI 12 ip [409]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 267 266 278 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 8 r8 [orig:405 idx ] [405])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [411])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [411])
(expr_list:REG_DEAD (reg/v:SI 8 r8 [orig:405 idx ] [405])
(nil))))
(insn 278 267 280 5 (set (reg:SI 12 ip [orig:415 MEM[base: D.6528_147, offset: 0B] ] [415])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 20 [0x14])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 20 [0x14])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 280 278 279 5 (set (reg:SI 8 r8 [orig:417 MEM[base: D.6527_146, offset: 0B] ] [417])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 20 [0x14])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 20 [0x14])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 279 280 281 5 (set (reg:SI 12 ip [416])
(and:SI (reg:SI 12 ip [orig:415 MEM[base: D.6528_147, offset: 0B] ] [415])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 281 279 282 5 (set (reg:SI 12 ip [418])
(ashiftrt:SI (reg:SI 8 r8 [orig:417 MEM[base: D.6527_146, offset: 0B] ] [417])
(reg:SI 12 ip [416]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 282 281 293 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 7 r7 [orig:412 idx ] [412])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [418])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [418])
(expr_list:REG_DEAD (reg/v:SI 7 r7 [orig:412 idx ] [412])
(nil))))
(insn 293 282 295 5 (set (reg:SI 12 ip [orig:422 MEM[base: D.6528_147, offset: 0B] ] [422])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 24 [0x18])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 24 [0x18])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 295 293 294 5 (set (reg:SI 7 r7 [orig:424 MEM[base: D.6527_146, offset: 0B] ] [424])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 24 [0x18])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 24 [0x18])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 294 295 296 5 (set (reg:SI 12 ip [423])
(and:SI (reg:SI 12 ip [orig:422 MEM[base: D.6528_147, offset: 0B] ] [422])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 296 294 297 5 (set (reg:SI 12 ip [425])
(ashiftrt:SI (reg:SI 7 r7 [orig:424 MEM[base: D.6527_146, offset: 0B] ] [424])
(reg:SI 12 ip [423]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 297 296 308 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 6 r6 [orig:419 idx ] [419])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [425])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [425])
(expr_list:REG_DEAD (reg/v:SI 6 r6 [orig:419 idx ] [419])
(nil))))
(insn 308 297 310 5 (set (reg:SI 12 ip [orig:429 MEM[base: D.6528_147, offset: 0B] ] [429])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 28 [0x1c])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 28 [0x1c])) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])
(nil)))
(insn 310 308 309 5 (set (reg:SI 6 r6 [orig:431 MEM[base: D.6527_146, offset: 0B] ] [431])
(mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 28 [0x1c])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 28 [0x1c])) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])
(nil)))
(insn 309 310 311 5 (set (reg:SI 12 ip [430])
(and:SI (reg:SI 12 ip [orig:429 MEM[base: D.6528_147, offset: 0B] ] [429])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 311 309 312 5 (set (reg:SI 12 ip [432])
(ashiftrt:SI (reg:SI 6 r6 [orig:431 MEM[base: D.6527_146, offset: 0B] ] [431])
(reg:SI 12 ip [430]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 312 311 323 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 5 r5 [orig:426 idx ] [426])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [432])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [432])
(expr_list:REG_DEAD (reg/v:SI 5 r5 [orig:426 idx ] [426])
(nil))))
(insn 323 312 325 5 (set (reg:SI 12 ip [orig:434 MEM[base: D.6528_147, offset: 0B] ] [434])
(mem:SI (pre_modify:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(plus:SI (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(const_int 32 [0x20]))) [2 MEM[base: D.6528_147, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_INC (reg:SI 2 r2 [orig:206 ivtmp.81 ] [206])
(nil)))
(insn 325 323 324 5 (set (reg:SI 5 r5 [orig:436 MEM[base: D.6527_146, offset: 0B] ] [436])
(mem:SI (pre_modify:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(plus:SI (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(const_int 32 [0x20]))) [2 MEM[base: D.6527_146, offset: 0B]+0 S4 A32])) /tmp/x.c:16 634 {*arm_movsi_vfp}
(expr_list:REG_INC (reg:SI 1 r1 [orig:197 ivtmp.72 ] [197])
(nil)))
(insn 324 325 326 5 (set (reg:SI 12 ip [435])
(and:SI (reg:SI 12 ip [orig:434 MEM[base: D.6528_147, offset: 0B] ] [434])
(const_int 7 [0x7]))) /tmp/x.c:16 75 {*arm_andsi3_insn}
(nil))
(insn 326 324 327 5 (set (reg:SI 12 ip [437])
(ashiftrt:SI (reg:SI 5 r5 [orig:436 MEM[base: D.6527_146, offset: 0B] ] [436])
(reg:SI 12 ip [435]))) /tmp/x.c:16 125 {*arm_shiftsi3}
(nil))
(insn 327 326 330 5 (set (mem:QI (plus:SI (reg/v/f:SI 0 r0 [orig:286 result ] [286])
(reg/v:SI 4 r4 [orig:433 idx ] [433])) [0 MEM[base: result_4(D), index: D.6529_148, offset: 0B]+0 S1 A8])
(reg:QI 12 ip [437])) /tmp/x.c:16 187 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:QI 12 ip [437])
(nil)))
(jump_insn 330 327 202 5 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 197)
(pc))) /tmp/x.c:15 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 9688 [0x25d8])
(nil)))
-> 197)
(code_label 202 330 203 6 1 "" [1 uses])
(note 203 202 359 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(note 359 203 360 6 NOTE_INSN_EPILOGUE_BEG)
(jump_insn 360 359 361 6 (unspec_volatile [
(return)
] VUNSPEC_EPILOGUE) /tmp/x.c:18 -1
(nil)
-> return)
(barrier 361 360 348)
(note 348 361 349 NOTE_INSN_DELETED)
(note 349 348 0 NOTE_INSN_DELETED)
;; Function main (main, funcdef_no=1, decl_uid=4794, cgraph_uid=1) (executed once)
;; 3 loops found
;;
;; Loop 0
;; header 0, latch 1
;; depth 0, outer -1
;; nodes: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
;;
;; Loop 2
;; header 5, latch 16
;; depth 1, outer 0
;; nodes: 5 16 15 14 13 12 11 10 7
;;
;; Loop 1
;; header 3, latch 3
;; depth 1, outer 0
;; nodes: 3
;; 2 succs { 3 }
;; 3 succs { 3 4 }
;; 4 succs { 5 }
;; 5 succs { 6 7 }
;; 6 succs { }
;; 7 succs { 8 10 }
;; 8 succs { 6 }
;; 9 succs { 1 }
;; 10 succs { 6 11 }
;; 11 succs { 6 12 }
;; 12 succs { 6 13 }
;; 13 succs { 6 14 }
;; 14 succs { 6 15 }
;; 15 succs { 6 16 }
;; 16 succs { 5 17 }
;; 17 succs { 9 }
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
========== no more changes
starting the processing of deferred insns
ending the processing of deferred insns
(note 1 0 5 NOTE_INSN_DELETED)
(note 5 1 324 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 324 5 325 2 (parallel [
(set (mem/c:BLK (pre_modify:SI (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -12 [0xfffffffffffffff4]))) [3 A8])
(unspec:BLK [
(reg:SI 4 r4)
] UNSPEC_PUSH_MULT))
(use (reg:SI 5 r5))
(use (reg:SI 14 lr))
]) /tmp/x.c:25 -1
(expr_list:REG_DEAD (reg:SI 14 lr)
(expr_list:REG_DEAD (reg:SI 5 r5)
(expr_list:REG_DEAD (reg:SI 4 r4)
(expr_list:REG_FRAME_RELATED_EXPR (sequence [
(set/f (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -12 [0xfffffffffffffff4])))
(set/f (mem/c:SI (reg/f:SI 13 sp) [3 S4 A32])
(reg:SI 4 r4))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 4 [0x4])) [3 S4 A32])
(reg:SI 5 r5))
(set/f (mem/c:SI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [3 S4 A32])
(reg:SI 14 lr))
])
(nil))))))
(insn/f 325 324 326 2 (set (reg/f:SI 13 sp)
(plus:SI (reg/f:SI 13 sp)
(const_int -132 [0xffffffffffffff7c]))) /tmp/x.c:25 -1
(nil))
(note 326 325 2 2 NOTE_INSN_PROLOGUE_END)
(note 2 326 9 2 NOTE_INSN_FUNCTION_BEG)
(note 9 2 12 2 NOTE_INSN_DELETED)
(insn 12 9 13 2 (set (reg:SI 0 r0)
(reg/f:SI 13 sp)) /tmp/x.c:27 634 {*arm_movsi_vfp}
(nil))
(insn 13 12 14 2 (set (reg:SI 1 r1)
(symbol_ref:SI ("*.LANCHOR0") [flags 0x182])) /tmp/x.c:27 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (symbol_ref:SI ("*.LANCHOR0") [flags 0x182])
(nil)))
(insn 14 13 15 2 (set (reg:SI 2 r2)
(const_int 128 [0x80])) /tmp/x.c:27 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const_int 128 [0x80])
(nil)))
(call_insn 15 14 78 2 (parallel [
(set (reg:SI 0 r0)
(call (mem:SI (symbol_ref:SI ("memcpy") [flags 0x41] <function_decl 0xb7063b80 memcpy>) [0 memcpy S4 A32])
(const_int 0 [0])))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
]) /tmp/x.c:27 243 {*call_value_symbol}
(expr_list:REG_DEAD (reg:SI 2 r2)
(expr_list:REG_DEAD (reg:SI 1 r1)
(expr_list:REG_UNUSED (reg:SI 0 r0)
(expr_list:REG_EH_REGION (const_int 0 [0])
(nil)))))
(expr_list:REG_DEP_TRUE (use (reg:SI 2 r2))
(expr_list:REG_DEP_TRUE (use (reg:SI 1 r1))
(expr_list:REG_DEP_TRUE (use (reg:SI 0 r0))
(nil)))))
(insn 78 15 80 2 (set (reg/f:SI 0 r0 [170])
(symbol_ref:SI ("arg1") [flags 0x80] <var_decl 0xb7224f60 arg1>)) 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (symbol_ref:SI ("arg1") [flags 0x80] <var_decl 0xb7224f60 arg1>)
(nil)))
(insn 80 78 3 2 (set (reg/f:SI 1 r1 [171])
(symbol_ref:SI ("arg2") [flags 0x80] <var_decl 0xb723d120 arg2>)) 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (symbol_ref:SI ("arg2") [flags 0x80] <var_decl 0xb723d120 arg2>)
(nil)))
(insn 3 80 4 2 (set (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 0 [0])) /tmp/x.c:27 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const_int 0 [0])
(nil)))
(insn 4 3 29 2 (set (reg/v:SI 3 r3 [orig:137 i ] [137])
(reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])) /tmp/x.c:29 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const_int 0 [0])
(nil)))
(code_label 29 4 17 3 15 "" [1 uses])
(note 17 29 21 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 21 17 25 3 (set (mem:SI (plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 3 r3 [orig:137 i ] [137])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 25 21 26 3 (set (mem:SI (plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 3 r3 [orig:137 i ] [137])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 26 25 306 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 306 26 305 3 (set (reg:SI 14 lr [175])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 4 [0x4]))) 4 {*arm_addsi3}
(nil))
(insn 305 306 209 3 (set (reg:SI 12 ip [174])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 1 [0x1]))) /tmp/x.c:29 4 {*arm_addsi3}
(nil))
(insn 209 305 211 3 (set (mem:SI (plus:SI (reg/f:SI 0 r0 [170])
(reg:SI 14 lr [175])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg:SI 12 ip [174])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 211 209 212 3 (set (mem:SI (plus:SI (reg/f:SI 1 r1 [171])
(reg:SI 14 lr [175])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg:SI 12 ip [174])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 14 lr [175])
(expr_list:REG_DEAD (reg:SI 12 ip [174])
(nil))))
(insn 212 211 214 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 214 212 213 3 (set (reg:SI 14 lr [orig:183 ivtmp.139 ] [183])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 8 [0x8]))) 4 {*arm_addsi3}
(nil))
(insn 213 214 223 3 (set (reg/v:SI 12 ip [orig:182 i ] [182])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 2 [0x2]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 14 lr [orig:183 ivtmp.139 ] [183])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 223 213 225 3 (set (mem:SI (plus:SI (reg:SI 14 lr [orig:183 ivtmp.139 ] [183])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 12 ip [orig:182 i ] [182])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 225 223 226 3 (set (mem:SI (plus:SI (reg:SI 14 lr [orig:183 ivtmp.139 ] [183])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 12 ip [orig:182 i ] [182])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 14 lr [orig:183 ivtmp.139 ] [183])
(expr_list:REG_DEAD (reg/v:SI 12 ip [orig:182 i ] [182])
(nil))))
(insn 226 225 228 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 228 226 227 3 (set (reg:SI 12 ip [orig:187 ivtmp.139 ] [187])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 12 [0xc]))) 4 {*arm_addsi3}
(nil))
(insn 227 228 237 3 (set (reg/v:SI 14 lr [orig:186 i ] [186])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 3 [0x3]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 12 ip [orig:187 ivtmp.139 ] [187])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 237 227 239 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:187 ivtmp.139 ] [187])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:186 i ] [186])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 239 237 240 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:187 ivtmp.139 ] [187])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:186 i ] [186])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 14 lr [orig:186 i ] [186])
(expr_list:REG_DEAD (reg:SI 12 ip [orig:187 ivtmp.139 ] [187])
(nil))))
(insn 240 239 242 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 242 240 241 3 (set (reg:SI 12 ip [orig:191 ivtmp.139 ] [191])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 16 [0x10]))) 4 {*arm_addsi3}
(nil))
(insn 241 242 251 3 (set (reg/v:SI 14 lr [orig:190 i ] [190])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 4 [0x4]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 12 ip [orig:191 ivtmp.139 ] [191])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 251 241 253 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:191 ivtmp.139 ] [191])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:190 i ] [190])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 253 251 254 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:191 ivtmp.139 ] [191])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:190 i ] [190])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 14 lr [orig:190 i ] [190])
(expr_list:REG_DEAD (reg:SI 12 ip [orig:191 ivtmp.139 ] [191])
(nil))))
(insn 254 253 256 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 256 254 255 3 (set (reg:SI 12 ip [orig:195 ivtmp.139 ] [195])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 20 [0x14]))) 4 {*arm_addsi3}
(nil))
(insn 255 256 265 3 (set (reg/v:SI 14 lr [orig:194 i ] [194])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 5 [0x5]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 12 ip [orig:195 ivtmp.139 ] [195])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 265 255 267 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:195 ivtmp.139 ] [195])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:194 i ] [194])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 267 265 268 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:195 ivtmp.139 ] [195])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:194 i ] [194])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 14 lr [orig:194 i ] [194])
(expr_list:REG_DEAD (reg:SI 12 ip [orig:195 ivtmp.139 ] [195])
(nil))))
(insn 268 267 270 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 270 268 269 3 (set (reg:SI 12 ip [orig:199 ivtmp.139 ] [199])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 24 [0x18]))) 4 {*arm_addsi3}
(nil))
(insn 269 270 279 3 (set (reg/v:SI 14 lr [orig:198 i ] [198])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 6 [0x6]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 12 ip [orig:199 ivtmp.139 ] [199])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 279 269 281 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:199 ivtmp.139 ] [199])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:198 i ] [198])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 281 279 282 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:199 ivtmp.139 ] [199])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:198 i ] [198])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 14 lr [orig:198 i ] [198])
(expr_list:REG_DEAD (reg:SI 12 ip [orig:199 ivtmp.139 ] [199])
(nil))))
(insn 282 281 284 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 284 282 283 3 (set (reg:SI 12 ip [orig:203 ivtmp.139 ] [203])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 28 [0x1c]))) 4 {*arm_addsi3}
(nil))
(insn 283 284 293 3 (set (reg/v:SI 14 lr [orig:202 i ] [202])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 7 [0x7]))) /tmp/x.c:29 4 {*arm_addsi3}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 12 ip [orig:203 ivtmp.139 ] [203])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(nil)))
(insn 293 283 295 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:203 ivtmp.139 ] [203])
(reg/f:SI 0 r0 [170])) [2 MEM[symbol: arg1, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:202 i ] [202])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(nil))
(insn 295 293 296 3 (set (mem:SI (plus:SI (reg:SI 12 ip [orig:203 ivtmp.139 ] [203])
(reg/f:SI 1 r1 [171])) [2 MEM[symbol: arg2, index: ivtmp.139_24, offset: 0B]+0 S4 A32])
(reg/v:SI 14 lr [orig:202 i ] [202])) /tmp/x.c:31 634 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg/v:SI 14 lr [orig:202 i ] [202])
(expr_list:REG_DEAD (reg:SI 12 ip [orig:203 ivtmp.139 ] [203])
(nil))))
(insn 296 295 297 3 (asm_input/v ("") /tmp/x.c:45) /tmp/x.c:32 -1
(nil))
(insn 297 296 298 3 (set (reg/v:SI 3 r3 [orig:137 i ] [137])
(plus:SI (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 8 [0x8]))) /tmp/x.c:29 4 {*arm_addsi3}
(nil))
(insn 298 297 299 3 (set (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(plus:SI (reg:SI 2 r2 [orig:142 ivtmp.139 ] [142])
(const_int 32 [0x20]))) 4 {*arm_addsi3}
(nil))
(insn 299 298 300 3 (set (reg:CC 24 cc)
(compare:CC (reg/v:SI 3 r3 [orig:137 i ] [137])
(const_int 96 [0x60]))) /tmp/x.c:29 206 {*arm_cmpsi_insn}
(nil))
(jump_insn 300 299 206 3 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 29)
(pc))) /tmp/x.c:29 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 9896 [0x26a8])
(nil)))
-> 29)
(note 206 300 39 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 39 206 40 4 (set (reg:SI 0 r0)
(symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)) /tmp/x.c:35 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)
(nil)))
(insn 40 39 41 4 (set (reg:SI 1 r1)
(symbol_ref:SI ("arg1") [flags 0x80] <var_decl 0xb7224f60 arg1>)) /tmp/x.c:35 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (symbol_ref:SI ("arg1") [flags 0x80] <var_decl 0xb7224f60 arg1>)
(nil)))
(insn 41 40 42 4 (set (reg:SI 2 r2)
(symbol_ref:SI ("arg2") [flags 0x80] <var_decl 0xb723d120 arg2>)) /tmp/x.c:35 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (symbol_ref:SI ("arg2") [flags 0x80] <var_decl 0xb723d120 arg2>)
(nil)))
(call_insn 42 41 43 4 (parallel [
(call (mem:SI (symbol_ref:SI ("f883b") [flags 0x3] <function_decl 0xb7223e80 f883b>) [0 f883b S4 A32])
(const_int 0 [0]))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
]) /tmp/x.c:35 242 {*call_symbol}
(expr_list:REG_DEAD (reg:SI 2 r2)
(expr_list:REG_DEAD (reg:SI 1 r1)
(expr_list:REG_DEAD (reg:SI 0 r0)
(expr_list:REG_EH_REGION (const_int 0 [0])
(nil)))))
(expr_list:REG_DEP_TRUE (use (reg:SI 2 r2))
(expr_list:REG_DEP_TRUE (use (reg:SI 1 r1))
(expr_list:REG_DEP_TRUE (use (reg:SI 0 r0))
(nil)))))
(insn 43 42 45 4 (set (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const:SI (plus:SI (symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)
(const_int 47 [0x2f])))) 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const:SI (plus:SI (symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)
(const_int 47 [0x2f])))
(nil)))
(insn 45 43 48 4 (set (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(plus:SI (reg/f:SI 13 sp)
(const_int -4 [0xfffffffffffffffc]))) 4 {*arm_addsi3}
(expr_list:REG_EQUAL (plus:SI (reg/f:SI 13 sp)
(const_int -4 [0xfffffffffffffffc]))
(nil)))
(insn 48 45 61 4 (set (reg/f:SI 12 ip [orig:151 D.6566 ] [151])
(plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 32 [0x20]))) /tmp/x.c:24 4 {*arm_addsi3}
(expr_list:REG_EQUIV (const:SI (plus:SI (symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)
(const_int 79 [0x4f])))
(nil)))
(code_label 61 48 49 5 17 "" [1 uses])
(note 49 61 52 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 52 49 197 5 (set (reg:SI 5 r5 [orig:167 MEM[base: D.6563_36, offset: 0B] ] [167])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 1 [0x1])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 197 52 53 5 (set (reg:SI 0 r0 [172])
(plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 1 [0x1]))) 4 {*arm_addsi3}
(nil))
(insn 53 197 198 5 (set (reg:SI 4 r4 [orig:168 MEM[base: D.6564_37, offset: 0B] ] [168])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 4 [0x4])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 4 [0x4])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 198 53 54 5 (set (reg:SI 1 r1 [173])
(plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 4 [0x4]))) 4 {*arm_addsi3}
(nil))
(insn 54 198 55 5 (set (reg:CC 24 cc)
(compare:CC (reg:SI 5 r5 [orig:167 MEM[base: D.6563_36, offset: 0B] ] [167])
(reg:SI 4 r4 [orig:168 MEM[base: D.6564_37, offset: 0B] ] [168]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(nil))
(jump_insn 55 54 315 5 (set (pc)
(if_then_else (eq (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref 59)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 9996 [0x270c])
(nil)))
-> 59)
(code_label 315 55 56 6 41 "" [7 uses])
(note 56 315 57 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(call_insn 57 56 58 6 (parallel [
(call (mem:SI (symbol_ref:SI ("abort") [flags 0x41] <function_decl 0xb72bb400 abort>) [0 __builtin_abort S4 A32])
(const_int 0 [0]))
(use (const_int 0 [0]))
(clobber (reg:SI 14 lr))
]) /tmp/x.c:41 242 {*call_symbol}
(expr_list:REG_NORETURN (const_int 0 [0])
(expr_list:REG_EH_REGION (const_int 0 [0])
(nil)))
(nil))
(barrier 58 57 59)
(code_label 59 58 60 7 16 "" [1 uses])
(note 60 59 88 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(insn 88 60 89 7 (set (reg:SI 0 r0 [orig:210 MEM[base: D.6563_36, offset: 0B] ] [210])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 0 r0 [172])
(const_int 1 [0x1])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 89 88 90 7 (set (reg:SI 1 r1 [orig:211 MEM[base: D.6564_37, offset: 0B] ] [211])
(mem:SI (plus:SI (reg:SI 1 r1 [173])
(const_int 4 [0x4])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(nil))
(insn 90 89 91 7 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:210 MEM[base: D.6563_36, offset: 0B] ] [210])
(reg:SI 1 r1 [orig:211 MEM[base: D.6564_37, offset: 0B] ] [211]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:211 MEM[base: D.6564_37, offset: 0B] ] [211])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:210 MEM[base: D.6563_36, offset: 0B] ] [210])
(nil))))
(jump_insn 91 90 314 7 (set (pc)
(if_then_else (eq (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 99)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 9996 [0x270c])
(nil)))
-> 99)
(note 314 91 316 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(jump_insn 316 314 317 8 (set (pc)
(label_ref 315)) 230 {*arm_jump}
(nil)
-> 315)
(barrier 317 316 319)
(code_label 319 317 64 9 42 "" [1 uses])
(note 64 319 69 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(insn 69 64 72 9 (set (reg/i:SI 0 r0)
(const_int 0 [0])) /tmp/x.c:45 634 {*arm_movsi_vfp}
(expr_list:REG_EQUAL (const_int 0 [0])
(nil)))
(insn 72 69 327 9 (use (reg/i:SI 0 r0)) /tmp/x.c:45 -1
(nil))
(note 327 72 328 9 NOTE_INSN_EPILOGUE_BEG)
(jump_insn 328 327 329 9 (unspec_volatile [
(return)
] VUNSPEC_EPILOGUE) /tmp/x.c:45 -1
(nil)
-> return)
(barrier 329 328 99)
(code_label 99 329 96 10 20 "" [1 uses])
(note 96 99 104 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(insn 104 96 105 10 (set (reg:SI 0 r0 [orig:214 MEM[base: D.6563_36, offset: 0B] ] [214])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 3 [0x3])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 105 104 106 10 (set (reg:SI 1 r1 [orig:215 MEM[base: D.6564_37, offset: 0B] ] [215])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 12 [0xc])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 12 [0xc])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 106 105 107 10 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:214 MEM[base: D.6563_36, offset: 0B] ] [214])
(reg:SI 1 r1 [orig:215 MEM[base: D.6564_37, offset: 0B] ] [215]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:215 MEM[base: D.6564_37, offset: 0B] ] [215])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:214 MEM[base: D.6563_36, offset: 0B] ] [214])
(nil))))
(jump_insn 107 106 112 10 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 112 107 120 11 [bb 11] NOTE_INSN_BASIC_BLOCK)
(insn 120 112 121 11 (set (reg:SI 0 r0 [orig:218 MEM[base: D.6563_36, offset: 0B] ] [218])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 4 [0x4])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 121 120 122 11 (set (reg:SI 1 r1 [orig:219 MEM[base: D.6564_37, offset: 0B] ] [219])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 16 [0x10])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 16 [0x10])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 122 121 123 11 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:218 MEM[base: D.6563_36, offset: 0B] ] [218])
(reg:SI 1 r1 [orig:219 MEM[base: D.6564_37, offset: 0B] ] [219]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:219 MEM[base: D.6564_37, offset: 0B] ] [219])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:218 MEM[base: D.6563_36, offset: 0B] ] [218])
(nil))))
(jump_insn 123 122 128 11 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 128 123 136 12 [bb 12] NOTE_INSN_BASIC_BLOCK)
(insn 136 128 137 12 (set (reg:SI 0 r0 [orig:222 MEM[base: D.6563_36, offset: 0B] ] [222])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 5 [0x5])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 137 136 138 12 (set (reg:SI 1 r1 [orig:223 MEM[base: D.6564_37, offset: 0B] ] [223])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 20 [0x14])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 20 [0x14])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 138 137 139 12 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:222 MEM[base: D.6563_36, offset: 0B] ] [222])
(reg:SI 1 r1 [orig:223 MEM[base: D.6564_37, offset: 0B] ] [223]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:223 MEM[base: D.6564_37, offset: 0B] ] [223])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:222 MEM[base: D.6563_36, offset: 0B] ] [222])
(nil))))
(jump_insn 139 138 144 12 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 144 139 152 13 [bb 13] NOTE_INSN_BASIC_BLOCK)
(insn 152 144 153 13 (set (reg:SI 0 r0 [orig:226 MEM[base: D.6563_36, offset: 0B] ] [226])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 6 [0x6])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 153 152 154 13 (set (reg:SI 1 r1 [orig:227 MEM[base: D.6564_37, offset: 0B] ] [227])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 24 [0x18])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 24 [0x18])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 154 153 155 13 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:226 MEM[base: D.6563_36, offset: 0B] ] [226])
(reg:SI 1 r1 [orig:227 MEM[base: D.6564_37, offset: 0B] ] [227]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:227 MEM[base: D.6564_37, offset: 0B] ] [227])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:226 MEM[base: D.6563_36, offset: 0B] ] [226])
(nil))))
(jump_insn 155 154 160 13 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 160 155 168 14 [bb 14] NOTE_INSN_BASIC_BLOCK)
(insn 168 160 169 14 (set (reg:SI 0 r0 [orig:230 MEM[base: D.6563_36, offset: 0B] ] [230])
(sign_extend:SI (mem:QI (plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 7 [0x7])) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(nil))
(insn 169 168 170 14 (set (reg:SI 1 r1 [orig:231 MEM[base: D.6564_37, offset: 0B] ] [231])
(mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 28 [0x1c])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_EQUIV (mem:SI (plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 28 [0x1c])) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])
(nil)))
(insn 170 169 171 14 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:230 MEM[base: D.6563_36, offset: 0B] ] [230])
(reg:SI 1 r1 [orig:231 MEM[base: D.6564_37, offset: 0B] ] [231]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:231 MEM[base: D.6564_37, offset: 0B] ] [231])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:230 MEM[base: D.6563_36, offset: 0B] ] [230])
(nil))))
(jump_insn 171 170 176 14 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 176 171 184 15 [bb 15] NOTE_INSN_BASIC_BLOCK)
(insn 184 176 185 15 (set (reg:SI 0 r0 [orig:232 MEM[base: D.6563_36, offset: 0B] ] [232])
(sign_extend:SI (mem:QI (pre_modify:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(plus:SI (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const_int 8 [0x8]))) [0 MEM[base: D.6563_36, offset: 0B]+0 S1 A8]))) /tmp/x.c:38 170 {*arm_extendqisi_v6}
(expr_list:REG_INC (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(nil)))
(insn 185 184 186 15 (set (reg:SI 1 r1 [orig:233 MEM[base: D.6564_37, offset: 0B] ] [233])
(mem:SI (pre_modify:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(plus:SI (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(const_int 32 [0x20]))) [2 MEM[base: D.6564_37, offset: 0B]+0 S4 A32])) /tmp/x.c:38 634 {*arm_movsi_vfp}
(expr_list:REG_INC (reg:SI 2 r2 [orig:147 ivtmp.122 ] [147])
(nil)))
(insn 186 185 187 15 (set (reg:CC 24 cc)
(compare:CC (reg:SI 0 r0 [orig:232 MEM[base: D.6563_36, offset: 0B] ] [232])
(reg:SI 1 r1 [orig:233 MEM[base: D.6564_37, offset: 0B] ] [233]))) /tmp/x.c:38 206 {*arm_cmpsi_insn}
(expr_list:REG_DEAD (reg:SI 1 r1 [orig:233 MEM[base: D.6564_37, offset: 0B] ] [233])
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:232 MEM[base: D.6563_36, offset: 0B] ] [232])
(nil))))
(jump_insn 187 186 192 15 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 315)
(pc))) /tmp/x.c:38 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 4 [0x4])
(nil)))
-> 315)
(note 192 187 190 16 [bb 16] NOTE_INSN_BASIC_BLOCK)
(insn 190 192 191 16 (set (reg:CC 24 cc)
(compare:CC (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(reg/f:SI 12 ip [orig:151 D.6566 ] [151]))) /tmp/x.c:37 206 {*arm_cmpsi_insn}
(expr_list:REG_EQUAL (compare:CC (reg:SI 3 r3 [orig:146 ivtmp.114 ] [146])
(const:SI (plus:SI (symbol_ref:SI ("result") [flags 0x80] <var_decl 0xb7224de0 result>)
(const_int 79 [0x4f]))))
(nil)))
(jump_insn 191 190 318 16 (set (pc)
(if_then_else (ne (reg:CC 24 cc)
(const_int 0 [0]))
(label_ref:SI 61)
(pc))) /tmp/x.c:37 218 {*arm_cond_branch}
(expr_list:REG_DEAD (reg:CC 24 cc)
(expr_list:REG_BR_PROB (const_int 9687 [0x25d7])
(nil)))
-> 61)
(note 318 191 320 17 [bb 17] NOTE_INSN_BASIC_BLOCK)
(jump_insn 320 318 321 17 (set (pc)
(label_ref 319)) 230 {*arm_jump}
(nil)
-> 319)
(barrier 321 320 322)
(note 322 321 0 NOTE_INSN_DELETED)
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: regrename and odd behaviour with early clobber operands
2011-08-16 6:40 regrename and odd behaviour with early clobber operands Ramana Radhakrishnan
@ 2011-08-16 15:25 ` Richard Sandiford
2011-08-18 8:10 ` Ramana Radhakrishnan
0 siblings, 1 reply; 3+ messages in thread
From: Richard Sandiford @ 2011-08-16 15:25 UTC (permalink / raw)
To: Ramana Radhakrishnan; +Cc: gcc
Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> writes:
> I can't see how it is right to construct essentially 2 chains for the
> same register that have overlapping live ranges without an intervening
> conditional branch and since regrename sort of works inside a bb .
> Ideally the chain for 122 should have been terminated at the end of
> 123 rather than allowing this to remain open and have the use in insn
> 141 available for use in both chains starting at 122 and 140 . What
> I'm not sure is which part of regrename makes sure that this part of
> the comment for Stage 5 is ensured.
>
> `and earlier
> chains they would overlap with must have been closed at
> the previous insn at the latest, as such operands cannot
> possibly overlap with any input operands. */'
Just to summarise on-list what we talked about on IRC: this is supposed
to happen through REG_DEAD notes. The bug in this case appears to be
that the required note is missing.
The patch below seems to fix things. If it's right, I'm very surprised
we hadn't noticed until now. There must be something else going on...
Richard
Index: gcc/df-problems.c
===================================================================
--- gcc/df-problems.c 2011-07-11 12:21:33.000000000 +0100
+++ gcc/df-problems.c 2011-08-16 16:18:52.333237669 +0100
@@ -3376,7 +3376,7 @@ df_note_bb_compute (unsigned int bb_inde
while (*mws_rec)
{
struct df_mw_hardreg *mws = *mws_rec;
- if ((DF_MWS_REG_DEF_P (mws))
+ if ((DF_MWS_REG_USE_P (mws))
&& !df_ignore_stack_reg (mws->start_regno))
{
bool really_add_notes = debug_insn != 0;
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: regrename and odd behaviour with early clobber operands
2011-08-16 15:25 ` Richard Sandiford
@ 2011-08-18 8:10 ` Ramana Radhakrishnan
0 siblings, 0 replies; 3+ messages in thread
From: Ramana Radhakrishnan @ 2011-08-18 8:10 UTC (permalink / raw)
To: Ramana Radhakrishnan, gcc, richard.sandiford
On 16 August 2011 16:24, Richard Sandiford <richard.sandiford@linaro.org> wrote:
> Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> writes:
>> I can't see how it is right to construct essentially 2 chains for the
>> same register that have overlapping live ranges without an intervening
>> conditional branch and since regrename sort of works inside a bb .
>> Ideally the chain for 122 should have been terminated at the end of
>> 123 rather than allowing this to remain open and have the use in insn
>> 141 available for use in both chains starting at 122 and 140 . What
>> I'm not sure is which part of regrename makes sure that this part of
>> the comment for Stage 5 is ensured.
>>
>> `and earlier
>> chains they would overlap with must have been closed at
>> the previous insn at the latest, as such operands cannot
>> possibly overlap with any input operands. */'
>
> Just to summarise on-list what we talked about on IRC: this is supposed
> to happen through REG_DEAD notes. The bug in this case appears to be
> that the required note is missing.
>
> The patch below seems to fix things. If it's right, I'm very surprised
> we hadn't noticed until now. There must be something else going on...
I've been digging a bit yesterday afternoon and reading the code it appears
as though if you are to check for multiword-register uses you do need
to check the macro DF_MWS_REG_USE_P (mws). I suspect if you don't look
at that you really aren't looking at what multiword-registers an
instruction really uses.
Interestingly your patch managed to survive a bootstrap and testrun on
x86 with no regressions.
Ramana
>
> Richard
>
>
> Index: gcc/df-problems.c
> ===================================================================
> --- gcc/df-problems.c 2011-07-11 12:21:33.000000000 +0100
> +++ gcc/df-problems.c 2011-08-16 16:18:52.333237669 +0100
> @@ -3376,7 +3376,7 @@ df_note_bb_compute (unsigned int bb_inde
> while (*mws_rec)
> {
> struct df_mw_hardreg *mws = *mws_rec;
> - if ((DF_MWS_REG_DEF_P (mws))
> + if ((DF_MWS_REG_USE_P (mws))
> && !df_ignore_stack_reg (mws->start_regno))
> {
> bool really_add_notes = debug_insn != 0;
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2011-08-18 8:10 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2011-08-16 15:25 ` Richard Sandiford
2011-08-18 8:10 ` Ramana Radhakrishnan
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