clobber CC for arithmetic instructions

clobber CC for arithmetic instructions

[Rohit Arul Raj]

Hello All,

I am working on 32-bit target with gcc 4.6.0. I need some help on the following:

For my target, If my CCR register is set, all the arithmetic
instructions update the CC register else the don't update.
Setting the CCR register is done by a built-in function.

Can any one help how to proceed with this? or any other target where a
similar case has been implemented?

Thanks,
Rohit

Re: clobber CC for arithmetic instructions

[Rohit Arul Raj]

On Fri, Aug 12, 2011 at 12:17 PM, Rohit Arul Raj <rohitarulraj@gmail.com> wrote:
> Hello All,
>
> I am working on 32-bit target with gcc 4.6.0. I need some help on the following:
>
> For my target, If my CCR register is set, all the arithmetic
> instructions update the CC register else the don't update.
> Setting the CCR register is done by a built-in function.
>
> Can any one help how to proceed with this? or any other target where a
> similar case has been implemented?
>
> Thanks,
> Rohit
>

Adding more info:

Note: There is 2 cycle latency between compare and branch instructions.

A) Without CCR register being set.

     cmp insn
     branch insn

     Here i can insert any arithmetic instruction e.g. 'addsi'
in-between 'cmp' and 'branch' as the CC register doesn't get modified.

B) With CCR register being set.

     Here i cannot insert any arithmetic instruction e.g. 'addsi'
in-between 'cmp' and 'branch' as the CC register will get modified.

~Rohit

Re: clobber CC for arithmetic instructions

[Richard Guenther]

On Fri, Aug 12, 2011 at 11:48 AM, Rohit Arul Raj <rohitarulraj@gmail.com> wrote:
> On Fri, Aug 12, 2011 at 12:17 PM, Rohit Arul Raj <rohitarulraj@gmail.com> wrote:
>> Hello All,
>>
>> I am working on 32-bit target with gcc 4.6.0. I need some help on the following:
>>
>> For my target, If my CCR register is set, all the arithmetic
>> instructions update the CC register else the don't update.
>> Setting the CCR register is done by a built-in function.
>>
>> Can any one help how to proceed with this? or any other target where a
>> similar case has been implemented?
>>
>> Thanks,
>> Rohit
>>
>
> Adding more info:
>
> Note: There is 2 cycle latency between compare and branch instructions.
>
> A) Without CCR register being set.
>
>     cmp insn
>     branch insn
>
>     Here i can insert any arithmetic instruction e.g. 'addsi'
> in-between 'cmp' and 'branch' as the CC register doesn't get modified.
>
> B) With CCR register being set.
>
>     Here i cannot insert any arithmetic instruction e.g. 'addsi'
> in-between 'cmp' and 'branch' as the CC register will get modified.

What does the ABI say about the CCR register state on function entry?
1) Implement that and disallow modifying the CCR register.
2) Add a -mccr flag and make the backend assume nothing about the
contents of the CCR register (I suppose a cmp instruction will nevertheless
modify CC), similar to how we have -frounding-math

If you want to exploit CCR in your backend you probably want to do so
late in machine reorg.

Richard.

> ~Rohit
>

Re: clobber CC for arithmetic instructions

[Hans-Peter Nilsson]

On Fri, 12 Aug 2011, Rohit Arul Raj wrote:
> On Fri, Aug 12, 2011 at 12:17 PM, Rohit Arul Raj <rohitarulraj@gmail.com> wrote:
> > Hello All,
> >
> > I am working on 32-bit target with gcc 4.6.0. I need some help on the following:
> >
> > For my target, If my CCR register is set, all the arithmetic
> > instructions update the CC register else the don't update.

So you have a control register called CCR and a status register
called CC?

> > Setting the CCR register is done by a built-in function.

Why is this user-controllable?
My first thought is that this is misguided.
Is this just a sketch or do you already have code using it?

> > Can any one help how to proceed with this? or any other target where a
> > similar case has been implemented?
> >
> > Thanks,
> > Rohit
> >
>
> Adding more info:
>
> Note: There is 2 cycle latency between compare and branch instructions.
>
> A) Without CCR register being set.
>
>      cmp insn
>      branch insn
>
>      Here i can insert any arithmetic instruction e.g. 'addsi'
> in-between 'cmp' and 'branch' as the CC register doesn't get modified.

Assuming that you can indeed emit reasonable code for compares
and conditional branches without the "CCR register" set to the
do-not-update state, I'd suggest you implement that.  Forget
about the builtin; don't implement it.

Some time later, when you're sufficiently acquinted with gcc
internals, maybe improve the generated code using the
always-update state if you can indeed spot generated code that
could be improved that way.  Don't do this for at least a few
months.  If there is no such code, forget about the
CCR=always-update state.

In either case, never mention (cc0) in your .md file.

brgds, H-P

Re: clobber CC for arithmetic instructions

[Hans-Peter Nilsson]

On Fri, 12 Aug 2011, Hans-Peter Nilsson wrote:
> On Fri, 12 Aug 2011, Rohit Arul Raj wrote:
> Assuming that you can indeed emit reasonable code for compares
> and conditional branches without the "CCR register" set to the
> do-not-update state, I'd suggest you implement that

Sorry for the miswrite: I meant 'without the "CCR register" set
to the always-update state' (with the "CCR register" constantly
set to the do-not-update state).

brgds, H-P

Re: clobber CC for arithmetic instructions

[Rohit Arul Raj]

On Sat, Aug 13, 2011 at 5:20 AM, Hans-Peter Nilsson <hp@bitrange.com> wrote:
> On Fri, 12 Aug 2011, Rohit Arul Raj wrote:
>> On Fri, Aug 12, 2011 at 12:17 PM, Rohit Arul Raj <rohitarulraj@gmail.com> wrote:
>> > Hello All,
>> >
>> > I am working on 32-bit target with gcc 4.6.0. I need some help on the following:
>> >
>> > For my target, If my CCR register is set, all the arithmetic
>> > instructions update the CC register else the don't update.
>
> So you have a control register called CCR and a status register
> called CC?

Yes.

>> > Setting the CCR register is done by a built-in function.
>
> Why is this user-controllable?
> My first thought is that this is misguided.
> Is this just a sketch or do you already have code using it?
>

We already have code using this :).


>> > Can any one help how to proceed with this? or any other target where a
>> > similar case has been implemented?
>> >
>> > Thanks,
>> > Rohit
>> >
>>
>> Adding more info:
>>
>> Note: There is 2 cycle latency between compare and branch instructions.
>>
>> A) Without CCR register being set.
>>
>>      cmp insn
>>      branch insn
>>
>>      Here i can insert any arithmetic instruction e.g. 'addsi'
>> in-between 'cmp' and 'branch' as the CC register doesn't get modified.
>
> Assuming that you can indeed emit reasonable code for compares
> and conditional branches without the "CCR register" set to the
> do-not-update state, I'd suggest you implement that.  Forget
> about the builtin; don't implement it.
>
> Some time later, when you're sufficiently acquinted with gcc
> internals, maybe improve the generated code using the
> always-update state if you can indeed spot generated code that
> could be improved that way.  Don't do this for at least a few
> months.  If there is no such code, forget about the
> CCR=always-update state.
>
> In either case, never mention (cc0) in your .md file.
>
> brgds, H-P
>

Thank You,
Rohit

Re: clobber CC for arithmetic instructions

[Hans-Peter Nilsson]

On Wed, 17 Aug 2011, Rohit Arul Raj wrote:
> On Sat, Aug 13, 2011 at 5:20 AM, Hans-Peter Nilsson <hp@bitrange.com> wrote:
> >> On Fri, Aug 12, 2011 at 12:17 PM, Rohit Arul Raj <rohitarulraj@gmail.com> wrote:
> >> > Setting the CCR register is done by a built-in function.
> >
> > Why is this user-controllable?

?

> > My first thought is that this is misguided.
> > Is this just a sketch or do you already have code using it?
> >
>
> We already have code using this :).

Hm.  Well, I don't see how user code can observe the state other
than through asms or called functions so you could supposedly
just set a variable in the builtin and set CCR to that value
before an asm, call or return...  But now I'm telling you
obvious things.  Good luck.

brgds, H-P