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From: Kinsey Moore <kinsey.moore@oarcorp.com>
To: gcc@gcc.gnu.org
Cc: Joel Sherrill <joel.sherrill@oarcorp.com>
Subject: ARM Cortex-R5F Support
Date: Tue, 1 Mar 2022 10:23:06 -0600	[thread overview]
Message-ID: <cb5c7cdd-d41a-b930-9179-d18d9bcf2e3f@oarcorp.com> (raw)

Hi,

I'm looking at working on Cortex-R5F support for RTEMS, but it seems as 
if latest GCC supports the Cortex-R5. This R5 has implicit FPU support 
which would make it really R5F. The ARM reference page on this core 
(https://developer.arm.com/Processors/Cortex-R5) specifies that the FPU 
is optional. I see that the FPU support can probably be disabled using 
the nofp option to achieve Cortex-R5 support, but I was wondering why 
this is handled differently from the Cortex-R4[F] support since that is 
broken out into two different CPU entries in gcc/config/arm/arm-cpus.in. 
It appears that R7 and R8 are handled the same way as R5.

Is the R4/R4F just the legacy way of handling this and R5/7/8 are the 
new way?


Thanks,

Kinsey


             reply	other threads:[~2022-03-01 16:23 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-01 16:23 Kinsey Moore [this message]
2022-03-02 11:49 ` Richard Earnshaw
2022-03-02 14:06   ` Kinsey Moore

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