From: Jeff Law <jeffreyalaw@gmail.com>
To: Vineet Gupta <vineetg@rivosinc.com>, Jakub Jelinek <jakub@redhat.com>
Cc: gcc@gcc.gnu.org, Michael Collison <collison@rivosinc.com>
Subject: Re: query about commit 666fdc46bc8489 ("RISC-V: Fix bad insn splits with paradoxical subregs")
Date: Fri, 4 Nov 2022 17:47:24 -0600 [thread overview]
Message-ID: <d64dbcf6-75fe-4f08-faaa-d0dde964fd3b@gmail.com> (raw)
In-Reply-To: <1202fdda-12b7-8e75-a327-9b7888d4af9d@rivosinc.com>
On 11/4/22 17:38, Vineet Gupta wrote:
>> commit 666fdc46bc848984ee7d2906f2dfe10e1ee5d535
>> Author: Jim Wilson <jimw@sifive.com>
>> Date: Sat Jun 30 21:52:01 2018 +0000
>>
>> RISC-V: Add patterns to convert AND mask to two shifts.
>>
>> gcc/
>> * config/riscv/predicates.md (p2m1_shift_operand): New.
>> (high_mask_shift_operand): New.
>
> Indeed Jim introduced the pattern with 666fdc46bc8, but the clobber
> was added later in 36ec3f57d305 ("RISC-V: Fix bad insn splits with
> paradoxical subregs"). He attributed this to Jakub, and with Jim not
> being super active these days, I tried reaching out to this cc list.
>
> Sorry I pasted wrong sha-id in my orig msg, it needs to be 36ec3f57d305
I'd look at the testcases in that hash. I bet you're going to find one
where we have a paradoxical subreg destination. We can't shift bits
into the paradoxical part, then expect to safely shift them back in.
The semantics of a paradoxical subreg are that the bits outside the
inner mode are don't cares. Of course you *may* need to go back to a
compiler a that point in time to see the problematical case.
Jeff
prev parent reply other threads:[~2022-11-04 23:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-04 22:59 Vineet Gupta
2022-11-04 23:13 ` Jeff Law
2022-11-04 23:38 ` Vineet Gupta
2022-11-04 23:47 ` Jeff Law [this message]
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