Re: query about commit 666fdc46bc8489 ("RISC-V: Fix bad insn splits with paradoxical subregs")

[Jeff Law <jeffreyalaw@gmail.com>]

On 11/4/22 16:59, Vineet Gupta wrote:
> Hi Jakub,
>
> I had a question about the aforementioned commit in RV backend.
>
> (define_split
>   [(set (match_operand:GPR 0 "register_operand")
>     (and:GPR (match_operand:GPR 1 "register_operand")
>                (match_operand:GPR 2 "p2m1_shift_operand")))
> +   (clobber (match_operand:GPR 3 "register_operand"))]
>   ""
> -  [(set (match_dup 0)
> +  [(set (match_dup 3)
>        (ashift:GPR (match_dup 1) (match_dup 2)))
>
> Is there something specific to this split which warrants this or so 
> any split patterns involving shifts have this to avoid the shifting by 
> more than SUBREG_REG problem.

Not sure.  Note it was Jim Wilson's change, not Jakub's change AFAICT:


commit 666fdc46bc848984ee7d2906f2dfe10e1ee5d535
Author: Jim Wilson <jimw@sifive.com>
Date:   Sat Jun 30 21:52:01 2018 +0000

     RISC-V: Add patterns to convert AND mask to two shifts.

             gcc/
             * config/riscv/predicates.md (p2m1_shift_operand): New.
             (high_mask_shift_operand): New.
             * config/riscv/riscv.md (lshrsi3_zero_extend_3+1): New combiner
             pattern using p2m1_shift_operand.
             (lshsi3_zero_extend_3+2): New combiner pattern using
             high_mask_shift_operand.

             gcc/testsuite/
             * gcc.target/riscv/shift-shift-1.c: New.
             * gcc.target/riscv/shift-shift-2.c: New.
             * gcc.target/riscv/shift-shift-3.c: New.

     From-SVN: r262278

You might find further discussion in the gcc-patches archives.


>
> Also could you please explain where the clobber itself is allocated ?

I'd expect the combiner.   There's going to be 2 or more insns that are 
combined to create this pattern where the output of one feeds a 
subsequent insn and dies.  So it's effectively a temporary.  Combine 
will re-use that temporary as the clobbered operand.


Jeff