Difficulties in merging patterns

Difficulties in merging patterns

[Richard Biener]

I'm trying to merge

(define_insn "avx_addsubv4df3"
  [(set (match_operand:V4DF 0 "register_operand" "=x")
        (vec_merge:V4DF
          (minus:V4DF
            (match_operand:V4DF 1 "register_operand" "x")
            (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
          (plus:V4DF (match_dup 1) (match_dup 2))
          (const_int 5)))]
  "TARGET_AVX"
  "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
  [(set_attr "type" "sseadd")
   (set_attr "prefix" "vex")
   (set_attr "mode" "V4DF")])

(define_insn "sse3_addsubv2df3"
  [(set (match_operand:V2DF 0 "register_operand" "=x,x")
        (vec_merge:V2DF
          (minus:V2DF
            (match_operand:V2DF 1 "register_operand" "0,x")
            (match_operand:V2DF 2 "vector_operand" "xBm,xm"))
          (plus:V2DF (match_dup 1) (match_dup 2))
          (const_int 1)))]
  "TARGET_SSE3"
  "@
   addsubpd\t{%2, %0|%0, %2}
   vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
  [(set_attr "isa" "noavx,avx")
   (set_attr "type" "sseadd")
   (set_attr "atom_unit" "complex")
   (set_attr "prefix" "orig,vex")
   (set_attr "mode" "V2DF")])

(define_insn "avx_addsubv8sf3"
  [(set (match_operand:V8SF 0 "register_operand" "=x")
        (vec_merge:V8SF
          (minus:V8SF
            (match_operand:V8SF 1 "register_operand" "x")
            (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
          (plus:V8SF (match_dup 1) (match_dup 2))
          (const_int 85)))]
  "TARGET_AVX"
  "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
  [(set_attr "type" "sseadd")
   (set_attr "prefix" "vex")
   (set_attr "mode" "V8SF")])

(define_insn "sse3_addsubv4sf3"
  [(set (match_operand:V4SF 0 "register_operand" "=x,x")
        (vec_merge:V4SF
          (minus:V4SF
            (match_operand:V4SF 1 "register_operand" "0,x")
            (match_operand:V4SF 2 "vector_operand" "xBm,xm"))
          (plus:V4SF (match_dup 1) (match_dup 2))
          (const_int 5)))]
  "TARGET_SSE3"
  "@
   addsubps\t{%2, %0|%0, %2}
   vaddsubps\t{%2, %1, %0|%0, %1, %2}"
  [(set_attr "isa" "noavx,avx")
   (set_attr "type" "sseadd")
   (set_attr "prefix" "orig,vex")
   (set_attr "prefix_rep" "1,*")
   (set_attr "mode" "V4SF")])

but the difficulty is in the (const_int ..) operand to (vec_merge ..).
I've tried sth like

(define_mode_attr addsub_cst [(V4DF "(const_int 5)") (V2DF "(const_int 
1)")
                              (V4SF "(const_int 5)") (V8SF "(const_int 
85)")])
(define_insn "vec_addsub<mode>"
  [(set (match_operand:VF_128_256 0 "register_operand" "=x")
        (vec_merge:VF_128_256
          (minus:VF_128_256
            (match_operand:VF_128_256 1 "register_operand" "x")
            (match_operand:VF_128_256 2 "nonimmediate_operand" "xm"))
          (plus:VF_128_256 (match_dup 1) (match_dup 2))
          ADDSUB_CST))]
  ""
  "%vaddsub<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"

but genpreds doesn't like whatever syntax I try to use at this place
<addsub_cst> (<addsub_cst>), ...

Is this somehow possible and is there an existing example I can look at?

Thanks,
Richard.

Re: Difficulties in merging patterns

[Jakub Jelinek]

On Thu, Jun 17, 2021 at 03:21:05PM +0200, Richard Biener wrote:
> but the difficulty is in the (const_int ..) operand to (vec_merge ..).
> I've tried sth like
> 
> (define_mode_attr addsub_cst [(V4DF "(const_int 5)") (V2DF "(const_int 
> 1)")
>                               (V4SF "(const_int 5)") (V8SF "(const_int 
> 85)")])

Have you tried making addsub_cst just "5" "1" or "85" and use (const_int
<addsub_cst>)?
If even that doesn't work, make it (match_operand ... "const_int_operand" "n")
and check the value in the insn condition using INTVAL (operands[xxx]) == <addsub_cst>
?

> (define_insn "vec_addsub<mode>"
>   [(set (match_operand:VF_128_256 0 "register_operand" "=x")
>         (vec_merge:VF_128_256
>           (minus:VF_128_256
>             (match_operand:VF_128_256 1 "register_operand" "x")
>             (match_operand:VF_128_256 2 "nonimmediate_operand" "xm"))
>           (plus:VF_128_256 (match_dup 1) (match_dup 2))
>           ADDSUB_CST))]
>   ""
>   "%vaddsub<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
> 
> but genpreds doesn't like whatever syntax I try to use at this place
> <addsub_cst> (<addsub_cst>), ...
> 
> Is this somehow possible and is there an existing example I can look at?
> 
> Thanks,
> Richard.

	Jakub

Re: Difficulties in merging patterns

[Richard Biener]

On Thu, 17 Jun 2021, Jakub Jelinek wrote:

> On Thu, Jun 17, 2021 at 03:21:05PM +0200, Richard Biener wrote:
> > but the difficulty is in the (const_int ..) operand to (vec_merge ..).
> > I've tried sth like
> > 
> > (define_mode_attr addsub_cst [(V4DF "(const_int 5)") (V2DF "(const_int 
> > 1)")
> >                               (V4SF "(const_int 5)") (V8SF "(const_int 
> > 85)")])
> 
> Have you tried making addsub_cst just "5" "1" or "85" and use (const_int
> <addsub_cst>)?

Ah, that works!  Now I only have to figure out the correct attributes
and alternatives.  For reference, this is what I have at the moment.
Will play further tomorrow.

(define_mode_attr addsub_cst [(V4DF "5") (V2DF "1")
                              (V4SF "5") (V8SF "85")])
(define_insn "vec_addsub<mode>3"
  [(set (match_operand:VF_128_256 0 "register_operand" "=x")
        (vec_merge:VF_128_256
          (minus:VF_128_256
            (match_operand:VF_128_256 1 "register_operand" "x")
            (match_operand:VF_128_256 2 "nonimmediate_operand" "xm"))
          (plus:VF_128_256 (match_dup 1) (match_dup 2))
          (const_int <addsub_cst>)))]
  "TARGET_SSE3"
  "%vaddsub<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
  [(set_attr "type" "sseadd")
   (set_attr "prefix" "vex")
   (set_attr "mode" "<MODE>")])

Richard.