[binutils-gdb] gdb/arm: Only stack S16..S31 when FPU registers are secure

[Yvan Roux <yroux@sourceware.org>]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=69b46464badb01340a88d0ee57cdef0b7fdf545e

commit 69b46464badb01340a88d0ee57cdef0b7fdf545e
Author: Yvan Roux <yvan.roux@foss.st.com>
Date:   Wed Jun 29 14:01:45 2022 +0200

    gdb/arm: Only stack S16..S31 when FPU registers are secure
    
    The FPCCR.TS bit is used to identify if FPU registers are considered
    non-secure or secure.  If they are secure, then callee saved registers
    (S16 to S31) are stacked on exception entry or otherwise skipped.
    
    Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
    Signed-off-by: Yvan Roux <yvan.roux@foss.st.com>

Diff:
---
 gdb/arch/arm.h | 9 +++++++++
 gdb/arm-tdep.c | 9 ++++++++-
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h
index 4ad329f6f1f..36757493406 100644
--- a/gdb/arch/arm.h
+++ b/gdb/arch/arm.h
@@ -109,6 +109,15 @@ enum arm_m_profile_type {
    ARM_M_TYPE_INVALID
 };
 
+/* System control registers accessible through an addresses.  */
+enum system_register_address : CORE_ADDR
+{
+  /* M-profile Floating-Point Context Control Register address, defined in
+     ARMv7-M (Section B3.2.2) and ARMv8-M (Section D1.2.99) reference
+     manuals.  */
+  FPCCR = 0xe000ef34
+};
+
 /* Instruction condition field values.  */
 #define INST_EQ		0x0
 #define INST_NE		0x1
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index e36bde9b3da..3a1b52c2380 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -3573,6 +3573,13 @@ arm_m_exception_cache (struct frame_info *this_frame)
     {
       int i;
       int fpu_regs_stack_offset;
+      ULONGEST fpccr;
+
+      /* Read FPCCR register.  */
+      gdb_assert (safe_read_memory_unsigned_integer (FPCCR,
+                                                     ARM_INT_REGISTER_SIZE,
+                                                     byte_order, &fpccr));
+      bool fpccr_ts = bit (fpccr,26);
 
       /* This code does not take into account the lazy stacking, see "Lazy
 	 context save of FP state", in B1.5.7, also ARM AN298, supported
@@ -3592,7 +3599,7 @@ arm_m_exception_cache (struct frame_info *this_frame)
       cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x60);
       fpu_regs_stack_offset += 4;
 
-      if (tdep->have_sec_ext && !default_callee_register_stacking)
+      if (tdep->have_sec_ext && !default_callee_register_stacking && fpccr_ts)
 	{
 	  /* Handle floating-point callee saved registers.  */
 	  fpu_regs_stack_offset = unwound_sp + sp_r0_offset + 0x68;