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From: Andrew Burgess <>
Subject: [binutils-gdb] sim/riscv: fix multiply instructions on simulator
Date: Tue, 11 Oct 2022 11:38:44 +0000 (GMT)	[thread overview]
Message-ID: <> (raw);h=c6422d7be70f14bf7140085f2fc7a592737f5df5

commit c6422d7be70f14bf7140085f2fc7a592737f5df5
Author: Tsukasa OI <>
Date:   Wed Aug 31 01:46:08 2022 +0000

    sim/riscv: fix multiply instructions on simulator
    After this commit:
      commit 0938b032daa52129b4215d8e0eedb6c9804f5280
      Date:   Wed Feb 2 10:06:15 2022 +0900
          RISC-V: Add 'Zmmul' extension in assembler.
    some instructions in the RISC-V simulator stopped working as a new
    instruction class 'INSN_CLASS_ZMMUL' was added, and some existing
    instructions were moved into this class.
    The simulator doesn't currently handle this instruction class, and so
    the instructions will now cause an illegal instruction trap.
    This commit adds support for INSN_CLASS_ZMMUL, and adds a test that
    ensures the affected instructions can be executed by the simulator.
    Reviewed-by: Palmer Dabbelt <>
    Reviewed-by: Andrew Burgess <>

 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 30d2f1e1c9a..0156f791d4b 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case INSN_CLASS_I:
       return execute_i (cpu, iw, op);
     case INSN_CLASS_M:
       return execute_m (cpu, iw, op);
       TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class);
diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s
new file mode 100644
index 00000000000..b80bd140e76
--- /dev/null
+++ b/sim/testsuite/riscv/m-ext.s
@@ -0,0 +1,18 @@
+# Check that the RV32M instructions run without any faults.
+# mach: riscv
+.include ""
+	start
+	.option	arch, +m
+	mul	x0, x1, x2
+	mulh	x0, x1, x2
+	mulhu	x0, x1, x2
+	mulhsu	x0, x1, x2
+	div	x0, x1, x2
+	divu	x0, x1, x2
+	rem	x0, x1, x2
+	remu	x0, x1, x2
+	pass

                 reply	other threads:[~2022-10-11 11:38 UTC|newest]

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