[binutils-gdb] sim: riscv: Fix confusion with c.jal vs. c.addiw

[binutils-gdb] sim: riscv: Fix confusion with c.jal vs. c.addiw

[Bernd Edlinger]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=d8e753b79118dc219855e21295b7d6e2f731e847

commit d8e753b79118dc219855e21295b7d6e2f731e847
Author: Bernd Edlinger <bernd.edlinger@hotmail.de>
Date:   Mon Apr 15 05:52:19 2024 +0200

    sim: riscv: Fix confusion with c.jal vs. c.addiw
    
    There was apparently a confusion which cpu model uses
    compressed JAL and which ADDIW.  Fixed that in execute_c,
    case MATCH_C_JAL | MATCH_C_ADDIW.
    
    Fixes 3224e32fb84f ("sim: riscv: Add support for compressed integer instructions")
    
    Approved-By: Andrew Burgess <aburgess@redhat.com>

Diff:
---
 sim/riscv/sim-main.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 1ccae450ad4..41973d9dd06 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1014,9 +1014,9 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
       break;
     case MATCH_C_JAL | MATCH_C_ADDIW:
-      /* JAL and ADDIW have the same mask but are only available on RV64 or
-	 RV32 respectively.  */
-      if (RISCV_XLEN (cpu) == 64)
+      /* JAL and ADDIW have the same mask but are only available on RV32 or
+	 RV64 respectively.  */
+      if (RISCV_XLEN (cpu) == 32)
 	{
 	  imm = EXTRACT_CJTYPE_IMM (iw);
 	  TRACE_INSN (cpu, "c.jal %" PRIxTW,
@@ -1025,7 +1025,7 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	  pc = riscv_cpu->pc + imm;
 	  TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
 	}
-      else if (RISCV_XLEN (cpu) == 32)
+      else if (RISCV_XLEN (cpu) == 64)
 	{
 	  imm = EXTRACT_CITYPE_IMM (iw);
 	  TRACE_INSN (cpu, "c.addiw %s, %s, %#" PRIxTW ";  // %s += %#" PRIxTW,