* [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types
@ 2022-01-01 20:55 Mike Frysinger
2022-01-01 20:55 ` [PATCH 02/17] sim: d10v: " Mike Frysinger
` (15 more replies)
0 siblings, 16 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.
Also migrate off the sim-specific unsignedXX types.
---
sim/cr16/cr16_sim.h | 29 +-
sim/cr16/interp.c | 34 +-
sim/cr16/simops.c | 1188 +++++++++++++++++++++----------------------
3 files changed, 621 insertions(+), 630 deletions(-)
diff --git a/sim/cr16/cr16_sim.h b/sim/cr16/cr16_sim.h
index 54df026d5f29..86ee50a24ae2 100644
--- a/sim/cr16/cr16_sim.h
+++ b/sim/cr16/cr16_sim.h
@@ -44,25 +44,16 @@ extern int cr16_debug;
#include "sim-config.h"
#include "sim-types.h"
-typedef unsigned8 uint8;
-typedef signed8 int8;
-typedef unsigned16 uint16;
-typedef signed16 int16;
-typedef unsigned32 uint32;
-typedef signed32 int32;
-typedef unsigned64 uint64;
-typedef signed64 int64;
-
/* FIXME: CR16 defines */
-typedef uint16 reg_t;
-typedef uint32 creg_t;
+typedef uint16_t reg_t;
+typedef uint32_t creg_t;
struct simops
{
char mnemonic[12];
- uint32 size;
- uint32 mask;
- uint32 opcode;
+ uint32_t size;
+ uint32_t mask;
+ uint32_t opcode;
int format;
char fname[12];
void (*func)(SIM_DESC, SIM_CPU *);
@@ -205,7 +196,7 @@ struct _state
#define GPR32(N) \
(N < 12) ? \
- ((((uint16) State.regs[(N) + 1]) << 16) | (uint16) State.regs[(N)]) \
+ ((((uint16_t) State.regs[(N) + 1]) << 16) | (uint16_t) State.regs[(N)]) \
: GPR (N)
#define SET_GPR32(N,VAL) do { \
@@ -232,7 +223,7 @@ struct _state
/* trace data */
struct {
- uint16 psw;
+ uint16_t psw;
} trace;
int pc_changed;
@@ -247,8 +238,8 @@ struct _state
extern struct _state State;
-extern uint32 OP[4];
-extern uint32 sign_flag;
+extern uint32_t OP[4];
+extern uint32_t sign_flag;
extern struct simops Simops[];
enum
@@ -394,7 +385,7 @@ enum
/* Yes, this is as whacked as it looks. The sim currently reads little endian
for 16 bits, but then merge them like big endian to get 32 bits. */
-static inline uint32 get_longword (SIM_CPU *cpu, address_word addr)
+static inline uint32_t get_longword (SIM_CPU *cpu, address_word addr)
{
return (RW (addr) << 16) | RW (addr + 2);
}
diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c
index 5ba752fd260a..47fb64781bfd 100644
--- a/sim/cr16/interp.c
+++ b/sim/cr16/interp.c
@@ -42,19 +42,19 @@ struct _state State;
int cr16_debug;
-uint32 OP[4];
-uint32 sign_flag;
+uint32_t OP[4];
+uint32_t sign_flag;
-static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint64 ins, int size);
-static void get_operands (operand_desc *s, uint64 mcode, int isize, int nops);
+static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint64_t ins, int size);
+static void get_operands (operand_desc *s, uint64_t mcode, int isize, int nops);
#define MAX_HASH 16
struct hash_entry
{
struct hash_entry *next;
- uint32 opcode;
- uint32 mask;
+ uint32_t opcode;
+ uint32_t mask;
int format;
int size;
struct simops *ops;
@@ -77,9 +77,9 @@ hash(unsigned long long insn, int format)
INLINE static struct hash_entry *
-lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint64 ins, int size)
+lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint64_t ins, int size)
{
- uint32 mask;
+ uint32_t mask;
struct hash_entry *h;
h = &hash_table[hash(ins,1)];
@@ -108,10 +108,10 @@ lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint64 ins, int size)
}
INLINE static void
-get_operands (operand_desc *s, uint64 ins, int isize, int nops)
+get_operands (operand_desc *s, uint64_t ins, int isize, int nops)
{
- uint32 i, opn = 0, start_bit = 0, op_type = 0;
- int32 op_size = 0, mask = 0;
+ uint32_t i, opn = 0, start_bit = 0, op_type = 0;
+ int32_t op_size = 0, mask = 0;
if (isize == 1) /* Trunkcate the extra 16 bits of INS. */
ins = ins >> 16;
@@ -328,7 +328,7 @@ get_operands (operand_desc *s, uint64 ins, int isize, int nops)
}
static int
-do_run (SIM_DESC sd, SIM_CPU *cpu, uint64 mcode)
+do_run (SIM_DESC sd, SIM_CPU *cpu, uint64_t mcode)
{
struct hash_entry *h;
@@ -579,8 +579,8 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb,
static void
step_once (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 curr_ins_size = 0;
- uint64 mcode = RLW (PC);
+ uint32_t curr_ins_size = 0;
+ uint64_t mcode = RLW (PC);
State.pc_changed = 0;
@@ -689,10 +689,10 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
return SIM_RC_OK;
}
-static uint32
+static uint32_t
cr16_extract_unsigned_integer (unsigned char *addr, int len)
{
- uint32 retval;
+ uint32_t retval;
unsigned char * p;
unsigned char * startaddr = (unsigned char *)addr;
unsigned char * endaddr = startaddr + len;
@@ -706,7 +706,7 @@ cr16_extract_unsigned_integer (unsigned char *addr, int len)
}
static void
-cr16_store_unsigned_integer (unsigned char *addr, int len, uint32 val)
+cr16_store_unsigned_integer (unsigned char *addr, int len, uint32_t val)
{
unsigned char *p;
unsigned char *startaddr = addr;
diff --git a/sim/cr16/simops.c b/sim/cr16/simops.c
index f668aca80fcc..d58c0c933953 100644
--- a/sim/cr16/simops.c
+++ b/sim/cr16/simops.c
@@ -362,7 +362,7 @@ trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_type
break;
case OP_MEMREF2:
- sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
+ sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]);
p += strlen (p);
comma = ",";
break;
@@ -398,39 +398,39 @@ trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_type
case OP_REG:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16) GPR (OP[i]));
+ (uint16_t) GPR (OP[i]));
break;
case OP_REGP:
- tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
+ tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1)));
sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
break;
case OP_PROC_REG:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16) CREG (OP[i]));
+ (uint16_t) CREG (OP[i]));
break;
case OP_CONSTANT16:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)OP[i]);
+ (uint16_t)OP[i]);
break;
case OP_CONSTANT4:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)SEXT4(OP[i]));
+ (uint16_t)SEXT4(OP[i]));
break;
case OP_CONSTANT3:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)SEXT3(OP[i]));
+ (uint16_t)SEXT3(OP[i]));
break;
case OP_MEMREF2:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)OP[i]);
+ (uint16_t)OP[i]);
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)GPR (OP[i + 1]));
+ (uint16_t)GPR (OP[i + 1]));
i++;
break;
}
@@ -459,7 +459,7 @@ do_trace_output_finish (SIM_DESC sd)
#if 0
static void
-trace_output_40 (SIM_DESC sd, uint64 val)
+trace_output_40 (SIM_DESC sd, uint64_t val)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
@@ -475,7 +475,7 @@ trace_output_40 (SIM_DESC sd, uint64 val)
#endif
static void
-trace_output_32 (SIM_DESC sd, uint32 val)
+trace_output_32 (SIM_DESC sd, uint32_t val)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
@@ -489,7 +489,7 @@ trace_output_32 (SIM_DESC sd, uint32 val)
}
static void
-trace_output_16 (SIM_DESC sd, uint16 val)
+trace_output_16 (SIM_DESC sd, uint16_t val)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
@@ -537,9 +537,9 @@ trace_output_flag (SIM_DESC sd)
void
OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp;
- uint8 a = OP[0] & 0xff;
- uint16 b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint16_t b = (GPR (OP[1])) & 0xff;
trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
tmp = (a + b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -550,8 +550,8 @@ OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
+ uint16_t tmp;
+ uint8_t a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = (a + b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -562,9 +562,9 @@ OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (GPR (OP[0])) & 0xff;
- uint8 b = (GPR (OP[1])) & 0xff;
- uint16 tmp = (a + b) & 0xff;
+ uint8_t a = (GPR (OP[0])) & 0xff;
+ uint8_t b = (GPR (OP[1])) & 0xff;
+ uint16_t tmp = (a + b) & 0xff;
trace_input ("addub", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
trace_output_16 (sd, tmp);
@@ -574,9 +574,9 @@ OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b);
+ uint16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b);
trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
@@ -586,9 +586,9 @@ OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b);
+ uint16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b);
trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
@@ -598,9 +598,9 @@ OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b);
+ uint16_t a = GPR (OP[0]);
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b);
trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
@@ -610,9 +610,9 @@ OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0];
- uint8 b = (GPR (OP[1]) & 0xff);
- uint16 tmp = (a + b) & 0xff;
+ uint8_t a = OP[0];
+ uint8_t b = (GPR (OP[1]) & 0xff);
+ uint16_t tmp = (a + b) & 0xff;
trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
@@ -624,9 +624,9 @@ OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint8 b = (GPR (OP[1]) & 0xff);
- uint16 tmp = (a + b) & 0xff;
+ uint8_t a = (OP[0]) & 0xff;
+ uint8_t b = (GPR (OP[1]) & 0xff);
+ uint16_t tmp = (a + b) & 0xff;
trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
@@ -638,9 +638,9 @@ OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (GPR (OP[0]) & 0xff);
- uint8 b = (GPR (OP[1]) & 0xff);
- uint16 tmp = (a + b) & 0xff;
+ uint8_t a = (GPR (OP[0]) & 0xff);
+ uint8_t b = (GPR (OP[1]) & 0xff);
+ uint16_t tmp = (a + b) & 0xff;
trace_input ("addb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
@@ -652,8 +652,8 @@ OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = OP[0];
- uint16 tmp, b = GPR (OP[1]);
+ int16_t a = OP[0];
+ uint16_t tmp, b = GPR (OP[1]);
tmp = (a + b);
trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
@@ -666,8 +666,8 @@ OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = OP[0];
- uint16 tmp, b = GPR (OP[1]);
+ int16_t a = OP[0];
+ uint16_t tmp, b = GPR (OP[1]);
tmp = (a + b);
trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
@@ -680,7 +680,7 @@ OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
+ uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("addw", OP_REG, OP_REG, OP_VOID);
tmp = (a + b);
SET_GPR (OP[1], tmp);
@@ -693,7 +693,7 @@ OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
tmp = (a + b + PSR_C) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -706,9 +706,9 @@ OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int8 a = OP[0] & 0xff;
- uint8 b = (GPR (OP[1])) & 0xff;
- uint8 tmp = (a + b + PSR_C) & 0xff;
+ int8_t a = OP[0] & 0xff;
+ uint8_t b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp = (a + b + PSR_C) & 0xff;
trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
@@ -720,9 +720,9 @@ OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (GPR (OP[0])) & 0xff;
- uint8 b = (GPR (OP[1])) & 0xff;
- uint8 tmp = (a + b + PSR_C) & 0xff;
+ uint8_t a = (GPR (OP[0])) & 0xff;
+ uint8_t b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp = (a + b + PSR_C) & 0xff;
trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
@@ -734,9 +734,9 @@ OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b + PSR_C);
+ uint16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b + PSR_C);
trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
@@ -748,9 +748,9 @@ OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b + PSR_C);
+ int16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b + PSR_C);
trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
@@ -762,9 +762,9 @@ OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[1]);
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b + PSR_C);
+ uint16_t a = GPR (OP[1]);
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b + PSR_C);
trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
@@ -776,9 +776,9 @@ OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = (OP[0]);
- uint32 b = GPR32 (OP[1]);
- uint32 tmp = (a + b);
+ int16_t a = (OP[0]);
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp = (a + b);
trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFFFFFF);
@@ -790,9 +790,9 @@ OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 a = (SEXT16(OP[0]));
- uint32 b = GPR32 (OP[1]);
- uint32 tmp = (a + b);
+ int32_t a = (SEXT16(OP[0]));
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp = (a + b);
trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFFFFFF);
@@ -804,9 +804,9 @@ OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 b = GPR32 (OP[1]);
- uint32 tmp = (a + b);
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp = (a + b);
trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
@@ -818,9 +818,9 @@ OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = OP[0];
- uint32 b = GPR32 (OP[1]);
- uint32 tmp;
+ uint32_t a = OP[0];
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp;
trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
tmp = (a + b);
SET_GPR32 (OP[1], tmp);
@@ -833,9 +833,9 @@ OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 a = OP[0];
- uint32 b = GPR32 (OP[1]);
- uint32 tmp;
+ int32_t a = OP[0];
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp;
trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
tmp = (a + b);
SET_GPR32 (OP[1], tmp);
@@ -848,7 +848,7 @@ OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -859,7 +859,7 @@ OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -870,7 +870,7 @@ OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("andb", OP_REG, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -881,7 +881,7 @@ OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = OP[0], b = GPR (OP[1]);
+ uint16_t tmp, a = OP[0], b = GPR (OP[1]);
trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], tmp);
@@ -892,7 +892,7 @@ OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = OP[0], b = GPR (OP[1]);
+ uint16_t tmp, a = OP[0], b = GPR (OP[1]);
trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], tmp);
@@ -903,7 +903,7 @@ OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
+ uint16_t tmp, a = GPR (OP[0]), b = GPR (OP[1]);
trace_input ("andw", OP_REG, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], tmp);
@@ -914,7 +914,7 @@ OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
+ uint32_t tmp, a = OP[0], b = GPR32 (OP[1]);
trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
tmp = a & b;
SET_GPR32 (OP[1], tmp);
@@ -925,7 +925,7 @@ OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
+ uint32_t tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
tmp = a & b;
SET_GPR32 (OP[1], tmp);
@@ -936,7 +936,7 @@ OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
+ uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR32 (OP[1], tmp);
@@ -947,7 +947,7 @@ OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
+ uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
tmp = a | b;
SET_GPR32 (OP[1], tmp);
@@ -958,7 +958,7 @@ OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
+ uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR32 (OP[1], tmp);
@@ -969,7 +969,7 @@ OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
+ uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
tmp = a ^ b;
SET_GPR32 (OP[1], tmp);
@@ -981,7 +981,7 @@ OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0, cc = cond_stat (OP[0]);
+ uint32_t tmp = 0, cc = cond_stat (OP[0]);
trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
if (cc)
{
@@ -1008,7 +1008,7 @@ OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0, cc = cond_stat (OP[0]);
+ uint32_t tmp = 0, cc = cond_stat (OP[0]);
trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
if (cc)
{
@@ -1035,7 +1035,7 @@ OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0, cc = cond_stat (OP[0]);
+ uint32_t tmp = 0, cc = cond_stat (OP[0]);
trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
if (cc)
{
@@ -1062,7 +1062,7 @@ OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
SET_GPR32 (14, tmp);
@@ -1090,7 +1090,7 @@ OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
SET_GPR32 (OP[0], tmp);
@@ -1116,7 +1116,7 @@ OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
tmp = GPR32 (OP[1]);
@@ -1140,7 +1140,7 @@ OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
tmp = GPR32 (OP[0]);
@@ -1164,8 +1164,8 @@ OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint8 a = (GPR (OP[0]) & 0xFF);
+ uint32_t addr;
+ uint8_t a = (GPR (OP[0]) & 0xFF);
trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a == 0)
@@ -1185,8 +1185,8 @@ OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint8 a = (GPR (OP[0]) & 0xFF);
+ uint32_t addr;
+ uint8_t a = (GPR (OP[0]) & 0xFF);
trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a != 0)
@@ -1206,8 +1206,8 @@ OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = GPR (OP[0]);
+ uint32_t addr;
+ uint16_t a = GPR (OP[0]);
trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a == 0)
@@ -1227,8 +1227,8 @@ OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = GPR (OP[0]);
+ uint32_t addr;
+ uint16_t a = GPR (OP[0]);
trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a != 0)
@@ -1249,7 +1249,7 @@ OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_Z) == 1)
{
@@ -1263,7 +1263,7 @@ OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_Z) == 0)
{
@@ -1277,7 +1277,7 @@ OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_C) == 1)
{
@@ -1291,7 +1291,7 @@ OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_C) == 0)
{
@@ -1305,7 +1305,7 @@ OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_L) == 1)
{
@@ -1319,7 +1319,7 @@ OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_L) == 0)
{
@@ -1333,7 +1333,7 @@ OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_N) == 1)
{
@@ -1347,7 +1347,7 @@ OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_N) == 0)
{
@@ -1362,7 +1362,7 @@ OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_F) == 1)
{
@@ -1376,7 +1376,7 @@ OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_F) == 0)
{
@@ -1390,7 +1390,7 @@ OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 0) & ((PSR_L) == 0))
{
@@ -1404,7 +1404,7 @@ OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 1) | ((PSR_L) == 1))
{
@@ -1418,7 +1418,7 @@ OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 0) & ((PSR_N) == 0))
{
@@ -1432,7 +1432,7 @@ OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 1) | ((PSR_N) == 1))
{
@@ -1446,7 +1446,7 @@ OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
@@ -1457,7 +1457,7 @@ OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
@@ -1637,8 +1637,8 @@ OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1651,8 +1651,8 @@ OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1665,8 +1665,8 @@ OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1679,8 +1679,8 @@ OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1693,8 +1693,8 @@ OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
void
OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1707,8 +1707,8 @@ OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1721,8 +1721,8 @@ OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1736,8 +1736,8 @@ OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1750,8 +1750,8 @@ OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1765,8 +1765,8 @@ OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1779,8 +1779,8 @@ OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1793,8 +1793,8 @@ OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = (OP[0]), tmp;
+ uint32_t addr;
+ uint16_t a = (OP[0]), tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
@@ -1814,8 +1814,8 @@ OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1828,8 +1828,8 @@ OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
void
OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1843,8 +1843,8 @@ OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1857,8 +1857,8 @@ OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1872,8 +1872,8 @@ OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1886,8 +1886,8 @@ OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1900,8 +1900,8 @@ OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1914,8 +1914,8 @@ OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1928,8 +1928,8 @@ OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1942,8 +1942,8 @@ OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1956,8 +1956,8 @@ OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
void
OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1971,8 +1971,8 @@ OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -1985,8 +1985,8 @@ OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2000,8 +2000,8 @@ OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2015,8 +2015,8 @@ OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2030,8 +2030,8 @@ OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2044,8 +2044,8 @@ OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2058,8 +2058,8 @@ OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = (OP[0]), tmp;
+ uint32_t addr;
+ uint16_t a = (OP[0]), tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
@@ -2078,8 +2078,8 @@ OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2092,8 +2092,8 @@ OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
void
OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2106,8 +2106,8 @@ OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2120,8 +2120,8 @@ OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2134,8 +2134,8 @@ OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2148,8 +2148,8 @@ OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2163,8 +2163,8 @@ OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2175,8 +2175,8 @@ OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2187,8 +2187,8 @@ OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2199,8 +2199,8 @@ OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2211,8 +2211,8 @@ OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
void
OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2223,8 +2223,8 @@ OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2235,8 +2235,8 @@ OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2247,8 +2247,8 @@ OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2259,8 +2259,8 @@ OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2272,8 +2272,8 @@ OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2284,8 +2284,8 @@ OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2297,8 +2297,8 @@ OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = (OP[0]), tmp;
+ uint32_t addr;
+ uint16_t a = (OP[0]), tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
@@ -2315,8 +2315,8 @@ OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2327,8 +2327,8 @@ OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
void
OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2339,8 +2339,8 @@ OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2351,8 +2351,8 @@ OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2363,8 +2363,8 @@ OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2376,8 +2376,8 @@ OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
@@ -2389,8 +2389,8 @@ OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = (GPR (OP[1]));
+ uint16_t a = OP[0];
+ uint16_t b = (GPR (OP[1]));
trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
SET_PSR_F (b & (1 << a));
trace_output_16 (sd, b);
@@ -2400,8 +2400,8 @@ OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b = (GPR (OP[1]));
+ uint16_t a = GPR (OP[0]);
+ uint16_t b = (GPR (OP[1]));
trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
SET_PSR_F (b & (1 << a));
trace_output_16 (sd, b);
@@ -2412,11 +2412,11 @@ OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xFF;
- uint8 b = (GPR (OP[1])) & 0xFF;
+ uint8_t a = (OP[0]) & 0xFF;
+ uint8_t b = (GPR (OP[1])) & 0xFF;
trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int8)a > (int8)b);
+ SET_PSR_N ((int8_t)a > (int8_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
@@ -2425,11 +2425,11 @@ OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xFF;
- uint8 b = (GPR (OP[1])) & 0xFF;
+ uint8_t a = (OP[0]) & 0xFF;
+ uint8_t b = (GPR (OP[1])) & 0xFF;
trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int8)a > (int8)b);
+ SET_PSR_N ((int8_t)a > (int8_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
@@ -2438,11 +2438,11 @@ OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (GPR (OP[0])) & 0xFF;
- uint8 b = (GPR (OP[1])) & 0xFF;
+ uint8_t a = (GPR (OP[0])) & 0xFF;
+ uint8_t b = (GPR (OP[1])) & 0xFF;
trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int8)a > (int8)b);
+ SET_PSR_N ((int8_t)a > (int8_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
@@ -2451,11 +2451,11 @@ OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint16 b = GPR (OP[1]);
+ uint16_t a = (OP[0]);
+ uint16_t b = GPR (OP[1]);
trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int16)a > (int16)b);
+ SET_PSR_N ((int16_t)a > (int16_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
@@ -2464,11 +2464,11 @@ OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint16 b = GPR (OP[1]);
+ uint16_t a = (OP[0]);
+ uint16_t b = GPR (OP[1]);
trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int16)a > (int16)b);
+ SET_PSR_N ((int16_t)a > (int16_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
@@ -2477,11 +2477,11 @@ OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]) ;
- uint16 b = GPR (OP[1]) ;
+ uint16_t a = GPR (OP[0]) ;
+ uint16_t b = GPR (OP[1]) ;
trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int16)a > (int16)b);
+ SET_PSR_N ((int16_t)a > (int16_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
@@ -2490,11 +2490,11 @@ OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = (OP[0]);
- uint32 b = GPR32 (OP[1]);
+ uint32_t a = (OP[0]);
+ uint32_t b = GPR32 (OP[1]);
trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int32)a > (int32)b);
+ SET_PSR_N ((int32_t)a > (int32_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
@@ -2503,11 +2503,11 @@ OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = (SEXT16(OP[0]));
- uint32 b = GPR32 (OP[1]);
+ uint32_t a = (SEXT16(OP[0]));
+ uint32_t b = GPR32 (OP[1]);
trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int32)a > (int32)b);
+ SET_PSR_N ((int32_t)a > (int32_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
@@ -2516,11 +2516,11 @@ OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]) ;
- uint32 b = GPR32 (OP[1]) ;
+ uint32_t a = GPR32 (OP[0]) ;
+ uint32_t b = GPR32 (OP[1]) ;
trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int32)a > (int32)b);
+ SET_PSR_N ((int32_t)a > (int32_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
@@ -2529,11 +2529,11 @@ OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = (OP[0]);
- uint32 b = GPR32 (OP[1]);
+ uint32_t a = (OP[0]);
+ uint32_t b = GPR32 (OP[1]);
trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int32)a > (int32)b);
+ SET_PSR_N ((int32_t)a > (int32_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
@@ -2543,8 +2543,8 @@ OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp = OP[0] & 0xFF;
- uint16 a = (GPR (OP[1])) & 0xFF00;
+ uint8_t tmp = OP[0] & 0xFF;
+ uint16_t a = (GPR (OP[1])) & 0xFF00;
trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
SET_GPR (OP[1], (a | tmp));
trace_output_16 (sd, tmp);
@@ -2554,8 +2554,8 @@ OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp = OP[0] & 0xFF;
- uint16 a = (GPR (OP[1])) & 0xFF00;
+ uint8_t tmp = OP[0] & 0xFF;
+ uint16_t a = (GPR (OP[1])) & 0xFF00;
trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (a | tmp));
trace_output_16 (sd, tmp);
@@ -2565,8 +2565,8 @@ OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp = (GPR (OP[0])) & 0xFF;
- uint16 a = (GPR (OP[1])) & 0xFF00;
+ uint8_t tmp = (GPR (OP[0])) & 0xFF;
+ uint16_t a = (GPR (OP[1])) & 0xFF00;
trace_input ("movb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (a | tmp));
trace_output_16 (sd, tmp);
@@ -2576,7 +2576,7 @@ OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = OP[0];
+ uint16_t tmp = OP[0];
trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp & 0xffff));
trace_output_16 (sd, tmp);
@@ -2586,7 +2586,7 @@ OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp = OP[0];
+ int16_t tmp = OP[0];
trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp & 0xffff));
trace_output_16 (sd, tmp);
@@ -2596,8 +2596,8 @@ OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = GPR (OP[0]);
- uint32 a = GPR32 (OP[1]);
+ uint16_t tmp = GPR (OP[0]);
+ uint32_t a = GPR32 (OP[1]);
trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
a = (a & 0xffff0000) | tmp;
SET_GPR32 (OP[1], a);
@@ -2608,7 +2608,7 @@ OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp = (GPR (OP[0])) & 0xFF;
+ uint8_t tmp = (GPR (OP[0])) & 0xFF;
trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
trace_output_16 (sd, tmp);
@@ -2618,7 +2618,7 @@ OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp = (GPR (OP[0])) & 0xFF;
+ uint8_t tmp = (GPR (OP[0])) & 0xFF;
trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
@@ -2628,7 +2628,7 @@ OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = GPR (OP[0]);
+ uint16_t tmp = GPR (OP[0]);
trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], SEXT16(tmp));
trace_output_16 (sd, tmp);
@@ -2638,7 +2638,7 @@ OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = GPR (OP[0]);
+ uint16_t tmp = GPR (OP[0]);
trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
trace_output_16 (sd, tmp);
@@ -2648,7 +2648,7 @@ OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp = OP[0];
+ int32_t tmp = OP[0];
trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
@@ -2658,7 +2658,7 @@ OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp = SEXT16(OP[0]);
+ int32_t tmp = SEXT16(OP[0]);
trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
@@ -2668,7 +2668,7 @@ OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = GPR32 (OP[0]);
+ uint32_t tmp = GPR32 (OP[0]);
trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
@@ -2678,7 +2678,7 @@ OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = OP[0];
+ uint32_t tmp = OP[0];
trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
@@ -2688,7 +2688,7 @@ OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp = OP[0];
+ int32_t tmp = OP[0];
trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
@@ -2698,8 +2698,8 @@ OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr = GPR (0);
- uint16 count = OP[0], reg = 2, tmp;
+ uint32_t addr = GPR (0);
+ uint16_t count = OP[0], reg = 2, tmp;
trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
if ((addr & 1))
{
@@ -2726,8 +2726,8 @@ OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
void
OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr = GPR32 (0);
- uint16 count = OP[0], reg = 2, tmp;
+ uint32_t addr = GPR32 (0);
+ uint16_t count = OP[0], reg = 2, tmp;
trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
if ((addr & 1))
{
@@ -2762,8 +2762,8 @@ OP_88_8 (SIM_DESC sd, SIM_CPU *cpu)
* with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
* by the core to 16M-64k to 16M. */
- uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
- uint32 addr = OP[0];
+ uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
+ uint32_t addr = OP[0];
trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
if (addr > 0xEFFFF) addr |= 0xF00000;
tmp = (RB (addr));
@@ -2779,8 +2779,8 @@ OP_127_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = abs24
* REGR = [ADDR]. */
- uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
- uint32 addr = OP[0];
+ uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
+ uint32_t addr = OP[0];
trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[1], (a | tmp));
@@ -2795,8 +2795,8 @@ OP_45_7 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rindex + zext24(disp20)
* REGR = [ADDR]. */
- uint32 addr;
- uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr;
+ uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
if (OP[0] == 0)
@@ -2817,8 +2817,8 @@ OP_B_4 (SIM_DESC sd, SIM_CPU *cpu)
/* loadb DIPS4(REGP) REG
* ADDR = RPBASE + zext24(DISP4)
* REG = [ADDR]. */
- uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = (GPR32 (OP[1])) + OP[0];
+ uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = (GPR32 (OP[1])) + OP[0];
trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
@@ -2833,8 +2833,8 @@ OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rpbasex + Rindex
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
+ uint32_t addr;
+ uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
addr = (GPR32 (OP[2])) + OP[1];
@@ -2857,8 +2857,8 @@ OP_219_A (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rpbasex + Rindex + zext24(disp14)
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
+ uint32_t addr;
+ uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
addr = (GPR32 (OP[2])) + OP[1];
@@ -2882,8 +2882,8 @@ OP_184_14 (SIM_DESC sd, SIM_CPU *cpu)
* zext24(Rbase) + zext24(dispe20)
* REG = [ADDR] */
- uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = OP[0] + (GPR (OP[1]));
+ uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = OP[0] + (GPR (OP[1]));
trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
@@ -2898,8 +2898,8 @@ OP_124_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = zext24(Rbase) + zext24(disp20)
* REG = [ADDR] */
- uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = OP[0] + (GPR (OP[1]));
+ uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = OP[0] + (GPR (OP[1]));
trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
@@ -2914,8 +2914,8 @@ OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPbase + zext24(disp16)
* REGR = [ADDR] */
- uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = (GPR32 (OP[1])) + OP[0];
+ uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = (GPR32 (OP[1])) + OP[0];
trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
@@ -2929,8 +2929,8 @@ OP_125_14 (SIM_DESC sd, SIM_CPU *cpu)
/* loadb disp20(REGP) REG
* ADDR = RPbase + zext24(disp20)
* REGR = [ADDR] */
- uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = (GPR32 (OP[1])) + OP[0];
+ uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = (GPR32 (OP[1])) + OP[0];
trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
@@ -2945,8 +2945,8 @@ OP_185_14 (SIM_DESC sd, SIM_CPU *cpu)
/* loadb -disp20(REGP) REG
* ADDR = RPbase + zext24(-disp20)
* REGR = [ADDR] */
- uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = (GPR32 (OP[1])) + OP[1];
+ uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = (GPR32 (OP[1])) + OP[1];
trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
@@ -2961,8 +2961,8 @@ OP_126_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPbasex + Rindex + zext24(disp20)
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
+ uint32_t addr;
+ uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
addr = (GPR32 (OP[2])) + OP[1];
@@ -2990,8 +2990,8 @@ OP_89_8 (SIM_DESC sd, SIM_CPU *cpu)
* with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
* by the core to 16M-64k to 16M. */
- uint16 tmp;
- uint32 addr = OP[0];
+ uint16_t tmp;
+ uint32_t addr = OP[0];
trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
if (addr > 0xEFFFF) addr |= 0xF00000;
tmp = (RW (addr));
@@ -3007,8 +3007,8 @@ OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu)
/* loadw ABS24, REG
* ADDR = abs24
* REGR = [ADDR] */
- uint16 tmp;
- uint32 addr = OP[0];
+ uint16_t tmp;
+ uint32_t addr = OP[0];
trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
tmp = (RW (addr));
SET_GPR (OP[1], tmp);
@@ -3023,8 +3023,8 @@ OP_47_7 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rindex + zext24(disp20)
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp;
+ uint32_t addr;
+ uint16_t tmp;
trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
if (OP[0] == 0)
@@ -3045,8 +3045,8 @@ OP_9_4 (SIM_DESC sd, SIM_CPU *cpu)
/* loadw DIPS4(REGP) REGP
* ADDR = RPBASE + zext24(DISP4)
* REGP = [ADDR]. */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
addr = (GPR32 (OP[1])) + OP[0];
tmp = (RW (addr));
@@ -3070,8 +3070,8 @@ OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rpbasex + Rindex
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp;
+ uint32_t addr;
+ uint16_t tmp;
trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
addr = (GPR32 (OP[2])) + OP[1];
@@ -3095,8 +3095,8 @@ OP_21B_A (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rpbasex + Rindex + zext24(disp14)
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp;
+ uint32_t addr;
+ uint16_t tmp;
trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
addr = (GPR32 (OP[2])) + OP[1];
@@ -3117,8 +3117,8 @@ OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu)
/* loadw dispe20(REG) REGP
* REGP = [DISPE20+[REG]] */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
addr = OP[0] + (GPR (OP[1]));
tmp = (RW (addr));
@@ -3142,8 +3142,8 @@ OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = zext24(Rbase) + zext24(disp20)
* REGP = [ADDR] */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
addr = OP[0] + (GPR (OP[1]));
tmp = (RW (addr));
@@ -3165,8 +3165,8 @@ OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu)
/* loadw disp16(REGP) REGP
* ADDR = RPbase + zext24(disp16)
* REGP = [ADDR] */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
addr = (GPR32 (OP[1])) + OP[0];
tmp = (RW (addr));
@@ -3188,8 +3188,8 @@ OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu)
/* loadw disp20(REGP) REGP
* ADDR = RPbase + zext24(disp20)
* REGP = [ADDR] */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
addr = (GPR32 (OP[1])) + OP[0];
tmp = (RW (addr));
@@ -3212,8 +3212,8 @@ OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPbase + zext24(-disp20)
* REGR = [ADDR] */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
addr = (GPR32 (OP[1])) + OP[0];
tmp = (RB (addr));
@@ -3237,8 +3237,8 @@ OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPbasex + Rindex + zext24(disp20)
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp;
+ uint32_t addr;
+ uint16_t tmp;
trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
if (OP[0] == 0)
@@ -3264,7 +3264,7 @@ OP_87_8 (SIM_DESC sd, SIM_CPU *cpu)
* with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
* by the core to 16M-64k to 16M. */
- uint32 addr, tmp;
+ uint32_t addr, tmp;
addr = OP[0];
trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
if (addr > 0xEFFFF) addr |= 0xF00000;
@@ -3282,8 +3282,8 @@ OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = abs24
* REGP = [ADDR] */
- uint32 addr = OP[0];
- uint32 tmp;
+ uint32_t addr = OP[0];
+ uint32_t tmp;
trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3300,7 +3300,7 @@ OP_46_7 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rindex + zext24(disp20)
* REGP = [ADDR] */
- uint32 addr, tmp;
+ uint32_t addr, tmp;
trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
if (OP[0] == 0)
@@ -3323,7 +3323,7 @@ OP_A_4 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rpbase + zext24(disp4)
* REGP = [ADDR] */
- uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
+ uint32_t tmp, addr = (GPR32 (OP[1])) + OP[0];
trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3340,7 +3340,7 @@ OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rpbasex + Rindex
* REGP = [ADDR] */
- uint32 addr, tmp;
+ uint32_t addr, tmp;
trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
if (OP[0] == 0)
@@ -3363,7 +3363,7 @@ OP_21A_A (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rpbasex + Rindex + zext24(disp14)
* REGR = [ADDR] */
- uint32 addr, tmp;
+ uint32_t addr, tmp;
trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
if (OP[0] == 0)
@@ -3386,7 +3386,7 @@ OP_188_14 (SIM_DESC sd, SIM_CPU *cpu)
* zext24(Rbase) + zext24(dispe20)
* REG = [ADDR] */
- uint32 tmp, addr = OP[0] + (GPR (OP[1]));
+ uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3403,7 +3403,7 @@ OP_128_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = zext24(Rbase) + zext24(disp20)
* REG = [ADDR] */
- uint32 tmp, addr = OP[0] + (GPR (OP[1]));
+ uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3418,7 +3418,7 @@ OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu)
/* loadd disp16(REGP) REGP
* ADDR = RPbase + zext24(disp16)
* REGR = [ADDR] */
- uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
+ uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3434,7 +3434,7 @@ OP_129_14 (SIM_DESC sd, SIM_CPU *cpu)
/* loadd disp20(REGP) REGP
* ADDR = RPbase + zext24(disp20)
* REGP = [ADDR] */
- uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
+ uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3450,7 +3450,7 @@ OP_189_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPbase + zext24(-disp20)
* REGP = [ADDR] */
- uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
+ uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
@@ -3466,7 +3466,7 @@ OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPbasex + Rindex + zext24(disp20)
* REGP = [ADDR] */
- uint32 addr, tmp;
+ uint32_t addr, tmp;
trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
if (OP[0] == 0)
@@ -3493,8 +3493,8 @@ OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu)
* with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
* by the core to 16M-64k to 16M. */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = OP[1];
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = OP[1];
trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3508,8 +3508,8 @@ OP_137_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = abs24
* [ADDR] = REGR. */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = OP[1];
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = OP[1];
trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3523,8 +3523,8 @@ OP_65_7 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rindex + zext24(disp20)
* [ADDR] = REGR */
- uint32 addr;
- uint8 a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr;
+ uint8_t a = ((GPR (OP[0])) & 0xff);
trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
@@ -3544,8 +3544,8 @@ OP_F_4 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPBASE + zext24(DISP4)
* [ADDR] = REG. */
- uint16 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3559,8 +3559,8 @@ OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rpbasex + Rindex
* [ADDR] = REGR */
- uint32 addr;
- uint8 a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr;
+ uint8_t a = ((GPR (OP[0])) & 0xff);
trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
if (OP[1] == 0)
@@ -3580,8 +3580,8 @@ OP_319_A (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = Rpbasex + Rindex + zext24(disp14)
* [ADDR] = REGR */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3595,8 +3595,8 @@ OP_194_14 (SIM_DESC sd, SIM_CPU *cpu)
* zext24(Rbase) + zext24(dispe20)
* [ADDR] = REG */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = OP[1] + (GPR (OP[2]));
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = OP[1] + (GPR (OP[2]));
trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3610,8 +3610,8 @@ OP_134_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = zext24(Rbase) + zext24(disp20)
* [ADDR] = REG */
- uint8 a = (GPR (OP[0]) & 0xff);
- uint32 addr = OP[1] + (GPR (OP[2]));
+ uint8_t a = (GPR (OP[0]) & 0xff);
+ uint32_t addr = OP[1] + (GPR (OP[2]));
trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3625,8 +3625,8 @@ OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPbase + zext24(disp16)
* [ADDR] = REGP */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3640,8 +3640,8 @@ OP_135_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPbase + zext24(disp20)
* [ADDR] = REGP */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3655,8 +3655,8 @@ OP_195_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPbase + zext24(-disp20)
* [ADDR] = REGP */
- uint8 a = (GPR (OP[0]) & 0xff);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (GPR (OP[0]) & 0xff);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3670,8 +3670,8 @@ OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
* ADDR = RPbasex + Rindex + zext24(disp20)
* [ADDR] = REGP */
- uint8 a = (GPR (OP[0])) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (GPR (OP[0])) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3682,8 +3682,8 @@ OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = OP[1];
trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3693,8 +3693,8 @@ OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = OP[1];
trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3704,8 +3704,8 @@ OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint8 a = (OP[0]) & 0xff;
+ uint32_t addr;
+ uint8_t a = (OP[0]) & 0xff;
trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
@@ -3721,8 +3721,8 @@ OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3732,8 +3732,8 @@ OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
void
OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3743,8 +3743,8 @@ OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3754,8 +3754,8 @@ OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3765,8 +3765,8 @@ OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3776,8 +3776,8 @@ OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
@@ -3788,8 +3788,8 @@ OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint32 addr = OP[1];
+ uint16_t a = GPR (OP[0]);
+ uint32_t addr = OP[1];
trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3799,8 +3799,8 @@ OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint32 addr = OP[1];
+ uint16_t a = GPR (OP[0]);
+ uint32_t addr = OP[1];
trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3810,8 +3810,8 @@ OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = GPR (OP[0]);
+ uint32_t addr;
+ uint16_t a = GPR (OP[0]);
trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
@@ -3828,8 +3828,8 @@ OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3839,8 +3839,8 @@ OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = GPR (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3850,8 +3850,8 @@ OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = GPR (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3861,8 +3861,8 @@ OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
void
OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3872,8 +3872,8 @@ OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3883,8 +3883,8 @@ OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3894,8 +3894,8 @@ OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3905,8 +3905,8 @@ OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3916,8 +3916,8 @@ OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3928,8 +3928,8 @@ OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1];
trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3939,8 +3939,8 @@ OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1];
trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3950,8 +3950,8 @@ OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = OP[0];
+ uint32_t addr;
+ uint16_t a = OP[0];
trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
@@ -3967,8 +3967,8 @@ OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3978,8 +3978,8 @@ OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
void
OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -3989,8 +3989,8 @@ OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -4000,8 +4000,8 @@ OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -4012,8 +4012,8 @@ OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -4023,8 +4023,8 @@ OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
@@ -4035,8 +4035,8 @@ OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = OP[1];
trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4046,8 +4046,8 @@ OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = OP[1];
trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4057,7 +4057,7 @@ OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr, a = GPR32 (OP[0]);
+ uint32_t addr, a = GPR32 (OP[0]);
trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
@@ -4073,8 +4073,8 @@ OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4084,8 +4084,8 @@ OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4095,8 +4095,8 @@ OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4106,8 +4106,8 @@ OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
void
OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4117,8 +4117,8 @@ OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4128,8 +4128,8 @@ OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4139,8 +4139,8 @@ OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4150,8 +4150,8 @@ OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4161,8 +4161,8 @@ OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
@@ -4172,8 +4172,8 @@ OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int16 src1, src2;
+ int32_t tmp;
+ int16_t src1, src2;
trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
src1 = GPR (OP[0]);
src2 = GPR (OP[1]);
@@ -4187,8 +4187,8 @@ OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
- uint16 src1, src2;
+ uint32_t tmp;
+ uint16_t src1, src2;
trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
src1 = GPR (OP[0]);
src2 = GPR (OP[1]);
@@ -4202,8 +4202,8 @@ OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int16 src1, src2;
+ int32_t tmp;
+ int16_t src1, src2;
trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
src1 = GPR (OP[0]);
src2 = GPR (OP[1]);
@@ -4218,9 +4218,9 @@ OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
- int8 a = (OP[0]) & 0xff;
- int8 b = (GPR (OP[1])) & 0xff;
+ int16_t tmp;
+ int8_t a = (OP[0]) & 0xff;
+ int8_t b = (GPR (OP[1])) & 0xff;
trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
tmp = (a * b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -4231,8 +4231,8 @@ OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
- int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ int16_t tmp;
+ int8_t a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = (a * b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -4244,8 +4244,8 @@ OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
- int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+ int16_t tmp;
+ int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
tmp = (a * b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -4257,9 +4257,9 @@ OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- uint16 a = OP[0];
- int16 b = (GPR (OP[1]));
+ int32_t tmp;
+ uint16_t a = OP[0];
+ int16_t b = (GPR (OP[1]));
trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
tmp = (a * b) & 0xffff;
SET_GPR (OP[1], tmp);
@@ -4270,8 +4270,8 @@ OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int16 a = OP[0], b = (GPR (OP[1]));
+ int32_t tmp;
+ int16_t a = OP[0], b = (GPR (OP[1]));
trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = (a * b) & 0xffff;
SET_GPR (OP[1], tmp);
@@ -4283,8 +4283,8 @@ OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
+ int32_t tmp;
+ int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
tmp = (a * b) & 0xffff;
SET_GPR (OP[1], tmp);
@@ -4296,8 +4296,8 @@ OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
- int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+ int16_t tmp;
+ int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
tmp = a * b;
SET_GPR (OP[1], tmp);
@@ -4308,8 +4308,8 @@ OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
+ int32_t tmp;
+ int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
tmp = a * b;
SET_GPR32 (OP[1], tmp);
@@ -4320,8 +4320,8 @@ OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
- uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
+ uint32_t tmp;
+ uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
tmp = a * b;
SET_GPR32 (OP[1], tmp);
@@ -4354,7 +4354,7 @@ OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
@@ -4365,7 +4365,7 @@ OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
@@ -4376,7 +4376,7 @@ OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("orb", OP_REG, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
@@ -4387,7 +4387,7 @@ OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+ uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], tmp);
@@ -4399,7 +4399,7 @@ OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+ uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], tmp);
@@ -4410,7 +4410,7 @@ OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
+ uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("orw", OP_REG, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], tmp);
@@ -4422,8 +4422,8 @@ OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 tmp, b = (GPR (OP[1])) & 0xFF;
+ uint16_t a = OP[0];
+ uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
@@ -4442,8 +4442,8 @@ OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0])) & 0xff;
- uint16 tmp, b = (GPR (OP[1])) & 0xFF;
+ uint16_t a = (GPR (OP[0])) & 0xff;
+ uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
if (a & ((long)1 << 3))
{
@@ -4468,8 +4468,8 @@ OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, b = GPR (OP[1]);
- int16 a = GPR (OP[0]);
+ uint16_t tmp, b = GPR (OP[1]);
+ int16_t a = GPR (OP[0]);
trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
if (a & ((long)1 << 4))
{
@@ -4494,8 +4494,8 @@ OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, b = GPR (OP[1]);
- uint16 a = OP[0];
+ uint16_t tmp, b = GPR (OP[1]);
+ uint16_t a = OP[0];
trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
@@ -4513,8 +4513,8 @@ OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, b = GPR32 (OP[1]);
- uint16 a = OP[0];
+ uint32_t tmp, b = GPR32 (OP[1]);
+ uint16_t a = OP[0];
trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
@@ -4533,8 +4533,8 @@ OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, b = GPR32 (OP[1]);
- uint16 a = GPR (OP[0]);
+ uint32_t tmp, b = GPR32 (OP[1]);
+ uint16_t a = GPR (OP[0]);
trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
if (a & ((long)1 << 5))
{
@@ -4559,8 +4559,8 @@ OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- int8 tmp, b = (GPR (OP[1])) & 0xFF;
+ uint16_t a = OP[0];
+ int8_t tmp, b = (GPR (OP[1])) & 0xFF;
trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
@@ -4579,8 +4579,8 @@ OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- int8 tmp, b = (GPR (OP[1])) & 0xFF;
+ uint16_t a = OP[0];
+ int8_t tmp, b = (GPR (OP[1])) & 0xFF;
trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
@@ -4600,8 +4600,8 @@ OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = (GPR (OP[0]));
- int8 tmp, b = (GPR (OP[1])) & 0xFF;
+ int16_t a = (GPR (OP[0]));
+ int8_t tmp, b = (GPR (OP[1])) & 0xFF;
trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
if (a & ((long)1 << 3))
@@ -4629,8 +4629,8 @@ OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp, b = GPR (OP[1]);
- uint16 a = OP[0];
+ int16_t tmp, b = GPR (OP[1]);
+ uint16_t a = OP[0];
trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
@@ -4649,8 +4649,8 @@ OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp, b = GPR (OP[1]);
- uint16 a = OP[0];
+ int16_t tmp, b = GPR (OP[1]);
+ uint16_t a = OP[0];
trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
@@ -4668,8 +4668,8 @@ OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
- int16 a = GPR (OP[0]), b = GPR (OP[1]);
+ int16_t tmp;
+ int16_t a = GPR (OP[0]), b = GPR (OP[1]);
trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
if (a & ((long)1 << 4))
@@ -4695,8 +4695,8 @@ OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp,b = GPR32 (OP[1]);
- uint32 a = OP[0];
+ int32_t tmp,b = GPR32 (OP[1]);
+ uint32_t a = OP[0];
trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
@@ -4714,8 +4714,8 @@ OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int32 a = OP[0], b = GPR32 (OP[1]);
+ int32_t tmp;
+ int32_t a = OP[0], b = GPR32 (OP[1]);
trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
@@ -4733,8 +4733,8 @@ OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
+ int32_t tmp;
+ int32_t a = GPR32 (OP[0]), b = GPR32 (OP[1]);
trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
if (a & ((long)1 << 5))
@@ -4760,8 +4760,8 @@ OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr = GPR (1);
- uint16 count = OP[0], reg = 2;
+ uint32_t addr = GPR (1);
+ uint16_t count = OP[0], reg = 2;
trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
if ((addr & 1))
{
@@ -4788,8 +4788,8 @@ OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
void
OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr = GPR32 (6);
- uint16 count = OP[0], reg = 2;
+ uint32_t addr = GPR32 (6);
+ uint16_t count = OP[0], reg = 2;
trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
if ((addr & 1))
{
@@ -4814,9 +4814,9 @@ OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
void
OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0];
- uint8 b = (GPR (OP[1])) & 0xff;
- uint16 tmp = (~a + 1 + b) & 0xff;
+ uint8_t a = OP[0];
+ uint8_t b = (GPR (OP[1])) & 0xff;
+ uint16_t tmp = (~a + 1 + b) & 0xff;
trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4830,9 +4830,9 @@ OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xFF;
- uint8 b = (GPR (OP[1])) & 0xFF;
- uint16 tmp = (~a + 1 + b) & 0xFF;
+ uint8_t a = OP[0] & 0xFF;
+ uint8_t b = (GPR (OP[1])) & 0xFF;
+ uint16_t tmp = (~a + 1 + b) & 0xFF;
trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4846,9 +4846,9 @@ OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (GPR (OP[0])) & 0xFF;
- uint8 b = (GPR (OP[1])) & 0xFF;
- uint16 tmp = (~a + 1 + b) & 0xff;
+ uint8_t a = (GPR (OP[0])) & 0xFF;
+ uint8_t b = (GPR (OP[1])) & 0xFF;
+ uint16_t tmp = (~a + 1 + b) & 0xff;
trace_input ("subb", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4862,9 +4862,9 @@ OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp = (~a + 1 + b);
+ uint16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (~a + 1 + b);
trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4878,9 +4878,9 @@ OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint32 tmp = (~a + 1 + b);
+ uint16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint32_t tmp = (~a + 1 + b);
trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4894,9 +4894,9 @@ OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b = GPR (OP[1]);
- uint32 tmp = (~a + 1 + b);
+ uint16_t a = GPR (OP[0]);
+ uint16_t b = GPR (OP[1]);
+ uint32_t tmp = (~a + 1 + b);
trace_input ("subw", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4910,11 +4910,11 @@ OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0];
- uint8 b = (GPR (OP[1])) & 0xff;
- //uint16 tmp1 = a + 1;
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ uint8_t a = OP[0];
+ uint8_t b = (GPR (OP[1])) & 0xff;
+ //uint16_t tmp1 = a + 1;
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4928,11 +4928,11 @@ OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = (GPR (OP[1])) & 0xff;
- //uint16 tmp1 = a + 1;
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ uint16_t a = OP[0];
+ uint16_t b = (GPR (OP[1])) & 0xff;
+ //uint16_t tmp1 = a + 1;
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4946,10 +4946,10 @@ OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0])) & 0xff;
- uint16 b = (GPR (OP[1])) & 0xff;
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ uint16_t a = (GPR (OP[0])) & 0xff;
+ uint16_t b = (GPR (OP[1])) & 0xff;
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4963,9 +4963,9 @@ OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0], b = (GPR (OP[1]));
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ uint16_t a = OP[0], b = (GPR (OP[1]));
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4979,10 +4979,10 @@ OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ int16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -4996,9 +4996,9 @@ OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -5012,9 +5012,9 @@ OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 a = OP[0];
- uint32 b = GPR32 (OP[1]);
- uint32 tmp = (~a + 1 + b);
+ int32_t a = OP[0];
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp = (~a + 1 + b);
trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -5029,9 +5029,9 @@ OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 b = GPR32 (OP[1]);
- uint32 tmp = (~a + 1 + b);
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp = (~a + 1 + b);
trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -5047,8 +5047,8 @@ void
OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
{
host_callback *cb = STATE_CALLBACK (sd);
- uint32 tmp;
- uint16 a;
+ uint32_t tmp;
+ uint16_t a;
trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
switch (OP[0])
{
@@ -5056,7 +5056,7 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
#if (DEBUG & DEBUG_TRAP) == 0
{
#if 0
- uint16 vec = OP[0] + TRAP_VECTOR_START;
+ uint16_t vec = OP[0] + TRAP_VECTOR_START;
SET_BPC (PC + 1);
SET_BPSR (PSR);
SET_PSR (PSR & PSR_SM_BIT);
@@ -5097,7 +5097,7 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
case 8: /* new system call trap */
/* Trap 8 is used for simulating low-level I/O */
{
- unsigned32 result = 0;
+ uint32_t result = 0;
errno = 0;
/* Registers passed to trap 0. */
@@ -5284,7 +5284,7 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
buf = PARM1;
RETVAL (pipe (host_fd));
SW (buf, host_fd[0]);
- buf += sizeof(uint16);
+ buf += sizeof(uint16_t);
SW (buf, host_fd[1]);
trace_output_16 (sd, result);
}
@@ -5449,7 +5449,7 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
break;
}
}
- if ((uint16) result == (uint16) -1)
+ if ((uint16_t) result == (uint16_t) -1)
RETERR (cb->get_errno (cb));
else
RETERR (0);
@@ -5463,8 +5463,8 @@ OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
- uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
+ uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+ uint32_t tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
for (; i < a; ++i)
@@ -5512,8 +5512,8 @@ OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 sp_addr, tmp, is_regp = 0;
- uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+ uint32_t sp_addr, tmp, is_regp = 0;
+ uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
if (c == 1)
@@ -5570,7 +5570,7 @@ OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 sp_addr = (GPR32 (15)), tmp;
+ uint32_t sp_addr = (GPR32 (15)), tmp;
trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
tmp = (GPR32 (14));
SLW(sp_addr-4,tmp); /* Store RA address. */
@@ -5583,8 +5583,8 @@ OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
- uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
+ uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+ uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
for (; i < a; ++i)
@@ -5636,8 +5636,8 @@ OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
- uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
+ uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+ uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;
trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
for (; i < a; ++i)
@@ -5690,8 +5690,8 @@ OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 sp_addr = GPR32 (15);
- uint32 tmp;
+ uint32_t sp_addr = GPR32 (15);
+ uint32_t tmp;
trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
tmp = RLW(sp_addr);
@@ -5705,7 +5705,7 @@ OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0], b = OP[1];
+ uint16_t a = OP[0], b = OP[1];
trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
OP_5_9 (sd, cpu);
JMP(((GPR32(14)) << 1) & 0xffffff);
@@ -5717,7 +5717,7 @@ OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0], b = OP[1];
+ uint16_t a = OP[0], b = OP[1];
trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
OP_2_8 (sd, cpu);
JMP(((GPR32(14)) << 1) & 0xffffff);
@@ -5729,7 +5729,7 @@ OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
OP_21E_10 (sd, cpu);
tmp = (((GPR32(14)) << 1) & 0xffffff);
@@ -5851,7 +5851,7 @@ OP_7_10 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -5862,7 +5862,7 @@ OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -5873,7 +5873,7 @@ OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
@@ -5884,7 +5884,7 @@ OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+ uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], tmp);
@@ -5895,7 +5895,7 @@ OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+ uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], tmp);
@@ -5906,7 +5906,7 @@ OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
+ uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], tmp);
@@ -5919,7 +5919,7 @@ OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
+ uint16_t a = GPR (OP[0]);
trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
SET_CREG (OP[1], a);
trace_output_16 (sd, a);
@@ -5929,7 +5929,7 @@ OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
+ uint32_t a = GPR32 (OP[0]);
trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
SET_CREG (OP[1], a);
trace_output_flag (sd);
@@ -5939,7 +5939,7 @@ OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = CREG (OP[0]);
+ uint16_t a = CREG (OP[0]);
trace_input ("spr", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], a);
trace_output_16 (sd, a);
@@ -5949,7 +5949,7 @@ OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = CREG (OP[0]);
+ uint32_t a = CREG (OP[0]);
trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], a);
trace_output_32 (sd, a);
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 02/17] sim: d10v: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 03/17] sim: m68hc11: " Mike Frysinger
` (14 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.
Also migrate off the sim-specific unsignedXX types.
---
sim/d10v/d10v_sim.h | 44 ++---
sim/d10v/endian.c | 32 ++--
sim/d10v/interp.c | 66 ++++----
sim/d10v/simops.c | 396 ++++++++++++++++++++++----------------------
4 files changed, 265 insertions(+), 273 deletions(-)
diff --git a/sim/d10v/d10v_sim.h b/sim/d10v/d10v_sim.h
index 1e1e84c76a82..7b354fd48414 100644
--- a/sim/d10v/d10v_sim.h
+++ b/sim/d10v/d10v_sim.h
@@ -24,16 +24,8 @@ extern int d10v_debug;
#include "sim-config.h"
#include "sim-types.h"
-typedef unsigned8 uint8;
-typedef unsigned16 uint16;
-typedef signed16 int16;
-typedef unsigned32 uint32;
-typedef signed32 int32;
-typedef unsigned64 uint64;
-typedef signed64 int64;
-
/* FIXME: D10V defines */
-typedef uint16 reg_t;
+typedef uint16_t reg_t;
struct simops
{
@@ -222,9 +214,9 @@ enum
struct d10v_memory
{
- uint8 *insn[IMEM_SEGMENTS];
- uint8 *data[DMEM_SEGMENTS];
- uint8 *unif[UMEM_SEGMENTS];
+ uint8_t *insn[IMEM_SEGMENTS];
+ uint8_t *data[DMEM_SEGMENTS];
+ uint8_t *unif[UMEM_SEGMENTS];
};
struct _state
@@ -233,8 +225,8 @@ struct _state
#define GPR(N) (State.regs[(N)] + 0)
#define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))
-#define GPR32(N) ((((uint32) State.regs[(N) + 0]) << 16) \
- | (uint16) State.regs[(N) + 1])
+#define GPR32(N) ((((uint32_t) State.regs[(N) + 0]) << 16) \
+ | (uint16_t) State.regs[(N) + 1])
#define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)
reg_t cregs[16]; /* control registers */
@@ -246,7 +238,7 @@ struct _state
#define HELD_SP(N) (State.sp[(N)] + 0)
#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
- int64 a[2]; /* accumulators */
+ int64_t a[2]; /* accumulators */
#define ACC(N) (State.a[(N)] + 0)
#define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)
@@ -256,10 +248,10 @@ struct _state
/* trace data */
struct {
- uint16 psw;
+ uint16_t psw;
} trace;
- uint8 exe;
+ uint8_t exe;
int pc_changed;
/* NOTE: everything below this line is not reset by
@@ -274,7 +266,7 @@ struct _state
extern struct _state State;
-extern uint16 OP[4];
+extern uint16_t OP[4];
extern struct simops Simops[];
enum
@@ -441,8 +433,8 @@ do \
} \
while (0)
-extern uint8 *dmem_addr (SIM_DESC, SIM_CPU *, uint16 offset);
-extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32);
+extern uint8_t *dmem_addr (SIM_DESC, SIM_CPU *, uint16_t offset);
+extern uint8_t *imem_addr (SIM_DESC, SIM_CPU *, uint32_t);
#define RB(x) (*(dmem_addr (sd, cpu, x)))
#define SB(addr,data) ( RB(addr) = (data & 0xff))
@@ -453,12 +445,12 @@ extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32);
#undef ENDIAN_INLINE
#else
-extern uint32 get_longword (uint8 *);
-extern uint16 get_word (uint8 *);
-extern int64 get_longlong (uint8 *);
-extern void write_word (uint8 *addr, uint16 data);
-extern void write_longword (uint8 *addr, uint32 data);
-extern void write_longlong (uint8 *addr, int64 data);
+extern uint32_t get_longword (uint8_t *);
+extern uint16_t get_word (uint8_t *);
+extern int64_t get_longlong (uint8_t *);
+extern void write_word (uint8_t *addr, uint16_t data);
+extern void write_longword (uint8_t *addr, uint32_t data);
+extern void write_longlong (uint8_t *addr, int64_t data);
#endif
#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data)
diff --git a/sim/d10v/endian.c b/sim/d10v/endian.c
index 70f63d8e5440..f3e1e46214f7 100644
--- a/sim/d10v/endian.c
+++ b/sim/d10v/endian.c
@@ -10,35 +10,35 @@
#define ENDIAN_INLINE
#endif
-ENDIAN_INLINE uint16
-get_word (uint8 *x)
+ENDIAN_INLINE uint16_t
+get_word (uint8_t *x)
{
- return ((uint16)x[0]<<8) + x[1];
+ return ((uint16_t)x[0]<<8) + x[1];
}
-ENDIAN_INLINE uint32
-get_longword (uint8 *x)
+ENDIAN_INLINE uint32_t
+get_longword (uint8_t *x)
{
- return ((uint32)x[0]<<24) + ((uint32)x[1]<<16) + ((uint32)x[2]<<8) + ((uint32)x[3]);
+ return ((uint32_t)x[0]<<24) + ((uint32_t)x[1]<<16) + ((uint32_t)x[2]<<8) + ((uint32_t)x[3]);
}
-ENDIAN_INLINE int64
-get_longlong (uint8 *x)
+ENDIAN_INLINE int64_t
+get_longlong (uint8_t *x)
{
- uint32 top = get_longword (x);
- uint32 bottom = get_longword (x+4);
- return (((int64)top)<<32) | (int64)bottom;
+ uint32_t top = get_longword (x);
+ uint32_t bottom = get_longword (x+4);
+ return (((int64_t)top)<<32) | (int64_t)bottom;
}
ENDIAN_INLINE void
-write_word (uint8 *addr, uint16 data)
+write_word (uint8_t *addr, uint16_t data)
{
addr[0] = (data >> 8) & 0xff;
addr[1] = data & 0xff;
}
ENDIAN_INLINE void
-write_longword (uint8 *addr, uint32 data)
+write_longword (uint8_t *addr, uint32_t data)
{
addr[0] = (data >> 24) & 0xff;
addr[1] = (data >> 16) & 0xff;
@@ -47,8 +47,8 @@ write_longword (uint8 *addr, uint32 data)
}
ENDIAN_INLINE void
-write_longlong (uint8 *addr, int64 data)
+write_longlong (uint8_t *addr, int64_t data)
{
- write_longword (addr, (uint32)(data >> 32));
- write_longword (addr+4, (uint32)data);
+ write_longword (addr, (uint32_t)(data >> 32));
+ write_longword (addr+4, (uint32_t)data);
}
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c
index 2a0cf6bc3a01..5716a10583ea 100644
--- a/sim/d10v/interp.c
+++ b/sim/d10v/interp.c
@@ -32,23 +32,23 @@ int old_segment_mapping;
unsigned long ins_type_counters[ (int)INS_MAX ];
-uint16 OP[4];
+uint16_t OP[4];
static long hash (long insn, int format);
-static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32 ins, int size);
-static void get_operands (struct simops *s, uint32 ins);
-static void do_long (SIM_DESC, SIM_CPU *, uint32 ins);
-static void do_2_short (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2, enum _leftright leftright);
-static void do_parallel (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2);
+static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32_t ins, int size);
+static void get_operands (struct simops *s, uint32_t ins);
+static void do_long (SIM_DESC, SIM_CPU *, uint32_t ins);
+static void do_2_short (SIM_DESC, SIM_CPU *, uint16_t ins1, uint16_t ins2, enum _leftright leftright);
+static void do_parallel (SIM_DESC, SIM_CPU *, uint16_t ins1, uint16_t ins2);
static char *add_commas (char *buf, int sizeof_buf, unsigned long value);
-static INLINE uint8 *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
+static INLINE uint8_t *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
#define MAX_HASH 63
struct hash_entry
{
struct hash_entry *next;
- uint32 opcode;
- uint32 mask;
+ uint32_t opcode;
+ uint32_t mask;
int size;
struct simops *ops;
};
@@ -65,7 +65,7 @@ hash (long insn, int format)
}
INLINE static struct hash_entry *
-lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32 ins, int size)
+lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32_t ins, int size)
{
struct hash_entry *h;
@@ -84,10 +84,10 @@ lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32 ins, int size)
}
INLINE static void
-get_operands (struct simops *s, uint32 ins)
+get_operands (struct simops *s, uint32_t ins)
{
int i, shift, bits, flags;
- uint32 mask;
+ uint32_t mask;
for (i=0; i < s->numops; i++)
{
shift = s->operands[3*i];
@@ -102,7 +102,7 @@ get_operands (struct simops *s, uint32 ins)
}
static void
-do_long (SIM_DESC sd, SIM_CPU *cpu, uint32 ins)
+do_long (SIM_DESC sd, SIM_CPU *cpu, uint32_t ins)
{
struct hash_entry *h;
#ifdef DEBUG
@@ -119,7 +119,7 @@ do_long (SIM_DESC sd, SIM_CPU *cpu, uint32 ins)
}
static void
-do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2, enum _leftright leftright)
+do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16_t ins1, uint16_t ins2, enum _leftright leftright)
{
struct hash_entry *h;
enum _ins_type first, second;
@@ -171,7 +171,7 @@ do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2, enum _leftright
}
static void
-do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2)
+do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16_t ins1, uint16_t ins2)
{
struct hash_entry *h1, *h2;
#ifdef DEBUG
@@ -293,7 +293,7 @@ enum
static void
set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value)
{
- uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ uint8_t *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ DMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
@@ -307,7 +307,7 @@ set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value)
static unsigned long
dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
{
- uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ uint8_t *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ DMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
@@ -315,7 +315,7 @@ dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
static void
set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value)
{
- uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ uint8_t *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ IMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
@@ -329,7 +329,7 @@ set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value)
static unsigned long
imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
{
- uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ uint8_t *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ IMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
@@ -597,11 +597,11 @@ sim_d10v_translate_addr (SIM_DESC sd,
is assumed that the client has already ensured that the access
isn't going to cross a segment boundary. */
-uint8 *
+uint8_t *
map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr)
{
- uint8 **memory;
- uint8 *raw;
+ uint8_t **memory;
+ uint8_t *raw;
unsigned offset;
int segment = ((phys_addr >> 24) & 0xff);
@@ -669,7 +669,7 @@ xfer_mem (SIM_DESC sd,
int size,
int write_p)
{
- uint8 *memory;
+ uint8_t *memory;
unsigned long phys;
int phys_size;
phys_size = sim_d10v_translate_addr (sd, NULL, virt, size, &phys, NULL,
@@ -866,16 +866,16 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
return sd;
}
-uint8 *
-dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16 offset)
+uint8_t *
+dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16_t offset)
{
unsigned long phys;
- uint8 *mem;
+ uint8_t *mem;
int phys_size;
/* Note: DMEM address range is 0..0x10000. Calling code can compute
things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
- is uint16 this is modulo'ed onto 0x0e5d. */
+ is uint16_t this is modulo'ed onto 0x0e5d. */
phys_size = sim_d10v_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL,
dmap_register);
@@ -896,11 +896,11 @@ dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16 offset)
return mem;
}
-uint8 *
-imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
+uint8_t *
+imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32_t offset)
{
unsigned long phys;
- uint8 *mem;
+ uint8_t *mem;
int phys_size = sim_d10v_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL,
imap_register);
if (phys_size == 0)
@@ -923,12 +923,12 @@ imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
static void
step_once (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 inst;
- uint8 *iaddr;
+ uint32_t inst;
+ uint8_t *iaddr;
/* TODO: Unindent this block. */
{
- iaddr = imem_addr (sd, cpu, (uint32)PC << 2);
+ iaddr = imem_addr (sd, cpu, (uint32_t)PC << 2);
inst = get_longword( iaddr );
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index 6e6bb0209dd4..9883b3f55281 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -319,7 +319,7 @@ trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_type
break;
case OP_MEMREF2:
- sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
+ sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]);
p += strlen (p);
comma = ",";
break;
@@ -400,22 +400,22 @@ trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_type
case OP_POSTINC:
case OP_PREDEC:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16) GPR (OP[i]));
+ (uint16_t) GPR (OP[i]));
break;
case OP_MEMREF3:
- sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16_t) OP[i]);
break;
case OP_DREG:
- tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
+ tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1)));
sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
break;
case OP_CR:
case OP_CR_REVERSE:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16) CREG (OP[i]));
+ (uint16_t) CREG (OP[i]));
break;
case OP_ACCUM:
@@ -427,22 +427,22 @@ trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_type
case OP_CONSTANT16:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)OP[i]);
+ (uint16_t)OP[i]);
break;
case OP_CONSTANT4:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)SEXT4(OP[i]));
+ (uint16_t)SEXT4(OP[i]));
break;
case OP_CONSTANT8:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)SEXT8(OP[i]));
+ (uint16_t)SEXT8(OP[i]));
break;
case OP_CONSTANT3:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)SEXT3(OP[i]));
+ (uint16_t)SEXT3(OP[i]));
break;
case OP_FLAG:
@@ -462,25 +462,25 @@ trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_type
case OP_MEMREF2:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)OP[i]);
+ (uint16_t)OP[i]);
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)GPR (OP[i + 1]));
+ (uint16_t)GPR (OP[i + 1]));
i++;
break;
case OP_R0:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16) GPR (0));
+ (uint16_t) GPR (0));
break;
case OP_R1:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16) GPR (1));
+ (uint16_t) GPR (1));
break;
case OP_R2:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16) GPR (2));
+ (uint16_t) GPR (2));
break;
}
@@ -508,7 +508,7 @@ do_trace_output_finish (SIM_DESC sd)
}
static void
-trace_output_40 (SIM_DESC sd, uint64 val)
+trace_output_40 (SIM_DESC sd, uint64_t val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
@@ -523,7 +523,7 @@ trace_output_40 (SIM_DESC sd, uint64 val)
}
static void
-trace_output_32 (SIM_DESC sd, uint32 val)
+trace_output_32 (SIM_DESC sd, uint32_t val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
@@ -537,7 +537,7 @@ trace_output_32 (SIM_DESC sd, uint32 val)
}
static void
-trace_output_16 (SIM_DESC sd, uint16 val)
+trace_output_16 (SIM_DESC sd, uint16_t val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
@@ -585,7 +585,7 @@ trace_output_flag (SIM_DESC sd)
void
OP_4607 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
SET_PSW_F1 (PSW_F0);
tmp = GPR(OP[0]);
@@ -604,7 +604,7 @@ OP_4607 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5607 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
SET_PSW_F1 (PSW_F0);
@@ -638,9 +638,9 @@ OP_5607 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_200 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b);
+ uint16_t a = GPR (OP[0]);
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b);
trace_input ("add", OP_REG, OP_REG, OP_VOID);
SET_PSW_C (a > tmp);
SET_GPR (OP[0], tmp);
@@ -651,7 +651,7 @@ OP_200 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1201 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
@@ -674,7 +674,7 @@ OP_1201 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1203 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
@@ -697,9 +697,9 @@ OP_1203 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1200 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
- uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
- uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
+ uint32_t tmp;
+ uint32_t a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
+ uint32_t b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
tmp = a + b;
SET_PSW_C (tmp < a);
@@ -712,9 +712,9 @@ OP_1200 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[1]);
- uint16 b = OP[2];
- uint16 tmp = (a + b);
+ uint16_t a = GPR (OP[1]);
+ uint16_t b = OP[2];
+ uint16_t tmp = (a + b);
trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
SET_PSW_C (tmp < a);
SET_GPR (OP[0], tmp);
@@ -725,7 +725,7 @@ OP_1000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_17000200 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
@@ -738,7 +738,7 @@ OP_17000200 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_17000202 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
@@ -751,7 +751,7 @@ OP_17000202 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_17001200 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
SET_PSW_F1 (PSW_F0);
trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
@@ -779,7 +779,7 @@ OP_17001200 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_17001202 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
SET_PSW_F1 (PSW_F0);
trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
@@ -807,9 +807,9 @@ OP_17001202 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_201 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b;
- uint16 tmp;
+ uint16_t a = GPR (OP[0]);
+ uint16_t b;
+ uint16_t tmp;
if (OP[1] == 0)
OP[1] = 16;
b = OP[1];
@@ -824,7 +824,7 @@ OP_201 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_C00 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
+ uint16_t tmp = GPR (OP[0]) & GPR (OP[1]);
trace_input ("and", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
@@ -834,7 +834,7 @@ OP_C00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = GPR (OP[1]) & OP[2];
+ uint16_t tmp = GPR (OP[1]) & OP[2];
trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
@@ -844,7 +844,7 @@ OP_6000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_C01 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
@@ -875,7 +875,7 @@ OP_24800000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A01 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
@@ -944,7 +944,7 @@ OP_25800000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_801 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
@@ -976,7 +976,7 @@ OP_600 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
- SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
+ SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)(GPR (OP[1]))) ? 1 : 0);
trace_output_flag (sd);
}
@@ -1036,7 +1036,7 @@ OP_601 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
SET_PSW_F1 (PSW_F0);
- SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
+ SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)SEXT4(OP[1])) ? 1 : 0);
trace_output_flag (sd);
}
@@ -1046,7 +1046,7 @@ OP_3000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
- SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
+ SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)(OP[1])) ? 1 : 0);
trace_output_flag (sd);
}
@@ -1074,7 +1074,7 @@ OP_23000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4E09 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 val;
+ uint8_t val;
trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
@@ -1096,7 +1096,7 @@ OP_4E09 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4E0F (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 val;
+ uint8_t val;
trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
@@ -1147,19 +1147,19 @@ OP_5F20 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_14002800 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 foo, tmp, tmpf;
- uint16 hi;
- uint16 lo;
+ uint16_t foo, tmp, tmpf;
+ uint16_t hi;
+ uint16_t lo;
trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
- tmp = (int16)foo - (int16)(GPR (OP[1]));
+ tmp = (int16_t)foo - (int16_t)(GPR (OP[1]));
tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
hi = ((tmpf == 1) ? tmp : foo);
lo = ((GPR (OP[0] + 1) << 1) | tmpf);
SET_GPR (OP[0] + 0, hi);
SET_GPR (OP[0] + 1, lo);
- trace_output_32 (sd, ((uint32) hi << 16) | lo);
+ trace_output_32 (sd, ((uint32_t) hi << 16) | lo);
}
/* exef0f */
@@ -1238,11 +1238,11 @@ OP_4E22 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_15002A00 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, foo;
+ uint32_t tmp, foo;
int i;
trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
- if (((int16)GPR (OP[1])) >= 0)
+ if (((int16_t)GPR (OP[1])) >= 0)
tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
else
tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
@@ -1266,7 +1266,7 @@ OP_15002A00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_15002A02 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp, foo;
+ int64_t tmp, foo;
int i;
trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
@@ -1315,8 +1315,8 @@ OP_4C00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_30000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint16 addr = OP[1] + GPR (OP[2]);
+ uint16_t tmp;
+ uint16_t addr = OP[1] + GPR (OP[2]);
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
@@ -1332,8 +1332,8 @@ OP_30000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6401 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint16 addr = GPR (OP[1]);
+ uint16_t tmp;
+ uint16_t addr = GPR (OP[1]);
trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
if ((addr & 1))
{
@@ -1351,8 +1351,8 @@ OP_6401 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6001 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint16 addr = GPR (OP[1]);
+ uint16_t tmp;
+ uint16_t addr = GPR (OP[1]);
trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
@@ -1370,8 +1370,8 @@ OP_6001 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint16 addr = GPR (OP[1]);
+ uint16_t tmp;
+ uint16_t addr = GPR (OP[1]);
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
@@ -1387,8 +1387,8 @@ OP_6000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_32010000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint16 addr = OP[1];
+ uint16_t tmp;
+ uint16_t addr = OP[1];
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
@@ -1404,8 +1404,8 @@ OP_32010000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_31000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- uint16 addr = OP[1] + GPR (OP[2]);
+ int32_t tmp;
+ uint16_t addr = OP[1] + GPR (OP[2]);
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
@@ -1421,8 +1421,8 @@ OP_31000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6601 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
- int32 tmp;
+ uint16_t addr = GPR (OP[1]);
+ int32_t tmp;
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
if ((addr & 1))
{
@@ -1440,8 +1440,8 @@ OP_6601 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6201 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- uint16 addr = GPR (OP[1]);
+ int32_t tmp;
+ uint16_t addr = GPR (OP[1]);
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
@@ -1459,8 +1459,8 @@ OP_6201 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6200 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
- int32 tmp;
+ uint16_t addr = GPR (OP[1]);
+ int32_t tmp;
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
@@ -1476,8 +1476,8 @@ OP_6200 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_33010000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- uint16 addr = OP[1];
+ int32_t tmp;
+ uint16_t addr = OP[1];
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
@@ -1493,7 +1493,7 @@ OP_33010000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_38000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
SET_GPR (OP[0], tmp);
@@ -1504,7 +1504,7 @@ OP_38000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_7000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
tmp = SEXT8 (RB (GPR (OP[1])));
SET_GPR (OP[0], tmp);
@@ -1515,7 +1515,7 @@ OP_7000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4001 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
tmp = SEXT4 (OP[1]);
SET_GPR (OP[0], tmp);
@@ -1526,7 +1526,7 @@ OP_4001 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_20000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
tmp = OP[1];
SET_GPR (OP[0], tmp);
@@ -1537,7 +1537,7 @@ OP_20000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_39000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
tmp = RB (OP[1] + GPR (OP[2]));
SET_GPR (OP[0], tmp);
@@ -1548,7 +1548,7 @@ OP_39000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_7200 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
tmp = RB (GPR (OP[1]));
SET_GPR (OP[0], tmp);
@@ -1559,10 +1559,10 @@ OP_7200 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2A00 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
+ tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
if (PSW_FX)
tmp = SEXT40( (tmp << 1) & MASK40);
@@ -1590,10 +1590,10 @@ OP_2A00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1A00 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
+ tmp = SEXT40 ((int16_t) GPR (OP[1]) * GPR (OP[2]));
if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
@@ -1605,13 +1605,13 @@ OP_1A00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3A00 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint64 tmp;
- uint32 src1;
- uint32 src2;
+ uint64_t tmp;
+ uint32_t src1;
+ uint32_t src2;
trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
- src1 = (uint16) GPR (OP[1]);
- src2 = (uint16) GPR (OP[2]);
+ src1 = (uint16_t) GPR (OP[1]);
+ src2 = (uint16_t) GPR (OP[2]);
tmp = src1 * src2;
if (PSW_FX)
tmp = (tmp << 1);
@@ -1624,10 +1624,10 @@ OP_3A00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2600 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("max", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
- if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
+ if ((int16_t) GPR (OP[1]) > (int16_t)GPR (OP[0]))
{
tmp = GPR (OP[1]);
SET_PSW_F0 (1);
@@ -1645,7 +1645,7 @@ OP_2600 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3600 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
SET_PSW_F1 (PSW_F0);
@@ -1668,7 +1668,7 @@ OP_3600 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3602 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F1 (PSW_F0);
if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
@@ -1690,10 +1690,10 @@ OP_3602 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2601 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("min", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
- if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
+ if ((int16_t)GPR (OP[1]) < (int16_t)GPR (OP[0]))
{
tmp = GPR (OP[1]);
SET_PSW_F0 (1);
@@ -1711,7 +1711,7 @@ OP_2601 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3601 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
SET_PSW_F1 (PSW_F0);
@@ -1734,7 +1734,7 @@ OP_3601 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3603 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F1 (PSW_F0);
if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
@@ -1755,10 +1755,10 @@ OP_3603 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2800 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
+ tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
@@ -1788,10 +1788,10 @@ OP_2800 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1800 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
+ tmp = SEXT40 ((int16_t)GPR (OP[1]) * GPR (OP[2]));
if (PSW_FX)
tmp = SEXT40( (tmp << 1) & MASK40);
tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
@@ -1803,13 +1803,13 @@ OP_1800 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3800 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint64 tmp;
- uint32 src1;
- uint32 src2;
+ uint64_t tmp;
+ uint32_t src1;
+ uint32_t src2;
trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
- src1 = (uint16) GPR (OP[1]);
- src2 = (uint16) GPR (OP[2]);
+ src1 = (uint16_t) GPR (OP[1]);
+ src2 = (uint16_t) GPR (OP[2]);
tmp = src1 * src2;
if (PSW_FX)
tmp = (tmp << 1);
@@ -1822,7 +1822,7 @@ OP_3800 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2E00 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mul", OP_REG, OP_REG, OP_VOID);
tmp = GPR (OP[0]) * GPR (OP[1]);
SET_GPR (OP[0], tmp);
@@ -1833,10 +1833,10 @@ OP_2E00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2C00 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
+ tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2])));
if (PSW_FX)
tmp = SEXT40 ((tmp << 1) & MASK40);
@@ -1853,10 +1853,10 @@ OP_2C00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1C00 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
+ tmp = SEXT40 ((int16_t)(GPR (OP[1])) * GPR (OP[2]));
if (PSW_FX)
tmp <<= 1;
@@ -1869,13 +1869,13 @@ OP_1C00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3C00 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint64 tmp;
- uint32 src1;
- uint32 src2;
+ uint64_t tmp;
+ uint32_t src1;
+ uint32_t src2;
trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- src1 = (uint16) GPR (OP[1]);
- src2 = (uint16) GPR (OP[2]);
+ src1 = (uint16_t) GPR (OP[1]);
+ src2 = (uint16_t) GPR (OP[2]);
tmp = src1 * src2;
if (PSW_FX)
tmp <<= 1;
@@ -1888,7 +1888,7 @@ OP_3C00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = GPR (OP[1]);
SET_GPR (OP[0], tmp);
@@ -1899,7 +1899,7 @@ OP_4000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
+ int32_t tmp;
trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
tmp = GPR32 (OP[1]);
SET_GPR32 (OP[0], tmp);
@@ -1910,7 +1910,7 @@ OP_5000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3E00 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
+ int32_t tmp;
trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_GPR32 (OP[0], tmp);
@@ -1921,7 +1921,7 @@ OP_3E00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3E01 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
SET_ACC (OP[1], tmp);
@@ -1932,7 +1932,7 @@ OP_3E01 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3E03 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_ACC (OP[0], tmp);
@@ -1943,7 +1943,7 @@ OP_3E03 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5400 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = SEXT8 (GPR (OP[1]) & 0xff);
SET_GPR (OP[0], tmp);
@@ -1954,7 +1954,7 @@ OP_5400 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4400 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
if (PSW_F0 == 0)
{
@@ -1970,7 +1970,7 @@ OP_4400 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4401 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
if (PSW_F0)
{
@@ -1986,7 +1986,7 @@ OP_4401 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1E04 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ((ACC (OP[1]) >> 32) & 0xff);
SET_GPR (OP[0], tmp);
@@ -1997,7 +1997,7 @@ OP_1E04 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1E00 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = (ACC (OP[1]) >> 16);
SET_GPR (OP[0], tmp);
@@ -2008,7 +2008,7 @@ OP_1E00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1E02 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_GPR (OP[0], tmp);
@@ -2019,7 +2019,7 @@ OP_1E02 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5200 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
tmp = CREG (OP[1]);
SET_GPR (OP[0], tmp);
@@ -2030,10 +2030,10 @@ OP_5200 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1E41 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
tmp = ((ACC (OP[1]) & MASK32)
- | ((int64)(GPR (OP[0]) & 0xff) << 32));
+ | ((int64_t)(GPR (OP[0]) & 0xff) << 32));
SET_ACC (OP[1], tmp);
trace_output_40 (sd, tmp);
}
@@ -2042,7 +2042,7 @@ OP_1E41 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1E01 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint64 tmp;
+ uint64_t tmp;
trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]) & 0xffff;
tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
@@ -2054,7 +2054,7 @@ OP_1E01 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1E21 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
SET_ACC (OP[1], tmp);
@@ -2065,7 +2065,7 @@ OP_1E21 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5600 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
tmp = GPR (OP[0]);
tmp = SET_CREG (OP[1], tmp);
@@ -2076,7 +2076,7 @@ OP_5600 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5401 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = (GPR (OP[1]) & 0xff);
SET_GPR (OP[0], tmp);
@@ -2087,7 +2087,7 @@ OP_5401 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4605 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
tmp = - GPR (OP[0]);
SET_GPR (OP[0], tmp);
@@ -2098,7 +2098,7 @@ OP_4605 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5605 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
tmp = -SEXT40(ACC (OP[0]));
@@ -2163,7 +2163,7 @@ OP_5E00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4603 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("not", OP_REG, OP_VOID, OP_VOID);
tmp = ~GPR (OP[0]);
SET_GPR (OP[0], tmp);
@@ -2174,7 +2174,7 @@ OP_4603 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_800 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("or", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) | GPR (OP[1]));
SET_GPR (OP[0], tmp);
@@ -2185,7 +2185,7 @@ OP_800 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
tmp = (GPR (OP[1]) | OP[2]);
SET_GPR (OP[0], tmp);
@@ -2196,7 +2196,7 @@ OP_4000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5201 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
int shift = SEXT3 (OP[2]);
trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
@@ -2238,7 +2238,7 @@ OP_5201 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4201 (SIM_DESC sd, SIM_CPU *cpu)
{
- signed64 tmp;
+ int64_t tmp;
int shift = SEXT3 (OP[2]);
trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
@@ -2335,7 +2335,7 @@ OP_5F40 (SIM_DESC sd, SIM_CPU *cpu)
/* sac */
void OP_5209 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
@@ -2368,7 +2368,7 @@ void OP_5209 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4209 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
@@ -2401,7 +2401,7 @@ OP_4209 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1223 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
@@ -2424,7 +2424,7 @@ OP_1223 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4611 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
tmp = ((PSW_F0 == 0) ? 1 : 0);
SET_GPR (OP[0], tmp);
@@ -2435,7 +2435,7 @@ OP_4611 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4613 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
tmp = ((PSW_F0 == 1) ? 1 : 0);
SET_GPR (OP[0], tmp);
@@ -2446,8 +2446,8 @@ OP_4613 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3220 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
- int16 reg;
+ int64_t tmp;
+ int16_t reg;
trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
@@ -2505,7 +2505,7 @@ OP_5FC0 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2200 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("sll", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
@@ -2516,7 +2516,7 @@ OP_2200 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3200 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
@@ -2545,7 +2545,7 @@ OP_3200 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2201 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) << OP[1]);
SET_GPR (OP[0], tmp);
@@ -2556,7 +2556,7 @@ OP_2201 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3201 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
if (OP[1] == 0)
OP[1] = 16;
@@ -2583,7 +2583,7 @@ OP_3201 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_460B (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
tmp = ((GPR (OP[0]) << 1) | PSW_F0);
SET_GPR (OP[0], tmp);
@@ -2594,9 +2594,9 @@ OP_460B (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2400 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("sra", OP_REG, OP_REG, OP_VOID);
- tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
+ tmp = (((int16_t)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
}
@@ -2608,7 +2608,7 @@ OP_3400 (SIM_DESC sd, SIM_CPU *cpu)
trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
{
- int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
+ int64_t tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
SET_ACC (OP[0], tmp);
trace_output_40 (sd, tmp);
}
@@ -2623,9 +2623,9 @@ OP_3400 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2401 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
- tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
+ tmp = (((int16_t)(GPR (OP[0]))) >> OP[1]);
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
}
@@ -2634,7 +2634,7 @@ OP_2401 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3401 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
if (OP[1] == 0)
OP[1] = 16;
@@ -2648,7 +2648,7 @@ OP_3401 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("srl", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
@@ -2662,7 +2662,7 @@ OP_3000 (SIM_DESC sd, SIM_CPU *cpu)
trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
{
- int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
+ int64_t tmp = ((uint64_t)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
SET_ACC (OP[0], tmp);
trace_output_40 (sd, tmp);
}
@@ -2678,7 +2678,7 @@ OP_3000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_2001 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) >> OP[1]);
SET_GPR (OP[0], tmp);
@@ -2689,12 +2689,12 @@ OP_2001 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_3001 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
if (OP[1] == 0)
OP[1] = 16;
trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
- tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
+ tmp = ((uint64_t)(ACC (OP[0]) & MASK40) >> OP[1]);
SET_ACC (OP[0], tmp);
trace_output_40 (sd, tmp);
}
@@ -2703,7 +2703,7 @@ OP_3001 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_4609 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
+ uint16_t tmp;
trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
tmp = PSW_F0 << 15;
tmp = ((GPR (OP[0]) >> 1) | tmp);
@@ -2715,7 +2715,7 @@ OP_4609 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_34000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = OP[1] + GPR (OP[2]);
+ uint16_t addr = OP[1] + GPR (OP[2]);
trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
@@ -2730,7 +2730,7 @@ OP_34000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6800 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
@@ -2746,7 +2746,7 @@ OP_6800 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6C1F (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]) - 2;
+ uint16_t addr = GPR (OP[1]) - 2;
trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
if (OP[1] != 15)
{
@@ -2767,7 +2767,7 @@ OP_6C1F (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6801 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
@@ -2783,7 +2783,7 @@ OP_6801 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6C01 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
if ( OP[1] == 15 )
{
@@ -2804,7 +2804,7 @@ OP_6C01 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_36010000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = OP[1];
+ uint16_t addr = OP[1];
trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
@@ -2819,7 +2819,7 @@ OP_36010000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_35000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[2])+ OP[1];
+ uint16_t addr = GPR (OP[2])+ OP[1];
trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
if ((addr & 1))
{
@@ -2835,7 +2835,7 @@ OP_35000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6A00 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
if ((addr & 1))
{
@@ -2851,7 +2851,7 @@ OP_6A00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6E1F (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]) - 4;
+ uint16_t addr = GPR (OP[1]) - 4;
trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
if ( OP[1] != 15 )
{
@@ -2873,7 +2873,7 @@ OP_6E1F (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6A01 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
if ((addr & 1))
{
@@ -2890,7 +2890,7 @@ OP_6A01 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_6E01 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = GPR (OP[1]);
+ uint16_t addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
if ( OP[1] == 15 )
{
@@ -2912,7 +2912,7 @@ OP_6E01 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_37010000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 addr = OP[1];
+ uint16_t addr = OP[1];
trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
if ((addr & 1))
{
@@ -2955,9 +2955,9 @@ OP_5FE0 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_0 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a - b);
+ uint16_t a = GPR (OP[0]);
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a - b);
trace_input ("sub", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
@@ -2970,7 +2970,7 @@ OP_0 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1001 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
@@ -2995,7 +2995,7 @@ OP_1001 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1003 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
@@ -3019,11 +3019,11 @@ OP_1003 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_1000 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a, b;
+ uint32_t tmp, a, b;
trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
- a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
- b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
+ a = (uint32_t)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
+ b = (uint32_t)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits */
tmp = a - b;
@@ -3036,7 +3036,7 @@ OP_1000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_17000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
@@ -3048,7 +3048,7 @@ OP_17000000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_17000002 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
@@ -3060,7 +3060,7 @@ OP_17000002 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_17001000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
SET_PSW_F1 (PSW_F0);
@@ -3087,7 +3087,7 @@ OP_17001000 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_17001002 (SIM_DESC sd, SIM_CPU *cpu)
{
- int64 tmp;
+ int64_t tmp;
trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
SET_PSW_F1 (PSW_F0);
@@ -3122,8 +3122,8 @@ OP_1 (SIM_DESC sd, SIM_CPU *cpu)
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
/* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
- tmp = ((unsigned)(unsigned16) GPR (OP[0])
- + (unsigned)(unsigned16) ( - OP[1]));
+ tmp = ((unsigned)(uint16_t) GPR (OP[0])
+ + (unsigned)(uint16_t) ( - OP[1]));
SET_PSW_C (tmp >= (1 << 16));
SET_GPR (OP[0], tmp);
trace_output_16 (sd, tmp);
@@ -3143,7 +3143,7 @@ OP_5F00 (SIM_DESC sd, SIM_CPU *cpu)
default:
#if (DEBUG & DEBUG_TRAP) == 0
{
- uint16 vec = OP[0] + TRAP_VECTOR_START;
+ uint16_t vec = OP[0] + TRAP_VECTOR_START;
SET_BPC (PC + 1);
SET_BPSW (PSW);
SET_PSW (PSW & PSW_SM_BIT);
@@ -3183,7 +3183,7 @@ OP_5F00 (SIM_DESC sd, SIM_CPU *cpu)
case 15: /* new system call trap */
/* Trap 15 is used for simulating low-level I/O */
{
- unsigned32 result = 0;
+ uint32_t result = 0;
errno = 0;
/* Registers passed to trap 0 */
@@ -3370,7 +3370,7 @@ OP_5F00 (SIM_DESC sd, SIM_CPU *cpu)
buf = PARM1;
RETVAL (pipe (host_fd));
SW (buf, host_fd[0]);
- buf += sizeof(uint16);
+ buf += sizeof(uint16_t);
SW (buf, host_fd[1]);
trace_output_16 (sd, result);
}
@@ -3506,7 +3506,7 @@ OP_5F00 (SIM_DESC sd, SIM_CPU *cpu)
default:
cb->error (cb, "Unknown syscall %d", FUNC);
}
- if ((uint16) result == (uint16) -1)
+ if ((uint16_t) result == (uint16_t) -1)
RETERR (cb->get_errno (cb));
else
RETERR (0);
@@ -3548,7 +3548,7 @@ OP_5F80 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_A00 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("xor", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) ^ GPR (OP[1]));
SET_GPR (OP[0], tmp);
@@ -3559,7 +3559,7 @@ OP_A00 (SIM_DESC sd, SIM_CPU *cpu)
void
OP_5000000 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
+ int16_t tmp;
trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
tmp = (GPR (OP[1]) ^ OP[2]);
SET_GPR (OP[0], tmp);
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 03/17] sim: m68hc11: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
2022-01-01 20:55 ` [PATCH 02/17] sim: d10v: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 04/17] sim: v850: " Mike Frysinger
` (13 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.
Also migrate off the sim-specific unsignedXX types.
---
sim/m68hc11/dv-m68hc11.c | 54 ++++++-------
sim/m68hc11/dv-m68hc11eepr.c | 24 +++---
sim/m68hc11/dv-m68hc11sio.c | 18 ++---
sim/m68hc11/dv-m68hc11spi.c | 18 ++---
sim/m68hc11/dv-m68hc11tim.c | 52 ++++++------
sim/m68hc11/dv-nvram.c | 2 +-
sim/m68hc11/emulos.c | 2 +-
sim/m68hc11/gencode.c | 34 ++++----
sim/m68hc11/interp.c | 4 +-
sim/m68hc11/interrupts.c | 22 +++---
sim/m68hc11/interrupts.h | 24 +++---
sim/m68hc11/m68hc11_sim.c | 136 ++++++++++++++++----------------
sim/m68hc11/sim-main.h | 148 +++++++++++++++++------------------
13 files changed, 265 insertions(+), 273 deletions(-)
diff --git a/sim/m68hc11/dv-m68hc11.c b/sim/m68hc11/dv-m68hc11.c
index ccfa0f1c631a..cdcc9f8eb918 100644
--- a/sim/m68hc11/dv-m68hc11.c
+++ b/sim/m68hc11/dv-m68hc11.c
@@ -122,14 +122,14 @@ static const OPTION m68hc11_options[] =
struct input_osc
{
- signed64 on_time;
- signed64 off_time;
- signed64 repeat;
+ int64_t on_time;
+ int64_t off_time;
+ int64_t repeat;
struct hw_event *event;
const char *name;
- uint8 mask;
- uint8 value;
- uint16 addr;
+ uint8_t mask;
+ uint8_t value;
+ uint16_t addr;
};
#define NR_PORT_A_OSC (4)
@@ -209,7 +209,7 @@ static hw_ioctl_method m68hc11_ioctl;
static hw_port_event_method m68hc11cpu_port_event;
static void make_oscillator (struct m68hc11cpu *controller,
- const char *id, uint16 addr, uint8 mask);
+ const char *id, uint16_t addr, uint8_t mask);
static struct input_osc *find_oscillator (struct m68hc11cpu *controller,
const char *id);
static void reset_oscillators (struct hw *me);
@@ -412,7 +412,7 @@ deliver_m68hc11cpu_interrupt (struct hw *me, void *data)
static void
make_oscillator (struct m68hc11cpu *controller, const char *name,
- uint16 addr, uint8 mask)
+ uint16_t addr, uint8_t mask)
{
struct input_osc *osc;
@@ -445,8 +445,8 @@ oscillator_handler (struct hw *me, void *data)
struct input_osc *osc = (struct input_osc*) data;
SIM_DESC sd;
sim_cpu *cpu;
- signed64 dt;
- uint8 val;
+ int64_t dt;
+ uint8_t val;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
@@ -593,10 +593,10 @@ static void
m68hc11_info (struct hw *me)
{
SIM_DESC sd;
- uint16 base = 0;
+ uint16_t base = 0;
sim_cpu *cpu;
struct m68hc11sio *controller;
- uint8 val;
+ uint8_t val;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
@@ -634,8 +634,8 @@ m68hc11_info (struct hw *me)
val = cpu->ios[M6811_INIT];
print_io_byte (sd, "INIT ", 0, val, base + M6811_INIT);
sim_io_printf (sd, "Ram = 0x%04x IO = 0x%04x\n",
- (((uint16) (val & 0xF0)) << 8),
- (((uint16) (val & 0x0F)) << 12));
+ (((uint16_t) (val & 0xF0)) << 8),
+ (((uint16_t) (val & 0x0F)) << 12));
cpu_info (sd, cpu);
@@ -662,7 +662,7 @@ m68hc11_ioctl (struct hw *me,
stops. */
int
m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
- double ton, double toff, signed64 repeat)
+ double ton, double toff, int64_t repeat)
{
sim_cpu *cpu;
struct input_osc *osc;
@@ -677,13 +677,13 @@ m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
/* Compute the ON time in cpu cycles. */
f = (double) (cpu->cpu_frequency) * ton;
- osc->on_time = (signed64) (f / 4.0);
+ osc->on_time = (int64_t) (f / 4.0);
if (osc->on_time < 1)
osc->on_time = 1;
/* Compute the OFF time in cpu cycles. */
f = (double) (cpu->cpu_frequency) * toff;
- osc->off_time = (signed64) (f / 4.0);
+ osc->off_time = (int64_t) (f / 4.0);
if (osc->off_time < 1)
osc->off_time = 1;
@@ -777,7 +777,7 @@ m68hc11_option_handler (SIM_DESC sd, sim_cpu *cpu,
case OPTION_OSC_INFO:
for (i = 0; i < controller->last_oscillator; i++)
{
- signed64 t;
+ int64_t t;
struct input_osc *osc;
osc = &controller->oscillators[i];
@@ -878,10 +878,10 @@ m68hc11cpu_io_read_buffer (struct hw *me,
void
m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
- unsigned addr, uint8 val)
+ unsigned addr, uint8_t val)
{
- uint8 mask;
- uint8 delta;
+ uint8_t mask;
+ uint8_t delta;
int check_interrupts = 0;
int i;
@@ -925,11 +925,11 @@ m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
/* Scan IC3, IC2 and IC1. Bit number is 3 - i. */
for (i = 0; i < 3; i++)
{
- uint8 mask = (1 << i);
+ uint8_t mask = (1 << i);
if (delta & mask)
{
- uint8 edge;
+ uint8_t edge;
int captured;
edge = cpu->ios[M6811_TCTL2];
@@ -983,7 +983,7 @@ m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
static void
m68hc11cpu_io_write (struct hw *me, sim_cpu *cpu,
- unsigned_word addr, uint8 val)
+ unsigned_word addr, uint8_t val)
{
switch (addr)
{
@@ -1022,7 +1022,7 @@ m68hc11cpu_io_write (struct hw *me, sim_cpu *cpu,
/* Change the RAM and I/O mapping. */
case M6811_INIT:
{
- uint8 old_bank = cpu->ios[M6811_INIT];
+ uint8_t old_bank = cpu->ios[M6811_INIT];
cpu->ios[M6811_INIT] = val;
@@ -1111,11 +1111,11 @@ m68hc11cpu_io_write_buffer (struct hw *me,
byte = 0;
while (nr_bytes)
{
- uint8 val;
+ uint8_t val;
if (base >= controller->attach_size)
break;
- val = *((uint8*) source);
+ val = *((uint8_t*) source);
m68hc11cpu_io_write (me, cpu, base, val);
source = (char*) source + 1;
base++;
diff --git a/sim/m68hc11/dv-m68hc11eepr.c b/sim/m68hc11/dv-m68hc11eepr.c
index 261e9cfb715e..6d620e474e89 100644
--- a/sim/m68hc11/dv-m68hc11eepr.c
+++ b/sim/m68hc11/dv-m68hc11eepr.c
@@ -112,11 +112,11 @@ struct m68hc11eepr
located at the end of the EEPROM (eeprom size + 1). It is not mapped
in memory but it's saved in the EEPROM file. */
unsigned long eeprom_wcycle;
- uint16 eeprom_waddr;
- uint8 eeprom_wbyte;
- uint8 eeprom_wmode;
+ uint16_t eeprom_waddr;
+ uint8_t eeprom_wbyte;
+ uint8_t eeprom_wmode;
- uint8* eeprom;
+ uint8_t* eeprom;
/* Minimum time in CPU cycles for programming the EEPROM. */
unsigned long eeprom_min_cycles;
@@ -339,10 +339,10 @@ static void
m68hc11eepr_info (struct hw *me)
{
SIM_DESC sd;
- uint16 base = 0;
+ uint16_t base = 0;
sim_cpu *cpu;
struct m68hc11eepr *controller;
- uint8 val;
+ uint8_t val;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
@@ -418,13 +418,13 @@ m68hc11eepr_io_read_buffer (struct hw *me,
{
case M6811_PPROG:
case M6811_CONFIG:
- *((uint8*) dest) = cpu->ios[base];
+ *((uint8_t*) dest) = cpu->ios[base];
break;
default:
hw_abort (me, "reading wrong register 0x%04x", base);
}
- dest = (uint8*) (dest) + 1;
+ dest = (uint8_t*) (dest) + 1;
base++;
nr_bytes--;
cnt++;
@@ -456,7 +456,7 @@ m68hc11eepr_io_write_buffer (struct hw *me,
SIM_DESC sd;
struct m68hc11eepr *controller;
sim_cpu *cpu;
- uint8 val;
+ uint8_t val;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
@@ -475,13 +475,13 @@ m68hc11eepr_io_write_buffer (struct hw *me,
if (nr_bytes != 1)
hw_abort (me, "Cannot write more than 1 byte to EEPROM device at a time");
- val = *((const uint8*) source);
+ val = *((const uint8_t*) source);
/* Write to the EEPROM control register. */
if (space == io_map && base == M6811_PPROG)
{
- uint8 wrong_bits;
- uint16 addr;
+ uint8_t wrong_bits;
+ uint16_t addr;
addr = base + cpu_get_io_base (cpu);
diff --git a/sim/m68hc11/dv-m68hc11sio.c b/sim/m68hc11/dv-m68hc11sio.c
index bdda1e9e1ea0..82629713b97e 100644
--- a/sim/m68hc11/dv-m68hc11sio.c
+++ b/sim/m68hc11/dv-m68hc11sio.c
@@ -184,7 +184,7 @@ m68hc11sio_port_event (struct hw *me,
SIM_DESC sd;
struct m68hc11sio *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
controller = hw_data (me);
sd = hw_system (me);
@@ -421,10 +421,10 @@ static void
m68hc11sio_info (struct hw *me)
{
SIM_DESC sd;
- uint16 base = 0;
+ uint16_t base = 0;
sim_cpu *cpu;
struct m68hc11sio *controller;
- uint8 val;
+ uint8_t val;
long clock_cycle;
sd = hw_system (me);
@@ -457,7 +457,7 @@ m68hc11sio_info (struct hw *me)
if (controller->tx_poll_event)
{
- signed64 t;
+ int64_t t;
int n;
t = hw_event_remain_time (me, controller->tx_poll_event);
@@ -469,7 +469,7 @@ m68hc11sio_info (struct hw *me)
}
if (controller->rx_poll_event)
{
- signed64 t;
+ int64_t t;
t = hw_event_remain_time (me, controller->rx_poll_event);
sim_io_printf (sd, " Receive finished in %s\n",
@@ -499,7 +499,7 @@ m68hc11sio_io_read_buffer (struct hw *me,
SIM_DESC sd;
struct m68hc11sio *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
@@ -530,7 +530,7 @@ m68hc11sio_io_read_buffer (struct hw *me,
default:
return 0;
}
- *((unsigned8*) dest) = val;
+ *((uint8_t*) dest) = val;
return 1;
}
@@ -544,7 +544,7 @@ m68hc11sio_io_write_buffer (struct hw *me,
SIM_DESC sd;
struct m68hc11sio *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
@@ -552,7 +552,7 @@ m68hc11sio_io_write_buffer (struct hw *me,
cpu = STATE_CPU (sd, 0);
controller = hw_data (me);
- val = *((const unsigned8*) source);
+ val = *((const uint8_t*) source);
switch (base)
{
case M6811_BAUD:
diff --git a/sim/m68hc11/dv-m68hc11spi.c b/sim/m68hc11/dv-m68hc11spi.c
index 5237218c23fb..d587411692a5 100644
--- a/sim/m68hc11/dv-m68hc11spi.c
+++ b/sim/m68hc11/dv-m68hc11spi.c
@@ -159,7 +159,7 @@ m68hc11spi_port_event (struct hw *me,
SIM_DESC sd;
struct m68hc11spi *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
controller = hw_data (me);
sd = hw_system (me);
@@ -193,7 +193,7 @@ m68hc11spi_port_event (struct hw *me,
static void
set_bit_port (struct hw *me, sim_cpu *cpu, int port, int mask, int value)
{
- uint8 val;
+ uint8_t val;
if (value)
val = cpu->ios[port] | mask;
@@ -330,10 +330,10 @@ static void
m68hc11spi_info (struct hw *me)
{
SIM_DESC sd;
- uint16 base = 0;
+ uint16_t base = 0;
sim_cpu *cpu;
struct m68hc11spi *controller;
- uint8 val;
+ uint8_t val;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
@@ -353,7 +353,7 @@ m68hc11spi_info (struct hw *me)
if (controller->spi_event)
{
- signed64 t;
+ int64_t t;
sim_io_printf (sd, " SPI has %d bits to send\n",
controller->tx_bit + 1);
@@ -388,7 +388,7 @@ m68hc11spi_io_read_buffer (struct hw *me,
SIM_DESC sd;
struct m68hc11spi *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
@@ -419,7 +419,7 @@ m68hc11spi_io_read_buffer (struct hw *me,
default:
return 0;
}
- *((unsigned8*) dest) = val;
+ *((uint8_t*) dest) = val;
return 1;
}
@@ -433,7 +433,7 @@ m68hc11spi_io_write_buffer (struct hw *me,
SIM_DESC sd;
struct m68hc11spi *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
@@ -441,7 +441,7 @@ m68hc11spi_io_write_buffer (struct hw *me,
cpu = STATE_CPU (sd, 0);
controller = hw_data (me);
- val = *((const unsigned8*) source);
+ val = *((const uint8_t*) source);
switch (base)
{
case M6811_SPCR:
diff --git a/sim/m68hc11/dv-m68hc11tim.c b/sim/m68hc11/dv-m68hc11tim.c
index fc4bb66bd818..a2a6603e79a3 100644
--- a/sim/m68hc11/dv-m68hc11tim.c
+++ b/sim/m68hc11/dv-m68hc11tim.c
@@ -84,10 +84,10 @@ struct m68hc11tim
unsigned long cop_delay;
unsigned long rti_delay;
unsigned long ovf_delay;
- signed64 clock_prescaler;
- signed64 tcnt_adjust;
- signed64 cop_prev_interrupt;
- signed64 rti_prev_interrupt;
+ int64_t clock_prescaler;
+ int64_t tcnt_adjust;
+ int64_t cop_prev_interrupt;
+ int64_t rti_prev_interrupt;
/* Periodic timers. */
struct hw_event *rti_timer_event;
@@ -158,8 +158,8 @@ m68hc11tim_port_event (struct hw *me,
SIM_DESC sd;
struct m68hc11tim *controller;
sim_cpu *cpu;
- unsigned8 val;
- unsigned16 tcnt;
+ uint8_t val;
+ uint16_t tcnt;
controller = hw_data (me);
sd = hw_system (me);
@@ -207,7 +207,7 @@ m68hc11tim_port_event (struct hw *me,
}
case CAPTURE:
- tcnt = (uint16) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
+ tcnt = (uint16_t) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
/ controller->clock_prescaler);
switch (level)
{
@@ -252,8 +252,8 @@ m68hc11tim_timer_event (struct hw *me, void *data)
unsigned flags;
unsigned long tcnt_internal;
unsigned long tcnt, tcnt_prev;
- signed64 tcnt_insn_end;
- signed64 tcnt_insn_start;
+ int64_t tcnt_insn_end;
+ int64_t tcnt_insn_start;
int i;
sim_events *events;
@@ -471,13 +471,13 @@ io_reg_desc pactl_desc[] = {
};
static double
-to_realtime (sim_cpu *cpu, signed64 t)
+to_realtime (sim_cpu *cpu, int64_t t)
{
return (double) (t) / (double) (cpu->cpu_frequency / 4);
}
const char*
-cycle_to_string (sim_cpu *cpu, signed64 t, int flags)
+cycle_to_string (sim_cpu *cpu, int64_t t, int flags)
{
char time_buf[32];
char cycle_buf[32];
@@ -520,7 +520,7 @@ m68hc11tim_print_timer (struct hw *me, const char *name,
}
else
{
- signed64 t;
+ int64_t t;
sim_cpu *cpu;
cpu = STATE_CPU (sd, 0);
@@ -535,11 +535,11 @@ static void
m68hc11tim_info (struct hw *me)
{
SIM_DESC sd;
- uint16 base = 0;
+ uint16_t base = 0;
sim_cpu *cpu;
struct m68hc11tim *controller;
- uint8 val;
- uint16 val16;
+ uint8_t val;
+ uint16_t val16;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
@@ -643,7 +643,7 @@ m68hc11tim_io_read_buffer (struct hw *me,
SIM_DESC sd;
struct m68hc11tim *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
unsigned cnt = 0;
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
@@ -660,12 +660,12 @@ m68hc11tim_io_read_buffer (struct hw *me,
Reading in a 16-bit register will be split in two accesses
but this will be atomic within the simulator. */
case M6811_TCTN_H:
- val = (uint8) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
+ val = (uint8_t) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
/ (controller->clock_prescaler * 256));
break;
case M6811_TCTN_L:
- val = (uint8) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
+ val = (uint8_t) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
/ controller->clock_prescaler);
break;
@@ -673,7 +673,7 @@ m68hc11tim_io_read_buffer (struct hw *me,
val = cpu->ios[base];
break;
}
- *((unsigned8*) dest) = val;
+ *((uint8_t*) dest) = val;
dest = (char*) dest + 1;
base++;
nr_bytes--;
@@ -692,8 +692,8 @@ m68hc11tim_io_write_buffer (struct hw *me,
SIM_DESC sd;
struct m68hc11tim *controller;
sim_cpu *cpu;
- unsigned8 val, n;
- signed64 adj;
+ uint8_t val, n;
+ int64_t adj;
int reset_compare = 0;
int reset_overflow = 0;
int cnt = 0;
@@ -706,7 +706,7 @@ m68hc11tim_io_write_buffer (struct hw *me,
while (nr_bytes)
{
- val = *((const unsigned8*) source);
+ val = *((const uint8_t*) source);
switch (base)
{
/* Set the timer counter low part, trying to preserve the low part.
@@ -715,10 +715,10 @@ m68hc11tim_io_write_buffer (struct hw *me,
in 64-bit to avoid overflow problems. */
case M6811_TCTN_L:
adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
- / (controller->clock_prescaler * (signed64) 256)) & 0x0FF;
+ / (controller->clock_prescaler * (int64_t) 256)) & 0x0FF;
adj = cpu->cpu_absolute_cycle
- - (adj * controller->clock_prescaler * (signed64) 256)
- - ((signed64) adj * controller->clock_prescaler);
+ - (adj * controller->clock_prescaler * (int64_t) 256)
+ - ((int64_t) adj * controller->clock_prescaler);
controller->tcnt_adjust = adj;
reset_compare = 1;
reset_overflow = 1;
@@ -728,7 +728,7 @@ m68hc11tim_io_write_buffer (struct hw *me,
adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
/ controller->clock_prescaler) & 0x0ff;
adj = cpu->cpu_absolute_cycle
- - ((signed64) val * controller->clock_prescaler * (signed64) 256)
+ - ((int64_t) val * controller->clock_prescaler * (int64_t) 256)
- (adj * controller->clock_prescaler);
controller->tcnt_adjust = adj;
reset_compare = 1;
diff --git a/sim/m68hc11/dv-nvram.c b/sim/m68hc11/dv-nvram.c
index 50363b2f7ff0..f02160833047 100644
--- a/sim/m68hc11/dv-nvram.c
+++ b/sim/m68hc11/dv-nvram.c
@@ -106,7 +106,7 @@ struct nvram
{
address_word base_address; /* Base address of ram. */
unsigned size; /* Size of ram. */
- unsigned8 *data; /* Pointer to ram memory. */
+ uint8_t *data; /* Pointer to ram memory. */
const char *file_name; /* Path of ram file. */
int fd; /* File description of opened ram file. */
enum nvram_mode mode; /* How load/save ram file. */
diff --git a/sim/m68hc11/emulos.c b/sim/m68hc11/emulos.c
index 111bd99f55b7..b66117503c1d 100644
--- a/sim/m68hc11/emulos.c
+++ b/sim/m68hc11/emulos.c
@@ -107,7 +107,7 @@ emul_write (sim_cpu *cpu)
cpu->cpu_running = 0;
while (size)
{
- uint8 val = memory_read8 (cpu, addr);
+ uint8_t val = memory_read8 (cpu, addr);
if (write (0, &val, 1) != 1)
printf ("write failed: %s\n", strerror (errno));
diff --git a/sim/m68hc11/gencode.c b/sim/m68hc11/gencode.c
index 6ea2236588d1..fcc4b05b6ac5 100644
--- a/sim/m68hc11/gencode.c
+++ b/sim/m68hc11/gencode.c
@@ -134,7 +134,7 @@ struct m6811_opcode_pattern m6811_opcode_patterns[] = {
{ "rts11", "addr = cpu_m68hc11_pop_uint16 (cpu); cpu_set_pc (cpu, addr); cpu_return (cpu)" },
{ "rts12", "addr = cpu_m68hc12_pop_uint16 (cpu); cpu_set_pc (cpu, addr); cpu_return (cpu)" },
- { "mul16", "dst16 = ((uint16) src8 & 0x0FF) * ((uint16) dst8 & 0x0FF)",
+ { "mul16", "dst16 = ((uint16_t) src8 & 0x0FF) * ((uint16_t) dst8 & 0x0FF)",
"cpu_set_ccr_C (cpu, src8 & 0x80)" },
{ "neg8", "dst8 = - src8",
"cpu_set_ccr_C (cpu, src8 == 0); cpu_ccr_update_tst8 (cpu, dst8)" },
@@ -227,7 +227,7 @@ dst16 = dst16 + src16", 0 },
{ "txys16", "dst16 = src16 - 1;"},
/* Add b to X or Y with an unsigned extension 8->16. Flags not changed. */
- { "abxy16","dst16 = dst16 + (uint16) src8"},
+ { "abxy16","dst16 = dst16 + (uint16_t) src8"},
/* After 'daa', the Z flag is undefined. Mark it as changed. */
{ "daa8", "cpu_special (cpu, M6811_DAA)" },
@@ -256,8 +256,8 @@ cpu_set_ccr_V (cpu, 1);\n\
cpu_set_ccr_C (cpu, dst16 == 0);\n\
}\nelse\n{\n\
unsigned long l = (unsigned long) (dst16) << 16;\n\
-cpu_set_d (cpu, (uint16) (l % (unsigned long) (src16)));\n\
-dst16 = (uint16) (l / (unsigned long) (src16));\n\
+cpu_set_d (cpu, (uint16_t) (l % (unsigned long) (src16)));\n\
+dst16 = (uint16_t) (l / (unsigned long) (src16));\n\
cpu_set_ccr_V (cpu, 0);\n\
cpu_set_ccr_C (cpu, 0);\n\
cpu_set_ccr_Z (cpu, dst16 == 0);\n\
@@ -289,8 +289,8 @@ cpu_set_ccr_Z (cpu, dst16 == 0);\n\
{ "call_ind", "cpu_special (cpu, M6812_CALL_INDIRECT)" },
{ "dbcc8", "cpu_dbcc (cpu)" },
{ "ediv", "cpu_special (cpu, M6812_EDIV)" },
- { "emul", "{ uint32 src1 = (uint32) cpu_get_d (cpu);\
- uint32 src2 = (uint32) cpu_get_y (cpu);\
+ { "emul", "{ uint32_t src1 = (uint32_t) cpu_get_d (cpu);\
+ uint32_t src2 = (uint32_t) cpu_get_y (cpu);\
src1 *= src2;\
cpu_set_d (cpu, src1);\
cpu_set_y (cpu, src1 >> 16);\
@@ -1284,9 +1284,9 @@ print (FILE *fp, int col, const char *msg, ...)
- End of input operands.
Example:
- (x),a->a addr = x + (uint16) (fetch8 (cpu));
+ (x),a->a addr = x + (uint16_t) (fetch8 (cpu));
src8 = a
- *,#,r addr = (uint16) (fetch8 (cpu)) <- Temporary 'addr'
+ *,#,r addr = (uint16_t) (fetch8 (cpu)) <- Temporary 'addr'
src8 = read_mem8 (cpu, addr)
dst8 = fetch8 (cpu)
addr = fetch_relbranch (cpu) <- Final 'addr'
@@ -1357,7 +1357,7 @@ gen_fetch_operands (FILE *fp, int col,
addr_set = 1;
current_insn_size += 1;
- print (fp, col, "addr = (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = (uint16_t) cpu_fetch8 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
break;
@@ -1370,13 +1370,13 @@ gen_fetch_operands (FILE *fp, int col,
if (strncmp (operands, "(x)", 3) == 0)
{
current_insn_size += 1;
- print (fp, col, "addr = cpu_get_x (cpu) + (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = cpu_get_x (cpu) + (uint16_t) cpu_fetch8 (cpu);");
operands += 3;
}
else if (strncmp (operands, "(y)", 3) == 0)
{
current_insn_size += 1;
- print (fp, col, "addr = cpu_get_y (cpu) + (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = cpu_get_y (cpu) + (uint16_t) cpu_fetch8 (cpu);");
operands += 3;
}
else if (strncmp (operands, "()", 2) == 0)
@@ -1408,7 +1408,7 @@ gen_fetch_operands (FILE *fp, int col,
{
addr_set = 1;
current_insn_size += 1;
- print (fp, col, "addr = cpu_get_x (cpu) + (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = cpu_get_x (cpu) + (uint16_t) cpu_fetch8 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
operands += 2;
@@ -1417,7 +1417,7 @@ gen_fetch_operands (FILE *fp, int col,
{
addr_set = 1;
current_insn_size += 1;
- print (fp, col, "addr = cpu_get_y (cpu) + (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = cpu_get_y (cpu) + (uint16_t) cpu_fetch8 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
operands += 2;
@@ -1668,7 +1668,7 @@ gen_save_result (FILE *fp, int col,
if (addr_set == 0)
{
current_insn_size += 1;
- print (fp, col, "addr = (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = (uint16_t) cpu_fetch8 (cpu);");
}
result_size = operand_size;
print (fp, col, "memory_write%s (cpu, addr, dst%s);",
@@ -1995,11 +1995,11 @@ gen_function_entry (FILE *fp, const char *name, int locals)
/* Interpretor local variables. */
print (fp, indent_level, "unsigned char op;");
- print (fp, indent_level, "uint16 addr, src16, dst16;");
+ print (fp, indent_level, "uint16_t addr, src16, dst16;");
if (locals & USE_SRC8)
- print (fp, indent_level, "uint8 src8;\n");
+ print (fp, indent_level, "uint8_t src8;\n");
if (locals & USE_DST8)
- print (fp, indent_level, "uint8 dst8;\n");
+ print (fp, indent_level, "uint8_t dst8;\n");
}
void
diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c
index 016edb6fb24c..ab3c5a8e8619 100644
--- a/sim/m68hc11/interp.c
+++ b/sim/m68hc11/interp.c
@@ -533,7 +533,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
static int
m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- uint16 val;
+ uint16_t val;
int size = 2;
switch (rn)
@@ -597,7 +597,7 @@ m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
static int
m68hc11_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- uint16 val;
+ uint16_t val;
val = *memory++;
if (length == 2)
diff --git a/sim/m68hc11/interrupts.c b/sim/m68hc11/interrupts.c
index 1c097844b881..4e2a16af53fd 100644
--- a/sim/m68hc11/interrupts.c
+++ b/sim/m68hc11/interrupts.c
@@ -95,7 +95,7 @@ struct interrupt_def idefs[] = {
#endif
};
-#define CYCLES_MAX ((((signed64) 1) << 62) - 1)
+#define CYCLES_MAX ((((int64_t) 1) << 62) - 1)
enum
{
@@ -174,7 +174,7 @@ interrupts_reset (struct interrupts *interrupts)
if (interrupts->cpu->cpu_mode == M6811_SMOD)
{
bfd_vma addr = interrupts->vectors_addr;
- uint16 vector = 0x0100 - 3 * (M6811_INT_NUMBER - 1);
+ uint16_t vector = 0x0100 - 3 * (M6811_INT_NUMBER - 1);
for (i = 0; i < M6811_INT_NUMBER; i++)
{
memory_write16 (interrupts->cpu, addr, vector);
@@ -285,7 +285,7 @@ void
interrupts_update_pending (struct interrupts *interrupts)
{
int i;
- uint8 *ioregs;
+ uint8_t *ioregs;
unsigned long clear_mask;
unsigned long set_mask;
@@ -296,7 +296,7 @@ interrupts_update_pending (struct interrupts *interrupts)
for (i = 0; i < ARRAY_SIZE (idefs); i++)
{
struct interrupt_def *idef = &idefs[i];
- uint8 data;
+ uint8_t data;
/* Look if the interrupt is enabled. */
if (idef->enable_paddr)
@@ -332,7 +332,7 @@ interrupts_update_pending (struct interrupts *interrupts)
Also implements the breakpoint-on-interrupt. */
if (set_mask)
{
- signed64 cycle = cpu_current_cycle (interrupts->cpu);
+ int64_t cycle = cpu_current_cycle (interrupts->cpu);
int must_stop = 0;
for (i = 0; i < M6811_INT_NUMBER; i++)
@@ -427,7 +427,7 @@ int
interrupts_process (struct interrupts *interrupts)
{
int id;
- uint8 ccr;
+ uint8_t ccr;
/* See if interrupts are enabled/disabled and keep track of the
number of cycles the interrupts are masked. Such information is
@@ -441,7 +441,7 @@ interrupts_process (struct interrupts *interrupts)
else if (interrupts->start_mask_cycle >= 0
&& (ccr & M6811_I_BIT) == 0)
{
- signed64 t = cpu_current_cycle (interrupts->cpu);
+ int64_t t = cpu_current_cycle (interrupts->cpu);
t -= interrupts->start_mask_cycle;
if (t < interrupts->min_mask_cycles)
@@ -460,7 +460,7 @@ interrupts_process (struct interrupts *interrupts)
else if (interrupts->xirq_start_mask_cycle >= 0
&& (ccr & M6811_X_BIT) == 0)
{
- signed64 t = cpu_current_cycle (interrupts->cpu);
+ int64_t t = cpu_current_cycle (interrupts->cpu);
t -= interrupts->xirq_start_mask_cycle;
if (t < interrupts->xirq_min_mask_cycles)
@@ -474,7 +474,7 @@ interrupts_process (struct interrupts *interrupts)
id = interrupts_get_current (interrupts);
if (id >= 0)
{
- uint16 addr;
+ uint16_t addr;
struct interrupt_history *h;
/* Implement the breakpoint-on-interrupt. */
@@ -533,7 +533,7 @@ interrupts_raise (struct interrupts *interrupts, enum M6811_INT number)
void
interrupts_info (SIM_DESC sd, struct interrupts *interrupts)
{
- signed64 t, prev_interrupt;
+ int64_t t, prev_interrupt;
int i;
sim_io_printf (sd, "Interrupts Info:\n");
@@ -621,7 +621,7 @@ interrupts_info (SIM_DESC sd, struct interrupts *interrupts)
{
int which;
struct interrupt_history *h;
- signed64 dt;
+ int64_t dt;
which = interrupts->history_index - i - 1;
if (which < 0)
diff --git a/sim/m68hc11/interrupts.h b/sim/m68hc11/interrupts.h
index 2d208887bc32..d66fefbbb3f4 100644
--- a/sim/m68hc11/interrupts.h
+++ b/sim/m68hc11/interrupts.h
@@ -88,10 +88,10 @@ struct interrupt_history
enum M6811_INT type;
/* CPU cycle when interrupt handler is called. */
- signed64 taken_cycle;
+ int64_t taken_cycle;
/* CPU cycle when the interrupt is first raised by the device. */
- signed64 raised_cycle;
+ int64_t raised_cycle;
};
#define SIM_STOP_WHEN_RAISED 1
@@ -101,7 +101,7 @@ struct interrupt_history
struct interrupt
{
/* CPU cycle when the interrupt is raised by the device. */
- signed64 cpu_cycle;
+ int64_t cpu_cycle;
/* Number of times the interrupt was raised. */
unsigned long raised_count;
@@ -129,7 +129,7 @@ struct interrupts {
/* Address of vector table. This is set depending on the
68hc11 init mode. */
- uint16 vectors_addr;
+ uint16_t vectors_addr;
/* Priority order of interrupts. This is controlled by setting the HPRIO
IO register. */
@@ -139,16 +139,16 @@ struct interrupts {
/* Simulator statistics to report useful debug information to users. */
/* - Max/Min number of CPU cycles executed with interrupts masked. */
- signed64 start_mask_cycle;
- signed64 min_mask_cycles;
- signed64 max_mask_cycles;
- signed64 last_mask_cycles;
+ int64_t start_mask_cycle;
+ int64_t min_mask_cycles;
+ int64_t max_mask_cycles;
+ int64_t last_mask_cycles;
/* - Same for XIRQ. */
- signed64 xirq_start_mask_cycle;
- signed64 xirq_min_mask_cycles;
- signed64 xirq_max_mask_cycles;
- signed64 xirq_last_mask_cycles;
+ int64_t xirq_start_mask_cycle;
+ int64_t xirq_min_mask_cycles;
+ int64_t xirq_max_mask_cycles;
+ int64_t xirq_last_mask_cycles;
/* - Total number of interrupts raised. */
unsigned long nb_interrupts_raised;
diff --git a/sim/m68hc11/m68hc11_sim.c b/sim/m68hc11/m68hc11_sim.c
index 80a450d04261..6ec45f782062 100644
--- a/sim/m68hc11/m68hc11_sim.c
+++ b/sim/m68hc11/m68hc11_sim.c
@@ -101,7 +101,7 @@ cpu_option_handler (SIM_DESC sd, sim_cpu *cpu,
void
-cpu_call (sim_cpu *cpu, uint16 addr)
+cpu_call (sim_cpu *cpu, uint16_t addr)
{
cpu_set_pc (cpu, addr);
@@ -114,13 +114,13 @@ cpu_return (sim_cpu *cpu)
/* Set the stack pointer and re-compute the current frame. */
void
-cpu_set_sp (sim_cpu *cpu, uint16 val)
+cpu_set_sp (sim_cpu *cpu, uint16_t val)
{
cpu->cpu_regs.sp = val;
}
-static uint16
-cpu_get_reg (sim_cpu *cpu, uint8 reg)
+static uint16_t
+cpu_get_reg (sim_cpu *cpu, uint8_t reg)
{
switch (reg)
{
@@ -141,8 +141,8 @@ cpu_get_reg (sim_cpu *cpu, uint8 reg)
}
}
-static uint16
-cpu_get_src_reg (sim_cpu *cpu, uint8 reg)
+static uint16_t
+cpu_get_src_reg (sim_cpu *cpu, uint8_t reg)
{
switch (reg)
{
@@ -176,7 +176,7 @@ cpu_get_src_reg (sim_cpu *cpu, uint8 reg)
}
static void
-cpu_set_dst_reg (sim_cpu *cpu, uint8 reg, uint16 val)
+cpu_set_dst_reg (sim_cpu *cpu, uint8_t reg, uint16_t val)
{
switch (reg)
{
@@ -218,7 +218,7 @@ cpu_set_dst_reg (sim_cpu *cpu, uint8 reg, uint16 val)
}
static void
-cpu_set_reg (sim_cpu *cpu, uint8 reg, uint16 val)
+cpu_set_reg (sim_cpu *cpu, uint8_t reg, uint16_t val)
{
switch (reg)
{
@@ -245,13 +245,13 @@ cpu_set_reg (sim_cpu *cpu, uint8 reg, uint16 val)
/* Returns the address of a 68HC12 indexed operand.
Pre and post modifications are handled on the source register. */
-uint16
+uint16_t
cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted)
{
- uint8 reg;
- uint16 sval;
- uint16 addr;
- uint8 code;
+ uint8_t reg;
+ uint16_t sval;
+ uint16_t addr;
+ uint8_t code;
code = cpu_fetch8 (cpu);
@@ -350,29 +350,29 @@ cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted)
return addr;
}
-static uint8
+static uint8_t
cpu_get_indexed_operand8 (sim_cpu *cpu, int restricted)
{
- uint16 addr;
+ uint16_t addr;
addr = cpu_get_indexed_operand_addr (cpu, restricted);
return memory_read8 (cpu, addr);
}
-static uint16
+static uint16_t
cpu_get_indexed_operand16 (sim_cpu *cpu, int restricted)
{
- uint16 addr;
+ uint16_t addr;
addr = cpu_get_indexed_operand_addr (cpu, restricted);
return memory_read16 (cpu, addr);
}
void
-cpu_move8 (sim_cpu *cpu, uint8 code)
+cpu_move8 (sim_cpu *cpu, uint8_t code)
{
- uint8 src;
- uint16 addr;
+ uint8_t src;
+ uint16_t addr;
switch (code)
{
@@ -416,10 +416,10 @@ cpu_move8 (sim_cpu *cpu, uint8 code)
}
void
-cpu_move16 (sim_cpu *cpu, uint8 code)
+cpu_move16 (sim_cpu *cpu, uint8_t code)
{
- uint16 src;
- uint16 addr;
+ uint16_t src;
+ uint16_t addr;
switch (code)
{
@@ -530,7 +530,7 @@ cpu_reset (sim_cpu *cpu)
int
cpu_restart (sim_cpu *cpu)
{
- uint16 addr;
+ uint16_t addr;
/* Get CPU starting address depending on the CPU mode. */
if (cpu->cpu_use_elf_start == 0)
@@ -591,7 +591,7 @@ print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val, int mode)
void
print_io_byte (SIM_DESC sd, const char *name, io_reg_desc *desc,
- uint8 val, uint16 addr)
+ uint8_t val, uint16_t addr)
{
sim_io_printf (sd, " %-9.9s @ 0x%04x 0x%02x ", name, addr, val);
if (desc)
@@ -600,7 +600,7 @@ print_io_byte (SIM_DESC sd, const char *name, io_reg_desc *desc,
void
print_io_word (SIM_DESC sd, const char *name, io_reg_desc *desc,
- uint16 val, uint16 addr)
+ uint16_t val, uint16_t addr)
{
sim_io_printf (sd, " %-9.9s @ 0x%04x 0x%04x ", name, addr, val);
if (desc)
@@ -608,7 +608,7 @@ print_io_word (SIM_DESC sd, const char *name, io_reg_desc *desc,
}
void
-cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val)
+cpu_ccr_update_tst8 (sim_cpu *cpu, uint8_t val)
{
cpu_set_ccr_V (cpu, 0);
cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
@@ -616,10 +616,10 @@ cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val)
}
-uint16
+uint16_t
cpu_fetch_relbranch (sim_cpu *cpu)
{
- uint16 addr = (uint16) cpu_fetch8 (cpu);
+ uint16_t addr = (uint16_t) cpu_fetch8 (cpu);
if (addr & 0x0080)
{
@@ -629,10 +629,10 @@ cpu_fetch_relbranch (sim_cpu *cpu)
return addr;
}
-uint16
+uint16_t
cpu_fetch_relbranch16 (sim_cpu *cpu)
{
- uint16 addr = cpu_fetch16 (cpu);
+ uint16_t addr = cpu_fetch16 (cpu);
addr += cpu->cpu_regs.pc;
return addr;
@@ -664,10 +664,10 @@ cpu_push_all (sim_cpu *cpu)
void
cpu_dbcc (sim_cpu *cpu)
{
- uint8 code;
- uint16 addr;
- uint16 inc;
- uint16 reg;
+ uint8_t code;
+ uint16_t addr;
+ uint16_t inc;
+ uint16_t reg;
code = cpu_fetch8 (cpu);
switch (code & 0xc0)
@@ -703,11 +703,11 @@ cpu_dbcc (sim_cpu *cpu)
}
void
-cpu_exg (sim_cpu *cpu, uint8 code)
+cpu_exg (sim_cpu *cpu, uint8_t code)
{
- uint8 r1, r2;
- uint16 src1;
- uint16 src2;
+ uint8_t r1, r2;
+ uint16_t src1;
+ uint16_t src2;
r1 = (code >> 4) & 0x07;
r2 = code & 0x07;
@@ -741,7 +741,7 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
{
case M6811_RTI:
{
- uint8 ccr;
+ uint8_t ccr;
ccr = cpu_m68hc11_pop_uint8 (cpu);
cpu_set_ccr (cpu, ccr);
@@ -755,7 +755,7 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
case M6812_RTI:
{
- uint8 ccr;
+ uint8_t ccr;
ccr = cpu_m68hc12_pop_uint8 (cpu);
cpu_set_ccr (cpu, ccr);
@@ -791,7 +791,7 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
case M6811_ILLEGAL:
if (cpu->cpu_emul_syscall)
{
- uint8 op = memory_read8 (cpu,
+ uint8_t op = memory_read8 (cpu,
cpu_get_pc (cpu) - 1);
if (op == 0x41)
{
@@ -833,8 +833,8 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
case M6812_IDIVS:
{
- int32 src1 = (int16) cpu_get_d (cpu);
- int32 src2 = (int16) cpu_get_x (cpu);
+ int32_t src1 = (int16_t) cpu_get_d (cpu);
+ int32_t src2 = (int16_t) cpu_get_x (cpu);
if (src2 == 0)
{
@@ -855,9 +855,9 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
case M6812_EDIV:
{
- uint32 src1 = (uint32) cpu_get_x (cpu);
- uint32 src2 = (uint32) (cpu_get_y (cpu) << 16)
- | (uint32) (cpu_get_d (cpu));
+ uint32_t src1 = (uint32_t) cpu_get_x (cpu);
+ uint32_t src2 = (uint32_t) (cpu_get_y (cpu) << 16)
+ | (uint32_t) (cpu_get_d (cpu));
if (src1 == 0)
{
@@ -878,9 +878,9 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
case M6812_EDIVS:
{
- int32 src1 = (int16) cpu_get_x (cpu);
- int32 src2 = (uint32) (cpu_get_y (cpu) << 16)
- | (uint32) (cpu_get_d (cpu));
+ int32_t src1 = (int16_t) cpu_get_x (cpu);
+ int32_t src2 = (uint32_t) (cpu_get_y (cpu) << 16)
+ | (uint32_t) (cpu_get_d (cpu));
if (src1 == 0)
{
@@ -901,10 +901,10 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
case M6812_EMULS:
{
- int32 src1, src2;
+ int32_t src1, src2;
- src1 = (int16) cpu_get_d (cpu);
- src2 = (int16) cpu_get_y (cpu);
+ src1 = (int16_t) cpu_get_d (cpu);
+ src2 = (int16_t) cpu_get_y (cpu);
src1 = src1 * src2;
cpu_set_d (cpu, src1 & 0x0ffff);
cpu_set_y (cpu, src1 >> 16);
@@ -916,15 +916,15 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
case M6812_EMACS:
{
- int32 src1, src2;
- uint16 addr;
+ int32_t src1, src2;
+ uint16_t addr;
addr = cpu_fetch16 (cpu);
- src1 = (int16) memory_read16 (cpu, cpu_get_x (cpu));
- src2 = (int16) memory_read16 (cpu, cpu_get_y (cpu));
+ src1 = (int16_t) memory_read16 (cpu, cpu_get_x (cpu));
+ src2 = (int16_t) memory_read16 (cpu, cpu_get_y (cpu));
src1 = src1 * src2;
- src2 = (((uint32) memory_read16 (cpu, addr)) << 16)
- | (uint32) memory_read16 (cpu, addr + 2);
+ src2 = (((uint32_t) memory_read16 (cpu, addr)) << 16)
+ | (uint32_t) memory_read16 (cpu, addr + 2);
memory_write16 (cpu, addr, (src1 + src2) >> 16);
memory_write16 (cpu, addr + 2, (src1 + src2));
@@ -935,8 +935,8 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
case M6812_CALL:
{
- uint8 page;
- uint16 addr;
+ uint8_t page;
+ uint16_t addr;
addr = cpu_fetch16 (cpu);
page = cpu_fetch8 (cpu);
@@ -951,9 +951,9 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
case M6812_CALL_INDIRECT:
{
- uint8 code;
- uint16 addr;
- uint8 page;
+ uint8_t code;
+ uint16_t addr;
+ uint8_t page;
code = memory_read8 (cpu, cpu_get_pc (cpu));
/* Indirect addressing call has the page specified in the
@@ -979,8 +979,8 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
case M6812_RTC:
{
- uint8 page = cpu_m68hc12_pop_uint8 (cpu);
- uint16 addr = cpu_m68hc12_pop_uint16 (cpu);
+ uint8_t page = cpu_m68hc12_pop_uint8 (cpu);
+ uint16_t addr = cpu_m68hc12_pop_uint16 (cpu);
cpu_set_page (cpu, page);
cpu_set_pc (cpu, addr);
@@ -1019,7 +1019,7 @@ cpu_single_step (sim_cpu *cpu)
/* VARARGS */
void
sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
- uint16 addr, const char *message, ...)
+ uint16_t addr, const char *message, ...)
{
char buf[1024];
va_list args;
@@ -1035,7 +1035,7 @@ sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
void
cpu_memory_exception (sim_cpu *cpu, SIM_SIGNAL excep,
- uint16 addr, const char *message)
+ uint16_t addr, const char *message)
{
if (cpu->cpu_running == 0)
return;
diff --git a/sim/m68hc11/sim-main.h b/sim/m68hc11/sim-main.h
index 3c00f757b51d..e667c33a7055 100644
--- a/sim/m68hc11/sim-main.h
+++ b/sim/m68hc11/sim-main.h
@@ -32,14 +32,6 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-signal.h"
#include "sim-types.h"
-typedef unsigned8 uint8;
-typedef unsigned16 uint16;
-typedef signed16 int16;
-typedef unsigned32 uint32;
-typedef signed32 int32;
-typedef unsigned64 uint64;
-typedef signed64 int64;
-
struct _sim_cpu;
#include "interrupts.h"
@@ -98,9 +90,9 @@ typedef struct io_reg_desc io_reg_desc;
extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
int mode);
extern void print_io_byte (SIM_DESC sd, const char *name,
- io_reg_desc *desc, uint8 val, uint16 addr);
+ io_reg_desc *desc, uint8_t val, uint16_t addr);
extern void print_io_word (SIM_DESC sd, const char *name,
- io_reg_desc *desc, uint16 val, uint16 addr);
+ io_reg_desc *desc, uint16_t val, uint16_t addr);
/* List of special 68HC11&68HC12 instructions that are not handled by the
@@ -161,11 +153,11 @@ struct _sim_cpu {
/* CPU absolute cycle time. The cycle time is updated after
each instruction, by the number of cycles taken by the instruction.
It is cleared only when reset occurs. */
- signed64 cpu_absolute_cycle;
+ int64_t cpu_absolute_cycle;
/* Number of cycles to increment after the current instruction.
This is also the number of ticks for the generic event scheduler. */
- uint8 cpu_current_cycle;
+ uint8_t cpu_current_cycle;
int cpu_emul_syscall;
int cpu_is_initialized;
int cpu_running;
@@ -182,7 +174,7 @@ struct _sim_cpu {
/* The starting address specified in ELF header. */
int cpu_elf_start;
- uint16 cpu_insn_pc;
+ uint16_t cpu_insn_pc;
/* CPU frequency. This is the quartz frequency. It is divided by 4 to
get the cycle time. This is used for the timer rate and for the baud
@@ -197,15 +189,15 @@ struct _sim_cpu {
enum cpu_type cpu_type;
/* Initial value of the CONFIG register. */
- uint8 cpu_config;
- uint8 cpu_use_local_config;
+ uint8_t cpu_config;
+ uint8_t cpu_use_local_config;
- uint8 ios[MAX_PORTS];
+ uint8_t ios[MAX_PORTS];
/* Memory bank parameters which describe how the memory bank window
is mapped in memory and how to convert it in virtual address. */
- uint16 bank_start;
- uint16 bank_end;
+ uint16_t bank_start;
+ uint16_t bank_end;
address_word bank_virtual;
unsigned bank_shift;
@@ -219,14 +211,14 @@ struct _sim_cpu {
/* Returns the cpu absolute cycle time (A virtual counter incremented
at each 68HC11 E clock). */
#define cpu_current_cycle(cpu) ((cpu)->cpu_absolute_cycle)
-#define cpu_add_cycles(cpu, T) ((cpu)->cpu_current_cycle += (signed64) (T))
+#define cpu_add_cycles(cpu, T) ((cpu)->cpu_current_cycle += (int64_t) (T))
#define cpu_is_running(cpu) ((cpu)->cpu_running)
/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
#define cpu_get_io_base(cpu) \
- (((uint16)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
+ (((uint16_t)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
#define cpu_get_reg_base(cpu) \
- (((uint16)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
+ (((uint16_t)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
/* Returns the different CPU registers. */
#define cpu_get_ccr(cpu) ((cpu)->cpu_regs.ccr)
@@ -288,7 +280,7 @@ struct _sim_cpu {
extern void cpu_memory_exception (sim_cpu *cpu,
SIM_SIGNAL excep,
- uint16 addr,
+ uint16_t addr,
const char *message);
STATIC_INLINE UNUSED address_word
@@ -302,10 +294,10 @@ phys_to_virt (sim_cpu *cpu, address_word addr)
return (address_word) (addr);
}
-STATIC_INLINE UNUSED uint8
-memory_read8 (sim_cpu *cpu, uint16 addr)
+STATIC_INLINE UNUSED uint8_t
+memory_read8 (sim_cpu *cpu, uint16_t addr)
{
- uint8 val;
+ uint8_t val;
if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
{
@@ -316,7 +308,7 @@ memory_read8 (sim_cpu *cpu, uint16 addr)
}
STATIC_INLINE UNUSED void
-memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
+memory_write8 (sim_cpu *cpu, uint16_t addr, uint8_t val)
{
if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
{
@@ -325,23 +317,23 @@ memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
}
}
-STATIC_INLINE UNUSED uint16
-memory_read16 (sim_cpu *cpu, uint16 addr)
+STATIC_INLINE UNUSED uint16_t
+memory_read16 (sim_cpu *cpu, uint16_t addr)
{
- uint8 b[2];
+ uint8_t b[2];
if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
{
cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
"Read error");
}
- return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
+ return (((uint16_t) (b[0])) << 8) | ((uint16_t) b[1]);
}
STATIC_INLINE UNUSED void
-memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
+memory_write16 (sim_cpu *cpu, uint16_t addr, uint16_t val)
{
- uint8 b[2];
+ uint8_t b[2];
b[0] = val >> 8;
b[1] = val;
@@ -352,10 +344,10 @@ memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
}
}
extern void
-cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val);
+cpu_ccr_update_tst8 (sim_cpu *cpu, uint8_t val);
STATIC_INLINE UNUSED void
-cpu_ccr_update_tst16 (sim_cpu *cpu, uint16 val)
+cpu_ccr_update_tst16 (sim_cpu *cpu, uint16_t val)
{
cpu_set_ccr_V (cpu, 0);
cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
@@ -363,7 +355,7 @@ cpu_ccr_update_tst16 (sim_cpu *cpu, uint16 val)
}
STATIC_INLINE UNUSED void
-cpu_ccr_update_shift8 (sim_cpu *cpu, uint8 val)
+cpu_ccr_update_shift8 (sim_cpu *cpu, uint8_t val)
{
cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
@@ -371,7 +363,7 @@ cpu_ccr_update_shift8 (sim_cpu *cpu, uint8 val)
}
STATIC_INLINE UNUSED void
-cpu_ccr_update_shift16 (sim_cpu *cpu, uint16 val)
+cpu_ccr_update_shift16 (sim_cpu *cpu, uint16_t val)
{
cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
@@ -379,7 +371,7 @@ cpu_ccr_update_shift16 (sim_cpu *cpu, uint16 val)
}
STATIC_INLINE UNUSED void
-cpu_ccr_update_add8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
+cpu_ccr_update_add8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
{
cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
@@ -389,7 +381,7 @@ cpu_ccr_update_add8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
STATIC_INLINE UNUSED void
-cpu_ccr_update_sub8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
+cpu_ccr_update_sub8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
{
cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
@@ -398,7 +390,7 @@ cpu_ccr_update_sub8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
}
STATIC_INLINE UNUSED void
-cpu_ccr_update_add16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
+cpu_ccr_update_add16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
{
cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
@@ -407,7 +399,7 @@ cpu_ccr_update_add16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
}
STATIC_INLINE UNUSED void
-cpu_ccr_update_sub16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
+cpu_ccr_update_sub16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
{
cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
@@ -417,39 +409,39 @@ cpu_ccr_update_sub16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
/* Push and pop instructions for 68HC11 (next-available stack mode). */
STATIC_INLINE UNUSED void
-cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8 val)
+cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8_t val)
{
- uint16 addr = cpu->cpu_regs.sp;
+ uint16_t addr = cpu->cpu_regs.sp;
memory_write8 (cpu, addr, val);
cpu->cpu_regs.sp = addr - 1;
}
STATIC_INLINE UNUSED void
-cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16 val)
+cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16_t val)
{
- uint16 addr = cpu->cpu_regs.sp - 1;
+ uint16_t addr = cpu->cpu_regs.sp - 1;
memory_write16 (cpu, addr, val);
cpu->cpu_regs.sp = addr - 1;
}
-STATIC_INLINE UNUSED uint8
+STATIC_INLINE UNUSED uint8_t
cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.sp;
- uint8 val;
+ uint16_t addr = cpu->cpu_regs.sp;
+ uint8_t val;
val = memory_read8 (cpu, addr + 1);
cpu->cpu_regs.sp = addr + 1;
return val;
}
-STATIC_INLINE UNUSED uint16
+STATIC_INLINE UNUSED uint16_t
cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.sp;
- uint16 val;
+ uint16_t addr = cpu->cpu_regs.sp;
+ uint16_t val;
val = memory_read16 (cpu, addr + 1);
cpu->cpu_regs.sp = addr + 2;
@@ -458,9 +450,9 @@ cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
/* Push and pop instructions for 68HC12 (last-used stack mode). */
STATIC_INLINE UNUSED void
-cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8 val)
+cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8_t val)
{
- uint16 addr = cpu->cpu_regs.sp;
+ uint16_t addr = cpu->cpu_regs.sp;
addr --;
memory_write8 (cpu, addr, val);
@@ -468,31 +460,31 @@ cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8 val)
}
STATIC_INLINE UNUSED void
-cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16 val)
+cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16_t val)
{
- uint16 addr = cpu->cpu_regs.sp;
+ uint16_t addr = cpu->cpu_regs.sp;
addr -= 2;
memory_write16 (cpu, addr, val);
cpu->cpu_regs.sp = addr;
}
-STATIC_INLINE UNUSED uint8
+STATIC_INLINE UNUSED uint8_t
cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.sp;
- uint8 val;
+ uint16_t addr = cpu->cpu_regs.sp;
+ uint8_t val;
val = memory_read8 (cpu, addr);
cpu->cpu_regs.sp = addr + 1;
return val;
}
-STATIC_INLINE UNUSED uint16
+STATIC_INLINE UNUSED uint16_t
cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.sp;
- uint16 val;
+ uint16_t addr = cpu->cpu_regs.sp;
+ uint16_t val;
val = memory_read16 (cpu, addr);
cpu->cpu_regs.sp = addr + 2;
@@ -500,37 +492,37 @@ cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
}
/* Fetch a 8/16 bit value and update the PC. */
-STATIC_INLINE UNUSED uint8
+STATIC_INLINE UNUSED uint8_t
cpu_fetch8 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.pc;
- uint8 val;
+ uint16_t addr = cpu->cpu_regs.pc;
+ uint8_t val;
val = memory_read8 (cpu, addr);
cpu->cpu_regs.pc = addr + 1;
return val;
}
-STATIC_INLINE UNUSED uint16
+STATIC_INLINE UNUSED uint16_t
cpu_fetch16 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.pc;
- uint16 val;
+ uint16_t addr = cpu->cpu_regs.pc;
+ uint16_t val;
val = memory_read16 (cpu, addr);
cpu->cpu_regs.pc = addr + 2;
return val;
}
-extern void cpu_call (sim_cpu *cpu, uint16 addr);
-extern void cpu_exg (sim_cpu *cpu, uint8 code);
+extern void cpu_call (sim_cpu *cpu, uint16_t addr);
+extern void cpu_exg (sim_cpu *cpu, uint8_t code);
extern void cpu_dbcc (sim_cpu *cpu);
extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
-extern void cpu_move8 (sim_cpu *cpu, uint8 op);
-extern void cpu_move16 (sim_cpu *cpu, uint8 op);
+extern void cpu_move8 (sim_cpu *cpu, uint8_t op);
+extern void cpu_move16 (sim_cpu *cpu, uint8_t op);
-extern uint16 cpu_fetch_relbranch (sim_cpu *cpu);
-extern uint16 cpu_fetch_relbranch16 (sim_cpu *cpu);
+extern uint16_t cpu_fetch_relbranch (sim_cpu *cpu);
+extern uint16_t cpu_fetch_relbranch16 (sim_cpu *cpu);
extern void cpu_push_all (sim_cpu *cpu);
extern void cpu_single_step (sim_cpu *cpu);
@@ -540,30 +532,30 @@ extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
/* Returns the address of a 68HC12 indexed operand.
Pre and post modifications are handled on the source register. */
-extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
+extern uint16_t cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
extern void cpu_return (sim_cpu *cpu);
-extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
+extern void cpu_set_sp (sim_cpu *cpu, uint16_t val);
extern int cpu_reset (sim_cpu *cpu);
extern int cpu_restart (sim_cpu *cpu);
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
- uint16 addr, const char *message, ...);
+ uint16_t addr, const char *message, ...);
extern void emul_os (int op, sim_cpu *cpu);
extern void cpu_interp_m6811 (sim_cpu *cpu);
extern void cpu_interp_m6812 (sim_cpu *cpu);
extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
double ton, double toff,
- signed64 repeat);
+ int64_t repeat);
extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
- unsigned addr, uint8 val);
+ unsigned addr, uint8_t val);
extern void sim_board_reset (SIM_DESC sd);
#define PRINT_TIME 0x01
#define PRINT_CYCLE 0x02
-extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);
+extern const char *cycle_to_string (sim_cpu *cpu, int64_t t, int flags);
#endif
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 04/17] sim: v850: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
2022-01-01 20:55 ` [PATCH 02/17] sim: d10v: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 03/17] sim: m68hc11: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 05/17] sim: mn10300: " Mike Frysinger
` (12 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.
---
sim/v850/interp.c | 6 +--
sim/v850/sim-main.h | 44 ++++++++----------
sim/v850/simops.c | 52 ++++++++++-----------
sim/v850/simops.h | 4 +-
sim/v850/v850.igen | 110 ++++++++++++++++++++++----------------------
5 files changed, 105 insertions(+), 111 deletions(-)
diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index f450679aaf22..88191481a86a 100644
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -170,7 +170,7 @@ get_insn_name (sim_cpu *cpu, int i)
/* These default values correspond to expected usage for the chip. */
-uint32 OP[4];
+uint32_t OP[4];
static sim_cia
v850_pc_get (sim_cpu *cpu)
@@ -315,13 +315,13 @@ sim_create_inferior (SIM_DESC sd,
static int
v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- *(unsigned32*)memory = H2T_4 (State.regs[rn]);
+ *(uint32_t*)memory = H2T_4 (State.regs[rn]);
return -1;
}
static int
v850_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- State.regs[rn] = T2H_4 (*(unsigned32 *) memory);
+ State.regs[rn] = T2H_4 (*(uint32_t *) memory);
return length;
}
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index 792af5602199..49b845dfe7ae 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -14,14 +14,8 @@
#include "bfd.h"
-typedef signed8 int8;
-typedef unsigned8 uint8;
-typedef signed16 int16;
-typedef unsigned16 uint16;
-typedef signed32 int32;
-typedef unsigned32 uint32;
-typedef unsigned32 reg_t;
-typedef unsigned64 reg64_t;
+typedef uint32_t reg_t;
+typedef uint64_t reg64_t;
/* The current state of the processor; registers, memory, etc. */
@@ -62,7 +56,7 @@ extern SIM_DESC simulator;
macro's that store the instruction where the old simops expects
it. */
-extern uint32 OP[4];
+extern uint32_t OP[4];
#if 0
OP[0] = inst & 0x1f; /* RRRRR -> reg1 */
OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */
@@ -444,11 +438,11 @@ enum op_types
#ifdef DEBUG
void trace_input (char *name, enum op_types type, int size);
void trace_output (enum op_types result);
-void trace_result (int has_result, unsigned32 result);
+void trace_result (int has_result, uint32_t result);
extern int trace_num_values;
-extern unsigned32 trace_values[];
-extern unsigned32 trace_pc;
+extern uint32_t trace_values[];
+extern uint32_t trace_pc;
extern const char *trace_name;
extern int trace_module;
@@ -542,7 +536,7 @@ do { \
do { \
if (TRACE_FPU_P (CPU)) \
{ \
- unsigned64 f0; \
+ uint64_t f0; \
sim_fpu_to64 (&f0, (V0)); \
trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
} \
@@ -552,7 +546,7 @@ do { \
do { \
if (TRACE_FPU_P (CPU)) \
{ \
- unsigned64 f0, f1; \
+ uint64_t f0, f1; \
sim_fpu_to64 (&f0, (V0)); \
sim_fpu_to64 (&f1, (V1)); \
trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
@@ -563,7 +557,7 @@ do { \
do { \
if (TRACE_FPU_P (CPU)) \
{ \
- unsigned64 f0, f1, f2; \
+ uint64_t f0, f1, f2; \
sim_fpu_to64 (&f0, (V0)); \
sim_fpu_to64 (&f1, (V1)); \
sim_fpu_to64 (&f2, (V2)); \
@@ -576,7 +570,7 @@ do { \
if (TRACE_FPU_P (CPU)) \
{ \
int d0 = (V0); \
- unsigned64 f1, f2; \
+ uint64_t f1, f2; \
TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
TRACE_IDX (data) = TRACE_FPU_IDX; \
sim_fpu_to64 (&f1, (V1)); \
@@ -597,7 +591,7 @@ do { \
do { \
if (TRACE_FPU_P (CPU)) \
{ \
- unsigned64 f0; \
+ uint64_t f0; \
sim_fpu_to64 (&f0, (R0)); \
trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
} \
@@ -639,15 +633,15 @@ do { \
extern void divun ( unsigned int N,
unsigned long int als,
unsigned long int sfi,
- unsigned32 /*unsigned long int*/ * quotient_ptr,
- unsigned32 /*unsigned long int*/ * remainder_ptr,
+ uint32_t /*unsigned long int*/ * quotient_ptr,
+ uint32_t /*unsigned long int*/ * remainder_ptr,
int *overflow_ptr
);
extern void divn ( unsigned int N,
unsigned long int als,
unsigned long int sfi,
- signed32 /*signed long int*/ * quotient_ptr,
- signed32 /*signed long int*/ * remainder_ptr,
+ int32_t /*signed long int*/ * quotient_ptr,
+ int32_t /*signed long int*/ * remainder_ptr,
int *overflow_ptr
);
extern int type1_regs[];
@@ -667,7 +661,7 @@ extern int type3_regs[];
#define SAT16(X) \
do \
{ \
- signed64 z = (X); \
+ int64_t z = (X); \
if (z > 0x7fff) \
{ \
SESR |= SESR_OV | SESR_SOV; \
@@ -685,7 +679,7 @@ extern int type3_regs[];
#define SAT32(X) \
do \
{ \
- signed64 z = (X); \
+ int64_t z = (X); \
if (z > 0x7fffffff) \
{ \
SESR |= SESR_OV | SESR_SOV; \
@@ -703,7 +697,7 @@ extern int type3_regs[];
#define ABS16(X) \
do \
{ \
- signed64 z = (X) & 0xffff; \
+ int64_t z = (X) & 0xffff; \
if (z == 0x8000) \
{ \
SESR |= SESR_OV | SESR_SOV; \
@@ -720,7 +714,7 @@ extern int type3_regs[];
#define ABS32(X) \
do \
{ \
- signed64 z = (X) & 0xffffffff; \
+ int64_t z = (X) & 0xffffffff; \
if (z == 0x80000000) \
{ \
SESR |= SESR_OV | SESR_SOV; \
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 1178721a9759..8fac8bd98911 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -49,9 +49,9 @@ int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
#endif
-unsigned32 trace_values[3];
+uint32_t trace_values[3];
int trace_num_values;
-unsigned32 trace_pc;
+uint32_t trace_pc;
const char * trace_name;
int trace_module;
@@ -190,7 +190,7 @@ trace_input (char *name, enum op_types type, int size)
}
void
-trace_result (int has_result, unsigned32 result)
+trace_result (int has_result, uint32_t result)
{
char buf[1000];
char *chp;
@@ -415,7 +415,7 @@ fetch_argv (SIM_DESC sd, address_word addr)
while (1)
{
- unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
+ uint32_t a = sim_core_read_4 (STATE_CPU (sd, 0),
PC, read_map, addr + nr * 4);
if (a == 0) break;
buf[nr] = fetch_str (sd, a);
@@ -1669,7 +1669,7 @@ OP_10007E0 (void)
buf = PARM1;
RETVAL = pipe (host_fd);
SW (buf, host_fd[0]);
- buf += sizeof (uint16);
+ buf += sizeof (uint16_t);
SW (buf, host_fd[1]);
RETERR = errno;
}
@@ -2017,8 +2017,8 @@ divun
unsigned int N,
unsigned long int als,
unsigned long int sfi,
- unsigned32 /*unsigned long int*/ * quotient_ptr,
- unsigned32 /*unsigned long int*/ * remainder_ptr,
+ uint32_t /*unsigned long int*/ * quotient_ptr,
+ uint32_t /*unsigned long int*/ * remainder_ptr,
int * overflow_ptr
)
{
@@ -2091,8 +2091,8 @@ divn
unsigned int N,
unsigned long int als,
unsigned long int sfi,
- signed32 /*signed long int*/ * quotient_ptr,
- signed32 /*signed long int*/ * remainder_ptr,
+ int32_t /*signed long int*/ * quotient_ptr,
+ int32_t /*signed long int*/ * remainder_ptr,
int * overflow_ptr
)
{
@@ -2188,8 +2188,8 @@ divn
int
OP_1C207E0 (void)
{
- unsigned32 /*unsigned long int*/ quotient;
- unsigned32 /*unsigned long int*/ remainder;
+ uint32_t /*unsigned long int*/ quotient;
+ uint32_t /*unsigned long int*/ remainder;
unsigned long int divide_by;
unsigned long int divide_this;
int overflow = 0;
@@ -2223,8 +2223,8 @@ OP_1C207E0 (void)
int
OP_1C007E0 (void)
{
- signed32 /*signed long int*/ quotient;
- signed32 /*signed long int*/ remainder;
+ int32_t /*signed long int*/ quotient;
+ int32_t /*signed long int*/ remainder;
signed long int divide_by;
signed long int divide_this;
int overflow = 0;
@@ -2234,8 +2234,8 @@ OP_1C007E0 (void)
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
- divide_by = (signed32) State.regs[ OP[0] ];
- divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
+ divide_by = (int32_t) State.regs[ OP[0] ];
+ divide_this = (int32_t) (State.regs[ OP[1] ] << imm5);
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
@@ -2258,8 +2258,8 @@ OP_1C007E0 (void)
int
OP_18207E0 (void)
{
- unsigned32 /*unsigned long int*/ quotient;
- unsigned32 /*unsigned long int*/ remainder;
+ uint32_t /*unsigned long int*/ quotient;
+ uint32_t /*unsigned long int*/ remainder;
unsigned long int divide_by;
unsigned long int divide_this;
int overflow = 0;
@@ -2293,8 +2293,8 @@ OP_18207E0 (void)
int
OP_18007E0 (void)
{
- signed32 /*signed long int*/ quotient;
- signed32 /*signed long int*/ remainder;
+ int32_t /*signed long int*/ quotient;
+ int32_t /*signed long int*/ remainder;
signed long int divide_by;
signed long int divide_this;
int overflow = 0;
@@ -2305,7 +2305,7 @@ OP_18007E0 (void)
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
divide_by = EXTEND16 (State.regs[ OP[0] ]);
- divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
+ divide_this = (int32_t) (State.regs[ OP[1] ] << imm5);
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
@@ -2376,7 +2376,7 @@ OP_2C007E0 (void)
/* Compute the result. */
- divide_by = (signed32) State.regs[ OP[0] ];
+ divide_by = (int32_t) State.regs[ OP[0] ];
divide_this = State.regs[ OP[1] ];
if (divide_by == 0)
@@ -2392,7 +2392,7 @@ OP_2C007E0 (void)
}
else
{
- divide_this = (signed32) divide_this;
+ divide_this = (int32_t) divide_this;
State.regs[ OP[1] ] = quotient = divide_this / divide_by;
State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
@@ -2477,7 +2477,7 @@ OP_28007E0 (void)
}
else
{
- divide_this = (signed32) divide_this;
+ divide_this = (int32_t) divide_this;
State.regs[ OP[1] ] = quotient = divide_this / divide_by;
State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
@@ -3378,12 +3378,12 @@ v850_satsub (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p
*op2p = result;
}
-unsigned32
+uint32_t
load_data_mem (SIM_DESC sd,
SIM_ADDR addr,
int len)
{
- uint32 data;
+ uint32_t data;
switch (len)
{
@@ -3409,7 +3409,7 @@ void
store_data_mem (SIM_DESC sd,
SIM_ADDR addr,
int len,
- unsigned32 data)
+ uint32_t data)
{
switch (len)
{
diff --git a/sim/v850/simops.h b/sim/v850/simops.h
index 1b6b4072f082..632febe5de55 100644
--- a/sim/v850/simops.h
+++ b/sim/v850/simops.h
@@ -79,8 +79,8 @@ int OP_307E0 (void);
int v850_float_compare(SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p);
/* MEMORY ACCESS */
-unsigned32 load_data_mem(SIM_DESC sd, SIM_ADDR addr, int len);
-void store_data_mem(SIM_DESC sd, SIM_ADDR addr, int len, unsigned32 data);
+uint32_t load_data_mem(SIM_DESC sd, SIM_ADDR addr, int len);
+void store_data_mem(SIM_DESC sd, SIM_ADDR addr, int len, uint32_t data);
unsigned long Add32 (unsigned long a1, unsigned long a2, int * carry);
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index 41a9075a8e79..eb32c0f5ec33 100644
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -220,7 +220,7 @@ rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
*v850e3v5
"bsh r<reg2>, r<reg3>"
{
- unsigned32 value;
+ uint32_t value;
TRACE_ALU_INPUT1 (GR[reg2]);
value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
@@ -249,7 +249,7 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
"bsw r<reg2>, r<reg3>"
{
#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
- unsigned32 value;
+ uint32_t value;
TRACE_ALU_INPUT1 (GR[reg2]);
value = GR[reg2];
@@ -279,8 +279,8 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
*v850e3v5
"callt <imm6>"
{
- unsigned32 adr;
- unsigned32 off;
+ uint32_t adr;
+ uint32_t off;
CTPC = cia + 2;
CTPSW = PSW;
adr = (CTBP & ~1) + (imm6 << 1);
@@ -299,8 +299,8 @@ rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi
"caxi [reg1], reg2, reg3"
{
unsigned int z,s,cy,ov;
- unsigned32 addr;
- unsigned32 token,result;
+ uint32_t addr;
+ uint32_t token,result;
addr = GR[reg1];
@@ -486,7 +486,7 @@ rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
rrrrr!0,000010,RRRRR!0:I:::divh
"divh r<reg1>, r<reg2>"
{
- unsigned32 ov, s, z;
+ uint32_t ov, s, z;
signed long int op0, op1, result;
trace_input ("divh", OP_REG_REG, 0);
@@ -511,7 +511,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh
}
else
{
- result = (signed32) op1 / op0;
+ result = (int32_t) op1 / op0;
ov = 0;
/* Compute the condition codes. */
@@ -714,7 +714,7 @@ rrrrr,11111100000 + wwwww,01101000110:XII:::hsh
*v850e3v5
"hsh r<reg2>, r<reg3>"
{
- unsigned32 value;
+ uint32_t value;
TRACE_ALU_INPUT1 (GR[reg2]);
value = 0xffff & GR[reg2];
@@ -738,7 +738,7 @@ rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
*v850e3v5
"hsw r<reg2>, r<reg3>"
{
- unsigned32 value;
+ uint32_t value;
TRACE_ALU_INPUT1 (GR[reg2]);
value = GR[reg2];
@@ -844,8 +844,8 @@ rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
*v850e2v3
*v850e3v5
{
- unsigned32 addr = GR[reg1] + disp23;
- unsigned32 result = EXTEND8 (load_data_mem (sd, addr, 1));
+ uint32_t addr = GR[reg1] + disp23;
+ uint32_t result = EXTEND8 (load_data_mem (sd, addr, 1));
GR[reg3] = result;
TRACE_LD (addr, result);
}
@@ -861,8 +861,8 @@ rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
*v850e3v5
"ld.h <disp23>[r<reg1>], r<reg3>"
{
- unsigned32 addr = GR[reg1] + disp23;
- unsigned32 result = EXTEND16 (load_data_mem (sd, addr, 2));
+ uint32_t addr = GR[reg1] + disp23;
+ uint32_t result = EXTEND16 (load_data_mem (sd, addr, 2));
GR[reg3] = result;
TRACE_LD (addr, result);
}
@@ -878,8 +878,8 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
*v850e3v5
"ld.w <disp23>[r<reg1>], r<reg3>"
{
- unsigned32 addr = GR[reg1] + disp23;
- unsigned32 result = load_data_mem (sd, addr, 4);
+ uint32_t addr = GR[reg1] + disp23;
+ uint32_t result = load_data_mem (sd, addr, 4);
GR[reg3] = result;
TRACE_LD (addr, result);
}
@@ -888,8 +888,8 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
*v850e3v5
"ld.dw <disp23>[r<reg1>], r<reg3>"
{
- unsigned32 addr = GR[reg1] + disp23;
- unsigned32 result = load_data_mem (sd, addr, 4);
+ uint32_t addr = GR[reg1] + disp23;
+ uint32_t result = load_data_mem (sd, addr, 4);
GR[reg3] = result;
TRACE_LD (addr, result);
result = load_data_mem (sd, addr + 4, 4);
@@ -913,8 +913,8 @@ rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
*v850e3v5
"ld.bu <disp23>[r<reg1>], r<reg3>"
{
- unsigned32 addr = GR[reg1] + disp23;
- unsigned32 result = load_data_mem (sd, addr, 1);
+ uint32_t addr = GR[reg1] + disp23;
+ uint32_t result = load_data_mem (sd, addr, 1);
GR[reg3] = result;
TRACE_LD (addr, result);
}
@@ -935,8 +935,8 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
*v850e3v5
"ld.hu <disp23>[r<reg1>], r<reg3>"
{
- unsigned32 addr = GR[reg1] + disp23;
- unsigned32 result = load_data_mem (sd, addr, 2);
+ uint32_t addr = GR[reg1] + disp23;
+ uint32_t result = load_data_mem (sd, addr, 2);
GR[reg3] = result;
TRACE_LD (addr, result);
}
@@ -948,7 +948,7 @@ regID,111111,RRRRR + selID,00000100000:IX:::ldsr
"ldsr r<reg1>, s<regID>":(selID == 0)
"ldsr r<reg1>, s<regID>, <selID>"
{
- uint32 sreg = GR[reg1];
+ uint32_t sreg = GR[reg1];
TRACE_ALU_INPUT1 (GR[reg1]);
/* FIXME: For now we ignore the selID. */
@@ -1911,8 +1911,8 @@ rrrrr,0110,ddddddd:IV:::sld.b
"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
"sld.b <disp7>[ep], r<reg2>"
{
- unsigned32 addr = EP + disp7;
- unsigned32 result = load_mem (addr, 1);
+ uint32_t addr = EP + disp7;
+ uint32_t result = load_mem (addr, 1);
if (PSW & PSW_US)
{
GR[reg2] = result;
@@ -1930,8 +1930,8 @@ rrrrr,1000,ddddddd:IV:::sld.h
"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
"sld.h <disp8>[ep], r<reg2>"
{
- unsigned32 addr = EP + disp8;
- unsigned32 result = load_mem (addr, 2);
+ uint32_t addr = EP + disp8;
+ uint32_t result = load_mem (addr, 2);
if (PSW & PSW_US)
{
GR[reg2] = result;
@@ -1948,8 +1948,8 @@ rrrrr,1000,ddddddd:IV:::sld.h
rrrrr,1010,dddddd,0:IV:::sld.w
"sld.w <disp8>[ep], r<reg2>"
{
- unsigned32 addr = EP + disp8;
- unsigned32 result = load_mem (addr, 4);
+ uint32_t addr = EP + disp8;
+ uint32_t result = load_mem (addr, 4);
GR[reg2] = result;
TRACE_LD (addr, result);
}
@@ -1963,8 +1963,8 @@ rrrrr!0,0000110,dddd:IV:::sld.bu
"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
"sld.bu <disp4>[ep], r<reg2>"
{
- unsigned32 addr = EP + disp4;
- unsigned32 result = load_mem (addr, 1);
+ uint32_t addr = EP + disp4;
+ uint32_t result = load_mem (addr, 1);
if (PSW & PSW_US)
{
result = EXTEND8 (result);
@@ -1987,8 +1987,8 @@ rrrrr!0,0000111,dddd:IV:::sld.hu
"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
"sld.hu <disp5>[ep], r<reg2>"
{
- unsigned32 addr = EP + disp5;
- unsigned32 result = load_mem (addr, 2);
+ uint32_t addr = EP + disp5;
+ uint32_t result = load_mem (addr, 2);
if (PSW & PSW_US)
{
result = EXTEND16 (result);
@@ -2035,7 +2035,7 @@ rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
*v850e3v5
"st.b r<reg3>, <disp23>[r<reg1>]"
{
- unsigned32 addr = GR[reg1] + disp23;
+ uint32_t addr = GR[reg1] + disp23;
store_data_mem (sd, addr, 1, GR[reg3]);
TRACE_ST (addr, GR[reg3]);
}
@@ -2051,7 +2051,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
*v850e3v5
"st.h r<reg3>, <disp23>[r<reg1>]"
{
- unsigned32 addr = GR[reg1] + disp23;
+ uint32_t addr = GR[reg1] + disp23;
store_data_mem (sd, addr, 2, GR[reg3]);
TRACE_ST (addr, GR[reg3]);
}
@@ -2067,7 +2067,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
*v850e3v5
"st.w r<reg3>, <disp23>[r<reg1>]"
{
- unsigned32 addr = GR[reg1] + disp23;
+ uint32_t addr = GR[reg1] + disp23;
store_data_mem (sd, addr, 4, GR[reg3]);
TRACE_ST (addr, GR[reg3]);
}
@@ -2076,7 +2076,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
*v850e3v5
"st.dw r<reg3>, <disp23>[r<reg1>]"
{
- unsigned32 addr = GR[reg1] + disp23;
+ uint32_t addr = GR[reg1] + disp23;
store_data_mem (sd, addr, 4, GR[reg3]);
TRACE_ST (addr, GR[reg3]);
store_data_mem (sd, addr + 4, 4, GR[reg3 + 1]);
@@ -2088,7 +2088,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
rrrrr,111111,regID + 0000000001000000:IX:::stsr
"stsr s<regID>, r<reg2>"
{
- uint32 sreg = 0;
+ uint32_t sreg = 0;
if ((idecode_issue == idecode_v850e2_issue
|| idecode_issue == idecode_v850e3v5_issue
@@ -2561,7 +2561,7 @@ rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl
*v850e3v5
"cvtf.dl r<reg2e>, r<reg3e>"
{
- signed64 ans;
+ int64_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -2604,7 +2604,7 @@ rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw
*v850e3v5
"cvtf.dw r<reg2e>, r<reg3>"
{
- int32 ans;
+ int32_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -2626,11 +2626,11 @@ rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld
*v850e3v5
"cvtf.ld r<reg2e>, r<reg3e>"
{
- signed64 op;
+ int64_t op;
sim_fpu wop;
sim_fpu_status status;
- op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e];
+ op = ((int64_t)GR[reg2e+1] << 32L) | GR[reg2e];
TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]);
sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
@@ -2648,11 +2648,11 @@ rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls
*v850e3v5
"cvtf.ls r<reg2e>, r<reg3>"
{
- signed64 op;
+ int64_t op;
sim_fpu wop;
sim_fpu_status status;
- op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e];
+ op = ((int64_t)GR[reg2e+1] << 32L) | GR[reg2e];
TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]);
sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
@@ -2689,7 +2689,7 @@ rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl
*v850e3v5
"cvtf.sl r<reg2>, r<reg3e>"
{
- signed64 ans;
+ int64_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -2712,7 +2712,7 @@ rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw
*v850e3v5
"cvtf.sw r<reg2>, r<reg3>"
{
- int32 ans;
+ int32_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -3449,7 +3449,7 @@ rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl
*v850e3v5
"trncf.dl r<reg2e>, r<reg3e>"
{
- signed64 ans;
+ int64_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -3471,7 +3471,7 @@ rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul
*v850e3v5
"trncf.dul r<reg2e>, r<reg3e>"
{
- unsigned64 ans;
+ uint64_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -3493,7 +3493,7 @@ rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
*v850e3v5
"trncf.dw r<reg2e>, r<reg3>"
{
- int32 ans;
+ int32_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -3514,7 +3514,7 @@ rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw
*v850e3v5
"trncf.duw r<reg2e>, r<reg3>"
{
- uint32 ans;
+ uint32_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -3535,7 +3535,7 @@ rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl
*v850e3v5
"trncf.sl r<reg2>, r<reg3e>"
{
- signed64 ans;
+ int64_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -3555,7 +3555,7 @@ rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul
*v850e3v5
"trncf.sul r<reg2>, r<reg3e>"
{
- unsigned64 ans;
+ uint64_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -3575,7 +3575,7 @@ rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
*v850e3v5
"trncf.sw r<reg2>, r<reg3>"
{
- int32 ans;
+ int32_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -3596,7 +3596,7 @@ rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw
*v850e3v5
"trncf.suw r<reg2>, r<reg3>"
{
- uint32 ans;
+ uint32_t ans;
sim_fpu wop;
sim_fpu_status status;
@@ -3808,7 +3808,7 @@ rrrr,011111100000+0000011011011000:C:::modadd
"modadd r<reg2e>"
{
reg_t r;
- int32 inc;
+ int32_t inc;
reg_t max;
TRACE_ALU_INPUT1 (GR[reg2e]);
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 05/17] sim: mn10300: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (2 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 04/17] sim: v850: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 06/17] sim: erc32: " Mike Frysinger
` (11 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.
---
sim/mn10300/am33-2.igen | 18 +-
sim/mn10300/am33.igen | 580 +++++++++++++++++++-------------------
sim/mn10300/dv-mn103cpu.c | 14 +-
sim/mn10300/dv-mn103int.c | 20 +-
sim/mn10300/dv-mn103iop.c | 24 +-
sim/mn10300/dv-mn103ser.c | 42 +--
sim/mn10300/dv-mn103tim.c | 94 +++---
sim/mn10300/interp.c | 6 +-
sim/mn10300/mn10300.igen | 152 +++++-----
sim/mn10300/mn10300_sim.h | 33 +--
sim/mn10300/op_utils.c | 20 +-
11 files changed, 498 insertions(+), 505 deletions(-)
diff --git a/sim/mn10300/am33-2.igen b/sim/mn10300/am33-2.igen
index bcf68b46e2b7..40761b2a19d9 100644
--- a/sim/mn10300/am33-2.igen
+++ b/sim/mn10300/am33-2.igen
@@ -98,7 +98,7 @@
"bset"
*am33_2
{
- unsigned32 temp;
+ uint32_t temp;
int z;
PC = cia;
@@ -115,7 +115,7 @@
"bclr"
*am33_2
{
- unsigned32 temp;
+ uint32_t temp;
int z;
PC = cia;
@@ -1114,7 +1114,7 @@
else
{
int reg = translate_rreg (SD_, Rm);
- unsigned32 val = State.regs[reg];
+ uint32_t val = State.regs[reg];
FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
| ((FPCR & ~val) & EF_MASK);
}
@@ -1147,7 +1147,7 @@
fpu_disabled_exception (SD, CPU, cia);
else
{
- unsigned32 val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ uint32_t val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
| ((FPCR & ~val) & EF_MASK);
}
@@ -1424,7 +1424,7 @@
fpu_disabled_exception (SD, CPU, cia);
else
{
- uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE);
}
@@ -1496,7 +1496,7 @@
fpu_disabled_exception (SD, CPU, cia);
else
{
- uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
fpu_add (SD, CPU, cia,
&XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
@@ -1569,7 +1569,7 @@
fpu_disabled_exception (SD, CPU, cia);
else
{
- uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
fpu_sub (SD, CPU, cia,
&XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
@@ -1642,7 +1642,7 @@
fpu_disabled_exception (SD, CPU, cia);
else
{
- uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
fpu_mul (SD, CPU, cia,
&imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
@@ -1715,7 +1715,7 @@
fpu_disabled_exception (SD, CPU, cia);
else
{
- uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
fpu_div (SD, CPU, cia,
&XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen
index 5bc96aca6164..964f07521a8c 100644
--- a/sim/mn10300/am33.igen
+++ b/sim/mn10300/am33.igen
@@ -119,7 +119,7 @@
*am33
*am33_2
{
- unsigned32 sp, next_pc;
+ uint32_t sp, next_pc;
PC = cia;
sp = State.regs[REG_SP];
@@ -207,8 +207,8 @@
*am33
*am33_2
{
- unsigned32 usp = State.regs[REG_USP];
- unsigned32 mask;
+ uint32_t usp = State.regs[REG_USP];
+ uint32_t mask;
PC = cia;
mask = REGS;
@@ -301,8 +301,8 @@
*am33
*am33_2
{
- unsigned32 usp = State.regs[REG_USP];
- unsigned32 mask;
+ uint32_t usp = State.regs[REG_USP];
+ uint32_t mask;
PC = cia;
mask = REGS;
@@ -533,7 +533,7 @@
{
int srcreg, dstreg;
int z, c, n, v;
- unsigned32 reg1, reg2, sum;
+ uint32_t reg1, reg2, sum;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
@@ -577,7 +577,7 @@
{
int srcreg, dstreg;
int z, c, n, v;
- unsigned32 reg1, reg2, difference;
+ uint32_t reg1, reg2, difference;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
@@ -756,7 +756,7 @@
*am33_2
{
int srcreg, dstreg;
- signed32 temp;
+ int32_t temp;
int c, z, n;
PC = cia;
@@ -842,7 +842,7 @@
{
int dstreg;
int c, n, z;
- unsigned32 value;
+ uint32_t value;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
@@ -867,7 +867,7 @@
{
int dstreg;
int c, n, z;
- unsigned32 value;
+ uint32_t value;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
@@ -891,15 +891,15 @@
*am33_2
{
int srcreg, dstreg;
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
dstreg = translate_rreg (SD_, RN0);
- temp = ((signed64)(signed32)State.regs[dstreg]
- * (signed64)(signed32)State.regs[srcreg]);
+ temp = ((int64_t)(int32_t)State.regs[dstreg]
+ * (int64_t)(int32_t)State.regs[srcreg]);
State.regs[dstreg] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[dstreg] == 0);
@@ -915,15 +915,15 @@
*am33_2
{
int srcreg, dstreg;
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
dstreg = translate_rreg (SD_, RN0);
- temp = ((unsigned64)State.regs[dstreg]
- * (unsigned64)State.regs[srcreg]);
+ temp = ((uint64_t)State.regs[dstreg]
+ * (uint64_t)State.regs[srcreg]);
State.regs[dstreg] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[dstreg] == 0);
@@ -939,7 +939,7 @@
*am33_2
{
int srcreg, dstreg;
- signed64 temp;
+ int64_t temp;
int n, z;
PC = cia;
@@ -949,8 +949,8 @@
temp = State.regs[REG_MDR];
temp <<= 32;
temp |= State.regs[dstreg];
- State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
- temp /= (signed32)State.regs[srcreg];
+ State.regs[REG_MDR] = temp % (int32_t)State.regs[srcreg];
+ temp /= (int32_t)State.regs[srcreg];
State.regs[dstreg] = temp & 0xffffffff;
z = (State.regs[dstreg] == 0);
n = (State.regs[dstreg] & 0x80000000) != 0;
@@ -965,7 +965,7 @@
*am33_2
{
int srcreg, dstreg;
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
@@ -1215,15 +1215,15 @@
*am33_2
{
int srcreg1, srcreg2;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
srcreg2 = translate_rreg (SD_, RN0);
- temp = ((signed64)(signed32)State.regs[srcreg2]
- * (signed64)(signed32)State.regs[srcreg1]);
+ temp = ((int64_t)(int32_t)State.regs[srcreg2]
+ * (int64_t)(int32_t)State.regs[srcreg1]);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -1244,15 +1244,15 @@
*am33_2
{
int srcreg1, srcreg2;
- unsigned64 temp, sum;
+ uint64_t temp, sum;
int c, v;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
srcreg2 = translate_rreg (SD_, RN0);
- temp = ((unsigned64)State.regs[srcreg2]
- * (unsigned64)State.regs[srcreg1]);
+ temp = ((uint64_t)State.regs[srcreg2]
+ * (uint64_t)State.regs[srcreg1]);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -1273,15 +1273,15 @@
*am33_2
{
int srcreg1, srcreg2;
- signed32 temp, sum;
+ int32_t temp, sum;
int v;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
srcreg2 = translate_rreg (SD_, RN0);
- temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
- * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
+ temp = ((int32_t)(int8_t)(State.regs[srcreg2] & 0xff)
+ * (int32_t)(int8_t)(State.regs[srcreg1] & 0xff));
sum = State.regs[REG_MCRL] + temp;
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -1297,15 +1297,15 @@
*am33_2
{
int srcreg1, srcreg2;
- signed64 temp, sum;
+ int64_t temp, sum;
int v;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
srcreg2 = translate_rreg (SD_, RN0);
- temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
- * (unsigned32)(State.regs[srcreg1] & 0xff));
+ temp = ((uint32_t)(State.regs[srcreg2] & 0xff)
+ * (uint32_t)(State.regs[srcreg1] & 0xff));
sum = State.regs[REG_MCRL] + temp;
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -1321,15 +1321,15 @@
*am33_2
{
int srcreg1, srcreg2;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
srcreg2 = translate_rreg (SD_, RN0);
- temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
- * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp = ((uint64_t)(int16_t)(State.regs[srcreg2] & 0xffff)
+ * (uint64_t)(int16_t)(State.regs[srcreg1] & 0xffff));
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -1350,15 +1350,15 @@
*am33_2
{
int srcreg1, srcreg2;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
srcreg2 = translate_rreg (SD_, RN0);
- temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
- * (unsigned64)(State.regs[srcreg1] & 0xffff));
+ temp = ((uint64_t)(State.regs[srcreg2] & 0xffff)
+ * (uint64_t)(State.regs[srcreg1] & 0xffff));
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -1379,17 +1379,17 @@
*am33_2
{
int srcreg1, srcreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
int v;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
srcreg2 = translate_rreg (SD_, RN0);
- temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[srcreg2] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[srcreg2] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -1405,17 +1405,17 @@
*am33_2
{
int srcreg1, srcreg2;
- unsigned32 temp, temp2, sum;
+ uint32_t temp, temp2, sum;
int v;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
srcreg2 = translate_rreg (SD_, RN0);
- temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
- * (unsigned32)(State.regs[srcreg1] & 0xffff));
- temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
- * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
+ temp = ((uint32_t)(State.regs[srcreg2] & 0xffff)
+ * (uint32_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((uint32_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (uint32_t)((State.regs[srcreg2] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -1431,17 +1431,17 @@
*am33_2
{
int srcreg, dstreg;
- signed32 temp;
+ int32_t temp;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
dstreg = translate_rreg (SD_, RN0);
- temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg] & 0xffff));
State.regs[REG_MDRQ] = temp;
- temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
+ temp = ((int32_t)(int16_t)((State.regs[dstreg] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[srcreg] >>16) & 0xffff));
State.regs[dstreg] = temp;
}
@@ -1452,17 +1452,17 @@
*am33_2
{
int srcreg, dstreg;
- unsigned32 temp;
+ uint32_t temp;
PC = cia;
srcreg = translate_rreg (SD_, RM2);
dstreg = translate_rreg (SD_, RN0);
- temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
- * (unsigned32)(State.regs[srcreg] & 0xffff));
+ temp = ((uint32_t)(State.regs[dstreg] & 0xffff)
+ * (uint32_t)(State.regs[srcreg] & 0xffff));
State.regs[REG_MDRQ] = temp;
- temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
- * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
+ temp = ((uint32_t)((State.regs[dstreg] >> 16) & 0xffff)
+ * (uint32_t)((State.regs[srcreg] >>16) & 0xffff));
State.regs[dstreg] = temp;
}
@@ -1512,7 +1512,7 @@
/* 32bit saturation. */
if (State.regs[srcreg] == 0x20)
{
- signed64 tmp;
+ int64_t tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
@@ -1528,7 +1528,7 @@
/* 16bit saturation */
else if (State.regs[srcreg] == 0x10)
{
- signed64 tmp;
+ int64_t tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
@@ -1544,7 +1544,7 @@
/* 8 bit saturation */
else if (State.regs[srcreg] == 0x8)
{
- signed64 tmp;
+ int64_t tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
@@ -1560,7 +1560,7 @@
/* 9 bit saturation */
else if (State.regs[srcreg] == 0x9)
{
- signed64 tmp;
+ int64_t tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
@@ -1576,7 +1576,7 @@
/* 9 bit saturation */
else if (State.regs[srcreg] == 0x30)
{
- signed64 tmp;
+ int64_t tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
@@ -1731,7 +1731,7 @@
{
int dstreg, imm;
int z, c, n, v;
- unsigned32 reg2, sum;
+ uint32_t reg2, sum;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
@@ -1774,7 +1774,7 @@
{
int imm, dstreg;
int z, c, n, v;
- unsigned32 reg2, difference;
+ uint32_t reg2, difference;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
@@ -1886,7 +1886,7 @@
*am33_2
{
int dstreg;
- signed32 temp;
+ int32_t temp;
int c, z, n;
PC = cia;
@@ -1948,14 +1948,14 @@
*am33_2
{
int dstreg;
- unsigned64 temp;
+ uint64_t temp;
int z, n;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
- temp = ((signed64)(signed32)State.regs[dstreg]
- * (signed64)(signed32)EXTEND8 (IMM8));
+ temp = ((int64_t)(int32_t)State.regs[dstreg]
+ * (int64_t)(int32_t)EXTEND8 (IMM8));
State.regs[dstreg] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[dstreg] == 0);
@@ -1971,14 +1971,14 @@
*am33_2
{
int dstreg;
- unsigned64 temp;
+ uint64_t temp;
int z, n;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
- temp = ((unsigned64)State.regs[dstreg]
- * (unsigned64)(IMM8 & 0xff));
+ temp = ((uint64_t)State.regs[dstreg]
+ * (uint64_t)(IMM8 & 0xff));
State.regs[dstreg] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[dstreg] == 0);
@@ -2231,14 +2231,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((signed64)(signed32)EXTEND8 (IMM8)
- * (signed64)(signed32)State.regs[srcreg]);
+ temp = ((int64_t)(int32_t)EXTEND8 (IMM8)
+ * (int64_t)(int32_t)State.regs[srcreg]);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -2259,14 +2259,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((unsigned64) (IMM8)
- * (unsigned64)State.regs[srcreg]);
+ temp = ((uint64_t) (IMM8)
+ * (uint64_t)State.regs[srcreg]);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -2287,14 +2287,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((signed64)(signed8)EXTEND8 (IMM8)
- * (signed64)(signed8)State.regs[srcreg] & 0xff);
+ temp = ((int64_t)(int8_t)EXTEND8 (IMM8)
+ * (int64_t)(int8_t)State.regs[srcreg] & 0xff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -2315,14 +2315,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((unsigned64) (IMM8)
- * (unsigned64)State.regs[srcreg] & 0xff);
+ temp = ((uint64_t) (IMM8)
+ * (uint64_t)State.regs[srcreg] & 0xff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -2343,14 +2343,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((signed64)(signed16)EXTEND8 (IMM8)
- * (signed64)(signed16)State.regs[srcreg] & 0xffff);
+ temp = ((int64_t)(int16_t)EXTEND8 (IMM8)
+ * (int64_t)(int16_t)State.regs[srcreg] & 0xffff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -2371,14 +2371,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((unsigned64) (IMM8)
- * (unsigned64)State.regs[srcreg] & 0xffff);
+ temp = ((uint64_t) (IMM8)
+ * (uint64_t)State.regs[srcreg] & 0xffff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -2409,7 +2409,7 @@
/* 32bit saturation. */
if (IMM8 == 0x20)
{
- signed64 tmp;
+ int64_t tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
@@ -2425,7 +2425,7 @@
/* 16bit saturation */
else if (IMM8 == 0x10)
{
- signed64 tmp;
+ int64_t tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
@@ -2441,7 +2441,7 @@
/* 8 bit saturation */
else if (IMM8 == 0x8)
{
- signed64 tmp;
+ int64_t tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
@@ -2457,7 +2457,7 @@
/* 9 bit saturation */
else if (IMM8 == 0x9)
{
- signed64 tmp;
+ int64_t tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
@@ -2473,7 +2473,7 @@
/* 9 bit saturation */
else if (IMM8 == 0x30)
{
- signed64 tmp;
+ int64_t tmp;
tmp = State.regs[REG_MCRH];
tmp <<= 32;
@@ -2496,7 +2496,7 @@
*am33_2
{
int z, c, n, v;
- unsigned32 sum, source1, source2;
+ uint32_t sum, source1, source2;
int srcreg1, srcreg2, dstreg;
PC = cia;
@@ -2527,7 +2527,7 @@
*am33_2
{
int z, c, n, v;
- unsigned32 sum, source1, source2;
+ uint32_t sum, source1, source2;
int srcreg1, srcreg2, dstreg;
PC = cia;
@@ -2558,7 +2558,7 @@
*am33_2
{
int z, c, n, v;
- unsigned32 difference, source1, source2;
+ uint32_t difference, source1, source2;
int srcreg1, srcreg2, dstreg;
PC = cia;
@@ -2589,7 +2589,7 @@
*am33_2
{
int z, c, n, v;
- unsigned32 difference, source1, source2;
+ uint32_t difference, source1, source2;
int srcreg1, srcreg2, dstreg;
PC = cia;
@@ -2689,7 +2689,7 @@
*am33_2
{
int z, c, n;
- signed32 temp;
+ int32_t temp;
int srcreg1, srcreg2, dstreg;
PC = cia;
@@ -2763,7 +2763,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed64 temp;
+ int64_t temp;
int n, z;
PC = cia;
@@ -2772,8 +2772,8 @@
dstreg1 = translate_rreg (SD_, RD0);
dstreg2 = translate_rreg (SD_, RD2);
- temp = ((signed64)(signed32)State.regs[srcreg1]
- * (signed64)(signed32)State.regs[srcreg2]);
+ temp = ((int64_t)(int32_t)State.regs[srcreg1]
+ * (int64_t)(int32_t)State.regs[srcreg2]);
State.regs[dstreg2] = temp & 0xffffffff;
State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
@@ -2791,7 +2791,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed64 temp;
+ int64_t temp;
int n, z;
PC = cia;
@@ -2800,8 +2800,8 @@
dstreg1 = translate_rreg (SD_, RD0);
dstreg2 = translate_rreg (SD_, RD2);
- temp = ((unsigned64)State.regs[srcreg1]
- * (unsigned64)State.regs[srcreg2]);
+ temp = ((uint64_t)State.regs[srcreg1]
+ * (uint64_t)State.regs[srcreg2]);
State.regs[dstreg2] = temp & 0xffffffff;
State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
@@ -2987,8 +2987,8 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed64 temp;
- unsigned32 sum;
+ int64_t temp;
+ uint32_t sum;
int c, v;
PC = cia;
@@ -2997,8 +2997,8 @@
dstreg1 = translate_rreg (SD_, RD0);
dstreg2 = translate_rreg (SD_, RD2);
- temp = ((signed64)(signed32)State.regs[srcreg1]
- * (signed64)(signed32)State.regs[srcreg2]);
+ temp = ((int64_t)(int32_t)State.regs[srcreg1]
+ * (int64_t)(int32_t)State.regs[srcreg2]);
sum = State.regs[dstreg2] + (temp & 0xffffffff);
c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
@@ -3024,8 +3024,8 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed64 temp;
- unsigned32 sum;
+ int64_t temp;
+ uint32_t sum;
int c, v;
PC = cia;
@@ -3034,8 +3034,8 @@
dstreg1 = translate_rreg (SD_, RD0);
dstreg2 = translate_rreg (SD_, RD2);
- temp = ((unsigned64)State.regs[srcreg1]
- * (unsigned64)State.regs[srcreg2]);
+ temp = ((uint64_t)State.regs[srcreg1]
+ * (uint64_t)State.regs[srcreg2]);
sum = State.regs[dstreg2] + (temp & 0xffffffff);
c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
@@ -3061,7 +3061,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg;
- signed32 temp, sum;
+ int32_t temp, sum;
int v;
PC = cia;
@@ -3069,8 +3069,8 @@
srcreg2 = translate_rreg (SD_, RN0);
dstreg = translate_rreg (SD_, RD0);
- temp = ((signed32)(State.regs[srcreg2] & 0xff)
- * (signed32)(State.regs[srcreg1] & 0xff));
+ temp = ((int32_t)(State.regs[srcreg2] & 0xff)
+ * (int32_t)(State.regs[srcreg1] & 0xff));
sum = State.regs[dstreg] + temp;
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -3090,7 +3090,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg;
- signed32 temp, sum;
+ int32_t temp, sum;
int v;
PC = cia;
@@ -3098,8 +3098,8 @@
srcreg2 = translate_rreg (SD_, RN0);
dstreg = translate_rreg (SD_, RD0);
- temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
- * (unsigned32)(State.regs[srcreg1] & 0xff));
+ temp = ((uint32_t)(State.regs[srcreg2] & 0xff)
+ * (uint32_t)(State.regs[srcreg1] & 0xff));
sum = State.regs[dstreg] + temp;
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -3119,7 +3119,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed64 temp, sum;
+ int64_t temp, sum;
int v;
PC = cia;
@@ -3128,8 +3128,8 @@
dstreg1 = translate_rreg (SD_, RD0);
dstreg2 = translate_rreg (SD_, RD0);
- temp = ((signed32)(State.regs[srcreg2] & 0xffff)
- * (signed32)(State.regs[srcreg1] & 0xffff));
+ temp = ((int32_t)(State.regs[srcreg2] & 0xffff)
+ * (int32_t)(State.regs[srcreg1] & 0xffff));
State.regs[dstreg2] += (temp & 0xffffffff);
sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
@@ -3150,7 +3150,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed64 temp, sum;
+ int64_t temp, sum;
int v;
PC = cia;
@@ -3159,8 +3159,8 @@
dstreg1 = translate_rreg (SD_, RD0);
dstreg2 = translate_rreg (SD_, RD0);
- temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
- * (unsigned32)(State.regs[srcreg1] & 0xffff));
+ temp = ((uint32_t)(State.regs[srcreg2] & 0xffff)
+ * (uint32_t)(State.regs[srcreg1] & 0xffff));
State.regs[dstreg2] += (temp & 0xffffffff);
sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
@@ -3181,7 +3181,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
int v;
PC = cia;
@@ -3189,10 +3189,10 @@
srcreg2 = translate_rreg (SD_, RN0);
dstreg = translate_rreg (SD_, RD0);
- temp = ((signed32)(State.regs[srcreg2] & 0xffff)
- * (signed32)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
+ temp = ((int32_t)(State.regs[srcreg2] & 0xffff)
+ * (int32_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)((State.regs[srcreg2] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[dstreg];
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -3212,7 +3212,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
int v;
PC = cia;
@@ -3220,10 +3220,10 @@
srcreg2 = translate_rreg (SD_, RN0);
dstreg = translate_rreg (SD_, RD0);
- temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
- * (unsigned32)(State.regs[srcreg1] & 0xffff));
- temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
- * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
+ temp = ((uint32_t)(State.regs[srcreg2] & 0xffff)
+ * (uint32_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((uint32_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (uint32_t)((State.regs[srcreg2] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[dstreg];
v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -3243,7 +3243,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed64 temp;
+ int64_t temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
@@ -3251,11 +3251,11 @@
dstreg1 = translate_rreg (SD_, RD0);
dstreg2 = translate_rreg (SD_, RD2);
- temp = ((signed32)(State.regs[srcreg1] & 0xffff)
- * (signed32)(State.regs[srcreg1] & 0xffff));
+ temp = ((int32_t)(State.regs[srcreg1] & 0xffff)
+ * (int32_t)(State.regs[srcreg1] & 0xffff));
State.regs[dstreg2] = temp;
- temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
+ temp = ((int32_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)((State.regs[srcreg1] >>16) & 0xffff));
State.regs[dstreg1] = temp;
}
@@ -3266,7 +3266,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed64 temp;
+ int64_t temp;
PC = cia;
srcreg1 = translate_rreg (SD_, RM2);
@@ -3274,11 +3274,11 @@
dstreg1 = translate_rreg (SD_, RD0);
dstreg2 = translate_rreg (SD_, RD2);
- temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
- * (unsigned32)(State.regs[srcreg1] & 0xffff));
+ temp = ((uint32_t)(State.regs[srcreg1] & 0xffff)
+ * (uint32_t)(State.regs[srcreg1] & 0xffff));
State.regs[dstreg2] = temp;
- temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
- * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
+ temp = ((uint32_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (uint32_t)((State.regs[srcreg1] >>16) & 0xffff));
State.regs[dstreg1] = temp;
}
@@ -3396,7 +3396,7 @@
*am33_2
{
int dstreg, z, n, c, v;
- unsigned32 sum, imm, reg2;
+ uint32_t sum, imm, reg2;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
@@ -3437,7 +3437,7 @@
*am33_2
{
int dstreg, z, n, c, v;
- unsigned32 difference, imm, reg2;
+ uint32_t difference, imm, reg2;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
@@ -3549,7 +3549,7 @@
*am33_2
{
int dstreg;
- signed32 temp;
+ int32_t temp;
int c, z, n;
PC = cia;
@@ -3612,14 +3612,14 @@
*am33_2
{
int dstreg;
- unsigned64 temp;
+ uint64_t temp;
int z, n;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
- temp = ((signed64)(signed32)State.regs[dstreg]
- * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
+ temp = ((int64_t)(int32_t)State.regs[dstreg]
+ * (int64_t)(int32_t)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
State.regs[dstreg] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[dstreg] == 0);
@@ -3635,14 +3635,14 @@
*am33_2
{
int dstreg;
- unsigned64 temp;
+ uint64_t temp;
int z, n;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
- temp = ((unsigned64)State.regs[dstreg]
- * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
+ temp = ((uint64_t)State.regs[dstreg]
+ * (uint64_t)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
State.regs[dstreg] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[dstreg] == 0);
@@ -3909,14 +3909,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
- * (signed64)State.regs[srcreg]);
+ temp = ((int64_t)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (int64_t)State.regs[srcreg]);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -3937,14 +3937,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
- * (unsigned64)State.regs[srcreg]);
+ temp = ((uint64_t) (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (uint64_t)State.regs[srcreg]);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -3965,14 +3965,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
- * (signed64)State.regs[srcreg] & 0xff);
+ temp = ((int64_t)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (int64_t)State.regs[srcreg] & 0xff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -3993,14 +3993,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
- * (unsigned64)State.regs[srcreg] & 0xff);
+ temp = ((uint64_t) (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (uint64_t)State.regs[srcreg] & 0xff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -4021,14 +4021,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
- * (signed64)State.regs[srcreg] & 0xffff);
+ temp = ((int64_t)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (int64_t)State.regs[srcreg] & 0xffff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -4049,14 +4049,14 @@
*am33_2
{
int srcreg;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN2);
- temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
- * (unsigned64)State.regs[srcreg] & 0xffff);
+ temp = ((uint64_t) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
+ * (uint64_t)State.regs[srcreg] & 0xffff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -4197,7 +4197,7 @@
*am33_2
{
int dstreg;
- unsigned32 imm, reg2, sum;
+ uint32_t imm, reg2, sum;
int z, n, c, v;
PC = cia;
@@ -4239,7 +4239,7 @@
*am33_2
{
int dstreg;
- unsigned32 imm, reg2, difference;
+ uint32_t imm, reg2, difference;
int z, n, c, v;
PC = cia;
@@ -4352,7 +4352,7 @@
*am33_2
{
int dstreg;
- signed32 temp;
+ int32_t temp;
int c, z, n;
PC = cia;
@@ -4414,14 +4414,14 @@
*am33_2
{
int dstreg;
- unsigned64 temp;
+ uint64_t temp;
int z, n;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
- temp = ((signed64)(signed32)State.regs[dstreg]
- * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
+ temp = ((int64_t)(int32_t)State.regs[dstreg]
+ * (int64_t)(int32_t)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
State.regs[dstreg] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[dstreg] == 0);
@@ -4437,14 +4437,14 @@
*am33_2
{
int dstreg;
- unsigned64 temp;
+ uint64_t temp;
int z, n;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
- temp = ((unsigned64)State.regs[dstreg]
- * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
+ temp = ((uint64_t)State.regs[dstreg]
+ * (uint64_t) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
State.regs[dstreg] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[dstreg] == 0);
@@ -4710,15 +4710,15 @@
*am33_2
{
int srcreg, imm;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
- temp = ((signed64)(signed32)State.regs[srcreg]
- * (signed64)(signed32)imm);
+ temp = ((int64_t)(int32_t)State.regs[srcreg]
+ * (int64_t)(int32_t)imm);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -4739,15 +4739,15 @@
*am33_2
{
int srcreg, imm;
- signed64 temp, sum;
+ int64_t temp, sum;
int c, v;
PC = cia;
srcreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
- temp = ((unsigned64)State.regs[srcreg]
- * (unsigned64)imm);
+ temp = ((uint64_t)State.regs[srcreg]
+ * (uint64_t)imm);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
@@ -4768,15 +4768,15 @@
*am33_2
{
int srcreg, imm;
- signed32 temp, sum;
+ int32_t temp, sum;
int v;
PC = cia;
srcreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
- temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
- * (signed32)(signed8)(imm & 0xff));
+ temp = ((int32_t)(int8_t)(State.regs[srcreg] & 0xff)
+ * (int32_t)(int8_t)(imm & 0xff));
sum = State.regs[REG_MCRL] + temp;
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -4792,15 +4792,15 @@
*am33_2
{
int srcreg, imm;
- signed32 temp, sum;
+ int32_t temp, sum;
int v;
PC = cia;
srcreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
- temp = ((unsigned32)(State.regs[srcreg] & 0xff)
- * (unsigned32)(imm & 0xff));
+ temp = ((uint32_t)(State.regs[srcreg] & 0xff)
+ * (uint32_t)(imm & 0xff));
sum = State.regs[REG_MCRL] + temp;
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -4816,15 +4816,15 @@
*am33_2
{
int srcreg, imm;
- signed32 temp, sum;
+ int32_t temp, sum;
int v;
PC = cia;
srcreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
- temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
- * (signed32)(signed16)(imm & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[srcreg] & 0xffff)
+ * (int32_t)(int16_t)(imm & 0xffff));
sum = State.regs[REG_MCRL] + temp;
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -4840,15 +4840,15 @@
*am33_2
{
int srcreg, imm;
- signed32 temp, sum;
+ int32_t temp, sum;
int v;
PC = cia;
srcreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
- temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
- * (unsigned32)(imm & 0xffff));
+ temp = ((uint32_t)(State.regs[srcreg] & 0xffff)
+ * (uint32_t)(imm & 0xffff));
sum = State.regs[REG_MCRL] + temp;
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -4864,17 +4864,17 @@
*am33_2
{
int srcreg, imm;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
int v;
PC = cia;
srcreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
- temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
- * (signed32)(signed16)(imm & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
- * (signed32)(signed16)((imm >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[srcreg] & 0xffff)
+ * (int32_t)(int16_t)(imm & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((imm >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -4890,17 +4890,17 @@
*am33_2
{
int srcreg, imm;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
int v;
PC = cia;
srcreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
- temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
- * (unsigned32)(imm & 0xffff));
- temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
- * (unsigned32)((imm >> 16) & 0xffff));
+ temp = ((uint32_t)(State.regs[srcreg] & 0xffff)
+ * (uint32_t)(imm & 0xffff));
+ temp2 = ((uint32_t)((State.regs[srcreg] >> 16) & 0xffff)
+ * (uint32_t)((imm >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
&& (temp & 0x80000000) != (sum & 0x80000000));
@@ -4916,17 +4916,17 @@
*am33_2
{
int imm, dstreg;
- signed32 temp;
+ int32_t temp;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
- temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
- * (signed32)(signed16)(imm & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg] & 0xffff)
+ * (int32_t)(int16_t)(imm & 0xffff));
State.regs[REG_MDRQ] = temp;
- temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
- * (signed32)(signed16)((imm>>16) & 0xffff));
+ temp = ((int32_t)(int16_t)((State.regs[dstreg] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((imm>>16) & 0xffff));
State.regs[dstreg] = temp;
}
@@ -4937,17 +4937,17 @@
*am33_2
{
int imm, dstreg;
- signed32 temp;
+ int32_t temp;
PC = cia;
dstreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
- temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
- * (unsigned32)(imm & 0xffff));
+ temp = ((uint32_t)(State.regs[dstreg] & 0xffff)
+ * (uint32_t)(imm & 0xffff));
State.regs[REG_MDRQ] = temp;
- temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
- * (unsigned32)((imm >>16) & 0xffff));
+ temp = ((uint32_t)((State.regs[dstreg] >> 16) & 0xffff)
+ * (uint32_t)((imm >>16) & 0xffff));
State.regs[dstreg] = temp;
}
@@ -7348,7 +7348,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@ -7356,10 +7356,10 @@
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
State.regs[dstreg2] += State.regs[srcreg2];
@@ -7373,17 +7373,17 @@
*am33_2
{
int srcreg1, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
State.regs[dstreg2] += EXTEND4 (IMM4);
@@ -7397,7 +7397,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@ -7405,10 +7405,10 @@
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
State.regs[dstreg2] -= State.regs[srcreg2];
@@ -7422,17 +7422,17 @@
*am33_2
{
int srcreg1, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
State.regs[dstreg2] -= EXTEND4 (IMM4);
@@ -7446,7 +7446,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@ -7454,10 +7454,10 @@
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
@@ -7471,17 +7471,17 @@
*am33_2
{
int srcreg1, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
@@ -7495,7 +7495,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@ -7503,10 +7503,10 @@
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
State.regs[dstreg2] = State.regs[srcreg2];
@@ -7520,17 +7520,17 @@
*am33_2
{
int srcreg1, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
State.regs[dstreg2] = EXTEND4 (IMM4);
@@ -7544,7 +7544,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@ -7552,10 +7552,10 @@
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
temp = State.regs[dstreg2];
@@ -7571,17 +7571,17 @@
*am33_2
{
int srcreg1, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
temp = State.regs[dstreg2];
@@ -7597,7 +7597,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@ -7605,10 +7605,10 @@
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
State.regs[dstreg2] >>= State.regs[srcreg2];
@@ -7622,17 +7622,17 @@
*am33_2
{
int srcreg1, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
State.regs[dstreg2] >>= IMM4;
@@ -7647,7 +7647,7 @@
*am33_2
{
int srcreg1, srcreg2, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
@@ -7655,10 +7655,10 @@
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
State.regs[dstreg2] <<= State.regs[srcreg2];
@@ -7672,17 +7672,17 @@
*am33_2
{
int srcreg1, dstreg1, dstreg2;
- signed32 temp, temp2, sum;
+ int32_t temp, temp2, sum;
PC = cia;
srcreg1 = translate_rreg (SD_, RM1);
dstreg1 = translate_rreg (SD_, RN1);
dstreg2 = translate_rreg (SD_, RN2);
- temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
- * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
- temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
- * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+ * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
sum = temp + temp2 + State.regs[REG_MCRL];
State.regs[dstreg2] <<= IMM4;
diff --git a/sim/mn10300/dv-mn103cpu.c b/sim/mn10300/dv-mn103cpu.c
index c8e897ebbda6..b3640b93dacf 100644
--- a/sim/mn10300/dv-mn103cpu.c
+++ b/sim/mn10300/dv-mn103cpu.c
@@ -113,9 +113,9 @@ struct mn103cpu {
int pending_nmi;
int pending_reset;
/* the visible registers */
- unsigned16 interrupt_vector[NR_VECTORS];
- unsigned16 internal_memory_control;
- unsigned16 cpu_mode;
+ uint16_t interrupt_vector[NR_VECTORS];
+ uint16_t internal_memory_control;
+ uint16_t cpu_mode;
};
@@ -357,7 +357,7 @@ mn103cpu_io_read_buffer (struct hw *me,
unsigned nr_bytes)
{
struct mn103cpu *controller = hw_data (me);
- unsigned16 val = 0;
+ uint16_t val = 0;
enum mn103cpu_regs reg = decode_mn103cpu_addr (me, controller, base);
switch (reg)
@@ -383,7 +383,7 @@ mn103cpu_io_read_buffer (struct hw *me,
}
if (nr_bytes == 2)
- *(unsigned16*) dest = H2LE_2 (val);
+ *(uint16_t*) dest = H2LE_2 (val);
return nr_bytes;
}
@@ -396,14 +396,14 @@ mn103cpu_io_write_buffer (struct hw *me,
unsigned nr_bytes)
{
struct mn103cpu *controller = hw_data (me);
- unsigned16 val;
+ uint16_t val;
enum mn103cpu_regs reg;
if (nr_bytes != 2)
hw_abort (me, "must be two byte write");
reg = decode_mn103cpu_addr (me, controller, base);
- val = LE2H_2 (* (unsigned16 *) source);
+ val = LE2H_2 (* (uint16_t *) source);
switch (reg)
{
diff --git a/sim/mn10300/dv-mn103int.c b/sim/mn10300/dv-mn103int.c
index 66df97a63c8d..071d7e5389c7 100644
--- a/sim/mn10300/dv-mn103int.c
+++ b/sim/mn10300/dv-mn103int.c
@@ -517,14 +517,14 @@ decode_group (struct hw *me,
return &controller->group[gid];
}
-static unsigned8
+static uint8_t
read_icr (struct hw *me,
struct mn103int *controller,
unsigned_word base)
{
unsigned_word offset;
struct mn103int_group *group = decode_group (me, controller, base, &offset);
- unsigned8 val = 0;
+ uint8_t val = 0;
switch (group->type)
{
@@ -571,7 +571,7 @@ static void
write_icr (struct hw *me,
struct mn103int *controller,
unsigned_word base,
- unsigned8 val)
+ uint8_t val)
{
unsigned_word offset;
struct mn103int_group *group = decode_group (me, controller, base, &offset);
@@ -632,12 +632,12 @@ write_icr (struct hw *me,
/* Read the IAGR (Interrupt accepted group register) */
-static unsigned8
+static uint8_t
read_iagr (struct hw *me,
struct mn103int *controller,
unsigned_word offset)
{
- unsigned8 val;
+ uint8_t val;
switch (offset)
{
case 0:
@@ -687,13 +687,13 @@ external_group (struct mn103int *controller,
}
}
-static unsigned8
+static uint8_t
read_extmd (struct hw *me,
struct mn103int *controller,
unsigned_word offset)
{
int gid;
- unsigned8 val = 0;
+ uint8_t val = 0;
struct mn103int_group *group = external_group (controller, offset);
if (group != NULL)
{
@@ -710,7 +710,7 @@ static void
write_extmd (struct hw *me,
struct mn103int *controller,
unsigned_word offset,
- unsigned8 val)
+ uint8_t val)
{
int gid;
struct mn103int_group *group = external_group (controller, offset);
@@ -756,7 +756,7 @@ mn103int_io_read_buffer (struct hw *me,
unsigned nr_bytes)
{
struct mn103int *controller = hw_data (me);
- unsigned8 *buf = dest;
+ uint8_t *buf = dest;
unsigned byte;
/* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */
for (byte = 0; byte < nr_bytes; byte++)
@@ -789,7 +789,7 @@ mn103int_io_write_buffer (struct hw *me,
unsigned nr_bytes)
{
struct mn103int *controller = hw_data (me);
- const unsigned8 *buf = source;
+ const uint8_t *buf = source;
unsigned byte;
/* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */
for (byte = 0; byte < nr_bytes; byte++)
diff --git a/sim/mn10300/dv-mn103iop.c b/sim/mn10300/dv-mn103iop.c
index 2d86bfb17163..515b977b08b2 100644
--- a/sim/mn10300/dv-mn103iop.c
+++ b/sim/mn10300/dv-mn103iop.c
@@ -87,7 +87,7 @@ enum {
};
typedef struct _mn10300_ioport {
- unsigned8 output, output_mode, control, pin;
+ uint8_t output, output_mode, control, pin;
struct hw_event *event;
} mn10300_ioport;
@@ -96,7 +96,7 @@ typedef struct _mn10300_ioport {
struct mn103iop {
struct mn103iop_block block[NR_BLOCKS];
mn10300_ioport port[NR_PORTS];
- unsigned8 p2ss, p4ss;
+ uint8_t p2ss, p4ss;
};
@@ -215,7 +215,7 @@ read_output_reg (struct hw *me,
{
if ( nr_bytes == 1 )
{
- *(unsigned8 *)dest = io_port->port[io_port_reg].output;
+ *(uint8_t *)dest = io_port->port[io_port_reg].output;
}
else
{
@@ -236,7 +236,7 @@ read_output_mode_reg (struct hw *me,
{
/* check if there are fields which can't be written and
take appropriate action depending what bits are set */
- *(unsigned8 *)dest = io_port->port[io_port_reg].output_mode;
+ *(uint8_t *)dest = io_port->port[io_port_reg].output_mode;
}
else
{
@@ -255,7 +255,7 @@ read_control_reg (struct hw *me,
{
if ( nr_bytes == 1 )
{
- *(unsigned8 *)dest = io_port->port[io_port_reg].control;
+ *(uint8_t *)dest = io_port->port[io_port_reg].control;
}
else
{
@@ -274,7 +274,7 @@ read_pin_reg (struct hw *me,
{
if ( nr_bytes == 1 )
{
- *(unsigned8 *)dest = io_port->port[io_port_reg].pin;
+ *(uint8_t *)dest = io_port->port[io_port_reg].pin;
}
else
{
@@ -296,11 +296,11 @@ read_dedicated_control_reg (struct hw *me,
/* select on io_port_reg: */
if ( io_port_reg == P2SS )
{
- *(unsigned8 *)dest = io_port->p2ss;
+ *(uint8_t *)dest = io_port->p2ss;
}
else
{
- *(unsigned8 *)dest = io_port->p4ss;
+ *(uint8_t *)dest = io_port->p4ss;
}
}
else
@@ -375,7 +375,7 @@ write_output_reg (struct hw *me,
const void *source,
unsigned nr_bytes)
{
- unsigned8 buf = *(unsigned8 *)source;
+ uint8_t buf = *(uint8_t *)source;
if ( nr_bytes == 1 )
{
if ( io_port_reg == 3 && (buf & 0xfc) != 0 )
@@ -402,7 +402,7 @@ write_output_mode_reg (struct hw *me,
const void *source,
unsigned nr_bytes)
{
- unsigned8 buf = *(unsigned8 *)source;
+ uint8_t buf = *(uint8_t *)source;
if ( nr_bytes == 1 )
{
/* check if there are fields which can't be written and
@@ -432,7 +432,7 @@ write_control_reg (struct hw *me,
const void *source,
unsigned nr_bytes)
{
- unsigned8 buf = *(unsigned8 *)source;
+ uint8_t buf = *(uint8_t *)source;
if ( nr_bytes == 1 )
{
if ( io_port_reg == 3 && (buf & 0xfc) != 0 )
@@ -459,7 +459,7 @@ write_dedicated_control_reg (struct hw *me,
const void *source,
unsigned nr_bytes)
{
- unsigned8 buf = *(unsigned8 *)source;
+ uint8_t buf = *(uint8_t *)source;
if ( nr_bytes == 1 )
{
/* select on io_port_reg: */
diff --git a/sim/mn10300/dv-mn103ser.c b/sim/mn10300/dv-mn103ser.c
index b02f7d702758..c1a61c9798eb 100644
--- a/sim/mn10300/dv-mn103ser.c
+++ b/sim/mn10300/dv-mn103ser.c
@@ -81,8 +81,8 @@ enum serial_register_types {
#define SIO_STAT_RRDY 0x0010
typedef struct _mn10300_serial {
- unsigned16 status, control;
- unsigned8 txb, rxb, intmode;
+ uint16_t status, control;
+ uint8_t txb, rxb, intmode;
struct hw_event *event;
} mn10300_serial;
@@ -91,7 +91,7 @@ typedef struct _mn10300_serial {
struct mn103ser {
struct mn103ser_block block;
mn10300_serial device[NR_SERIAL_DEVS];
- unsigned8 serial2_timer_reg;
+ uint8_t serial2_timer_reg;
do_hw_poll_read_method *reader;
};
@@ -294,7 +294,7 @@ read_control_reg (struct hw *me,
/* really allow 1 byte read, too */
if ( nr_bytes == 2 )
{
- *(unsigned16 *)dest = H2LE_2 (serial->device[serial_reg].control);
+ *(uint16_t *)dest = H2LE_2 (serial->device[serial_reg].control);
}
else
{
@@ -313,7 +313,7 @@ read_intmode_reg (struct hw *me,
{
if ( nr_bytes == 1 )
{
- *(unsigned8 *)dest = serial->device[serial_reg].intmode;
+ *(uint8_t *)dest = serial->device[serial_reg].intmode;
}
else
{
@@ -332,7 +332,7 @@ read_txb (struct hw *me,
{
if ( nr_bytes == 1 )
{
- *(unsigned8 *)dest = serial->device[serial_reg].txb;
+ *(uint8_t *)dest = serial->device[serial_reg].txb;
}
else
{
@@ -351,7 +351,7 @@ read_rxb (struct hw *me,
{
if ( nr_bytes == 1 )
{
- *(unsigned8 *)dest = serial->device[serial_reg].rxb;
+ *(uint8_t *)dest = serial->device[serial_reg].rxb;
/* Reception buffer is now empty. */
serial->device[serial_reg].status &= ~SIO_STAT_RRDY;
}
@@ -429,11 +429,11 @@ read_status_reg (struct hw *me,
if ( nr_bytes == 1 )
{
- *(unsigned8 *)dest = (unsigned8)serial->device[serial_reg].status;
+ *(uint8_t *)dest = (uint8_t)serial->device[serial_reg].status;
}
else if ( nr_bytes == 2 && serial_reg != SC2STR )
{
- *(unsigned16 *)dest = H2LE_2 (serial->device[serial_reg].status);
+ *(uint16_t *)dest = H2LE_2 (serial->device[serial_reg].status);
}
else
{
@@ -451,7 +451,7 @@ read_serial2_timer_reg (struct hw *me,
{
if ( nr_bytes == 1 )
{
- * (unsigned8 *) dest = (unsigned8) serial->serial2_timer_reg;
+ * (uint8_t *) dest = (uint8_t) serial->serial2_timer_reg;
}
else
{
@@ -480,7 +480,7 @@ mn103ser_io_read_buffer (struct hw *me,
case SC2CTR:
read_control_reg(me, serial, serial_reg-SC0CTR, dest, nr_bytes);
HW_TRACE ((me, "read - ctrl reg%d has 0x%x\n", serial_reg-SC0CTR,
- *(unsigned8 *)dest));
+ *(uint8_t *)dest));
break;
/* interrupt mode registers */
@@ -489,7 +489,7 @@ mn103ser_io_read_buffer (struct hw *me,
case SC2ICR:
read_intmode_reg(me, serial, serial_reg-SC0ICR, dest, nr_bytes);
HW_TRACE ((me, "read - intmode reg%d has 0x%x\n", serial_reg-SC0ICR,
- *(unsigned8 *)dest));
+ *(uint8_t *)dest));
break;
/* transmission buffers */
@@ -516,12 +516,12 @@ mn103ser_io_read_buffer (struct hw *me,
case SC2STR:
read_status_reg(me, serial, serial_reg-SC0STR, dest, nr_bytes);
HW_TRACE ((me, "read - status reg%d has 0x%x\n", serial_reg-SC0STR,
- *(unsigned8 *)dest));
+ *(uint8_t *)dest));
break;
case SC2TIM:
read_serial2_timer_reg(me, serial, dest, nr_bytes);
- HW_TRACE ((me, "read - serial2 timer reg %d\n", *(unsigned8 *)dest));
+ HW_TRACE ((me, "read - serial2 timer reg %d\n", *(uint8_t *)dest));
break;
default:
@@ -539,7 +539,7 @@ write_control_reg (struct hw *me,
const void *source,
unsigned nr_bytes)
{
- unsigned16 val = LE2H_2 (*(unsigned16 *)source);
+ uint16_t val = LE2H_2 (*(uint16_t *)source);
/* really allow 1 byte write, too */
if ( nr_bytes == 2 )
@@ -568,7 +568,7 @@ write_intmode_reg (struct hw *me,
const void *source,
unsigned nr_bytes)
{
-unsigned8 val = *(unsigned8 *)source;
+uint8_t val = *(uint8_t *)source;
if ( nr_bytes == 1 )
{
@@ -604,7 +604,7 @@ write_txb (struct hw *me,
SIM_DESC sd = hw_system (me);
int status;
- serial->device[serial_reg].txb = *(unsigned8 *)source;
+ serial->device[serial_reg].txb = *(uint8_t *)source;
status = dv_sockser_status (sd);
if (!(status & DV_SOCKSER_DISCONNECTED))
@@ -635,7 +635,7 @@ write_serial2_timer_reg (struct hw *me,
{
if ( nr_bytes == 1 )
{
- serial->serial2_timer_reg = *(unsigned8 *)source;
+ serial->serial2_timer_reg = *(uint8_t *)source;
}
else
{
@@ -663,7 +663,7 @@ mn103ser_io_write_buffer (struct hw *me,
case SC1CTR:
case SC2CTR:
HW_TRACE ((me, "write - ctrl reg%d has 0x%x, nrbytes=%d.\n",
- serial_reg-SC0CTR, *(unsigned8 *)source, nr_bytes));
+ serial_reg-SC0CTR, *(uint8_t *)source, nr_bytes));
write_control_reg(me, serial, serial_reg-SC0CTR, source, nr_bytes);
break;
@@ -672,7 +672,7 @@ mn103ser_io_write_buffer (struct hw *me,
case SC1ICR:
case SC2ICR:
HW_TRACE ((me, "write - intmode reg%d has 0x%x, nrbytes=%d.\n",
- serial_reg-SC0ICR, *(unsigned8 *)source, nr_bytes));
+ serial_reg-SC0ICR, *(uint8_t *)source, nr_bytes));
write_intmode_reg(me, serial, serial_reg-SC0ICR, source, nr_bytes);
break;
@@ -701,7 +701,7 @@ mn103ser_io_write_buffer (struct hw *me,
case SC2TIM:
HW_TRACE ((me, "read - serial2 timer reg %d (nrbytes=%d)\n",
- *(unsigned8 *)source, nr_bytes));
+ *(uint8_t *)source, nr_bytes));
write_serial2_timer_reg(me, serial, source, nr_bytes);
break;
diff --git a/sim/mn10300/dv-mn103tim.c b/sim/mn10300/dv-mn103tim.c
index 969133cd46ce..bfda142fd6e8 100644
--- a/sim/mn10300/dv-mn103tim.c
+++ b/sim/mn10300/dv-mn103tim.c
@@ -97,12 +97,12 @@ enum timer_register_types {
#define NR_TIMERS 7
typedef struct _mn10300_timer_regs {
- unsigned32 base;
- unsigned8 mode;
+ uint32_t base;
+ uint8_t mode;
} mn10300_timer_regs;
typedef struct _mn10300_timer {
- unsigned32 div_ratio, start;
+ uint32_t div_ratio, start;
struct hw_event *event;
} mn10300_timer;
@@ -113,8 +113,8 @@ struct mn103tim {
mn10300_timer timer[NR_TIMERS];
/* treat timer 6 registers specially. */
- unsigned16 tm6md0, tm6md1, tm6bc, tm6ca, tm6cb;
- unsigned8 tm6mda, tm6mdb; /* compare/capture mode regs for timer 6 */
+ uint16_t tm6md0, tm6md1, tm6bc, tm6ca, tm6cb;
+ uint8_t tm6mda, tm6mdb; /* compare/capture mode regs for timer 6 */
};
/* output port ID's */
@@ -287,8 +287,8 @@ read_mode_reg (struct hw *me,
void *dest,
unsigned nr_bytes)
{
- unsigned16 val16;
- unsigned32 val32;
+ uint16_t val16;
+ uint32_t val32;
switch ( nr_bytes )
{
@@ -296,24 +296,24 @@ read_mode_reg (struct hw *me,
/* Accessing 1 byte is ok for all mode registers. */
if ( timer_nr == 6 )
{
- *(unsigned8*)dest = timers->tm6md0;
+ *(uint8_t*)dest = timers->tm6md0;
}
else
{
- *(unsigned8*)dest = timers->reg[timer_nr].mode;
+ *(uint8_t*)dest = timers->reg[timer_nr].mode;
}
break;
case 2:
if ( timer_nr == 6 )
{
- *(unsigned16 *)dest = (timers->tm6md0 << 8) | timers->tm6md1;
+ *(uint16_t *)dest = (timers->tm6md0 << 8) | timers->tm6md1;
}
else if ( timer_nr == 0 || timer_nr == 2 )
{
val16 = (timers->reg[timer_nr].mode << 8)
| timers->reg[timer_nr+1].mode;
- *(unsigned16*)dest = val16;
+ *(uint16_t*)dest = val16;
}
else
{
@@ -328,7 +328,7 @@ read_mode_reg (struct hw *me,
| (timers->reg[1].mode << 16)
| (timers->reg[2].mode << 8)
| timers->reg[3].mode;
- *(unsigned32*)dest = val32;
+ *(uint32_t*)dest = val32;
}
else
{
@@ -350,8 +350,8 @@ read_base_reg (struct hw *me,
void *dest,
unsigned nr_bytes)
{
- unsigned16 val16;
- unsigned32 val32;
+ uint16_t val16;
+ uint32_t val32;
/* Check nr_bytes: accesses of 1, 2 and 4 bytes allowed depending on timer. */
switch ( nr_bytes )
@@ -360,7 +360,7 @@ read_base_reg (struct hw *me,
/* Reading 1 byte is ok for all registers. */
if ( timer_nr < NR_8BIT_TIMERS )
{
- *(unsigned8*)dest = timers->reg[timer_nr].base;
+ *(uint8_t*)dest = timers->reg[timer_nr].base;
}
break;
@@ -380,7 +380,7 @@ read_base_reg (struct hw *me,
{
val16 = timers->reg[timer_nr].base;
}
- *(unsigned16*)dest = val16;
+ *(uint16_t*)dest = val16;
}
break;
@@ -389,12 +389,12 @@ read_base_reg (struct hw *me,
{
val32 = (timers->reg[0].base << 24) | (timers->reg[1].base << 16)
| (timers->reg[2].base << 8) | timers->reg[3].base;
- *(unsigned32*)dest = val32;
+ *(uint32_t*)dest = val32;
}
else if ( timer_nr == 4 )
{
val32 = (timers->reg[4].base << 16) | timers->reg[5].base;
- *(unsigned32*)dest = val32;
+ *(uint32_t*)dest = val32;
}
else
{
@@ -416,7 +416,7 @@ read_counter (struct hw *me,
void *dest,
unsigned nr_bytes)
{
- unsigned32 val;
+ uint32_t val;
if ( NULL == timers->timer[timer_nr].event )
{
@@ -449,15 +449,15 @@ read_counter (struct hw *me,
switch (nr_bytes) {
case 1:
- *(unsigned8 *)dest = val;
+ *(uint8_t *)dest = val;
break;
case 2:
- *(unsigned16 *)dest = val;
+ *(uint16_t *)dest = val;
break;
case 4:
- *(unsigned32 *)dest = val;
+ *(uint32_t *)dest = val;
break;
default:
@@ -474,26 +474,26 @@ read_special_timer6_reg (struct hw *me,
void *dest,
unsigned nr_bytes)
{
- unsigned32 val;
+ uint32_t val;
switch (nr_bytes) {
case 1:
{
switch ( timer_nr ) {
case TM6MDA:
- *(unsigned8 *)dest = timers->tm6mda;
+ *(uint8_t *)dest = timers->tm6mda;
break;
case TM6MDB:
- *(unsigned8 *)dest = timers->tm6mdb;
+ *(uint8_t *)dest = timers->tm6mdb;
break;
case TM6CA:
- *(unsigned8 *)dest = timers->tm6ca;
+ *(uint8_t *)dest = timers->tm6ca;
break;
case TM6CB:
- *(unsigned8 *)dest = timers->tm6cb;
+ *(uint8_t *)dest = timers->tm6cb;
break;
default:
@@ -505,11 +505,11 @@ read_special_timer6_reg (struct hw *me,
case 2:
if ( timer_nr == TM6CA )
{
- *(unsigned16 *)dest = timers->tm6ca;
+ *(uint16_t *)dest = timers->tm6ca;
}
else if ( timer_nr == TM6CB )
{
- *(unsigned16 *)dest = timers->tm6cb;
+ *(uint16_t *)dest = timers->tm6cb;
}
else
{
@@ -642,8 +642,8 @@ write_base_reg (struct hw *me,
unsigned nr_bytes)
{
unsigned i;
- const unsigned8 *buf8 = source;
- const unsigned16 *buf16 = source;
+ const uint8_t *buf8 = source;
+ const uint16_t *buf16 = source;
/* If TMnCNE == 0 (counting is off), writing to the base register
(TMnBR) causes a simultaneous write to the counter reg (TMnBC).
@@ -713,8 +713,8 @@ write_mode_reg (struct hw *me,
/* for timers 0 to 5 */
{
unsigned i;
- unsigned8 mode_val, next_mode_val;
- unsigned32 div_ratio;
+ uint8_t mode_val, next_mode_val;
+ uint32_t div_ratio;
if ( nr_bytes != 1 )
{
@@ -722,7 +722,7 @@ write_mode_reg (struct hw *me,
timer_nr);
}
- mode_val = *(unsigned8 *)source;
+ mode_val = *(uint8_t *)source;
timers->reg[timer_nr].mode = mode_val;
if ( ( mode_val & count_and_load_mask ) == count_and_load_mask )
@@ -840,8 +840,8 @@ write_tm6md (struct hw *me,
const void *source,
unsigned nr_bytes)
{
- unsigned8 mode_val0 = 0x00, mode_val1 = 0x00;
- unsigned32 div_ratio;
+ uint8_t mode_val0 = 0x00, mode_val1 = 0x00;
+ uint32_t div_ratio;
long timer_nr = 6;
unsigned_word offset = address - timers->block[0].base;
@@ -854,7 +854,7 @@ write_tm6md (struct hw *me,
if ( offset == 0x84 ) /* address of TM6MD */
{
/* Fill in first byte of mode */
- mode_val0 = *(unsigned8 *)source;
+ mode_val0 = *(uint8_t *)source;
timers->tm6md0 = mode_val0;
if ( ( mode_val0 & 0x26 ) != 0 )
@@ -868,11 +868,11 @@ write_tm6md (struct hw *me,
/* Fill in second byte of mode */
if ( nr_bytes == 2 )
{
- mode_val1 = *(unsigned8 *)source+1;
+ mode_val1 = *(uint8_t *)source+1;
}
else
{
- mode_val1 = *(unsigned8 *)source;
+ mode_val1 = *(uint8_t *)source;
}
timers->tm6md1 = mode_val1;
@@ -931,26 +931,26 @@ write_special_timer6_reg (struct hw *me,
const void *source,
unsigned nr_bytes)
{
- unsigned32 val;
+ uint32_t val;
switch (nr_bytes) {
case 1:
{
switch ( timer_nr ) {
case TM6MDA:
- timers->tm6mda = *(unsigned8 *)source;
+ timers->tm6mda = *(uint8_t *)source;
break;
case TM6MDB:
- timers->tm6mdb = *(unsigned8 *)source;
+ timers->tm6mdb = *(uint8_t *)source;
break;
case TM6CA:
- timers->tm6ca = *(unsigned8 *)source;
+ timers->tm6ca = *(uint8_t *)source;
break;
case TM6CB:
- timers->tm6cb = *(unsigned8 *)source;
+ timers->tm6cb = *(uint8_t *)source;
break;
default:
@@ -962,11 +962,11 @@ write_special_timer6_reg (struct hw *me,
case 2:
if ( timer_nr == TM6CA )
{
- timers->tm6ca = *(unsigned16 *)source;
+ timers->tm6ca = *(uint16_t *)source;
}
else if ( timer_nr == TM6CB )
{
- timers->tm6cb = *(unsigned16 *)source;
+ timers->tm6cb = *(uint16_t *)source;
}
else
{
@@ -992,7 +992,7 @@ mn103tim_io_write_buffer (struct hw *me,
enum timer_register_types timer_reg;
HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,
- (int) nr_bytes, *(unsigned32 *)source));
+ (int) nr_bytes, *(uint32_t *)source));
timer_reg = decode_addr (me, timers, base);
diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c
index 551d17630082..2e7fd1630479 100644
--- a/sim/mn10300/interp.c
+++ b/sim/mn10300/interp.c
@@ -320,7 +320,7 @@ sim_create_inferior (SIM_DESC sd,
} else {
PC = 0;
}
- CPU_PC_SET (STATE_CPU (sd, 0), (unsigned64) PC);
+ CPU_PC_SET (STATE_CPU (sd, 0), (uint64_t) PC);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2)
PSW |= PSW_FE;
@@ -335,7 +335,7 @@ static int
mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
reg_t reg = State.regs[rn];
- uint8 *a = memory;
+ uint8_t *a = memory;
a[0] = reg;
a[1] = reg >> 8;
a[2] = reg >> 16;
@@ -346,7 +346,7 @@ mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
static int
mn10300_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- uint8 *a = memory;
+ uint8_t *a = memory;
State.regs[rn] = (a[3] << 24) + (a[2] << 16) + (a[1] << 8) + a[0];
return length;
}
diff --git a/sim/mn10300/mn10300.igen b/sim/mn10300/mn10300.igen
index 9431c0b51790..6330d6f0090a 100644
--- a/sim/mn10300/mn10300.igen
+++ b/sim/mn10300/mn10300.igen
@@ -21,7 +21,7 @@
*am33_2
{
/* OP_8000 (); */
- signed32 immed = EXTEND8 (IMM8);
+ int32_t immed = EXTEND8 (IMM8);
State.regs[REG_D0+DN0] = immed;
PC = cia;
}
@@ -776,7 +776,7 @@
{
/* OP_2C0000 (); */
- unsigned32 value;
+ uint32_t value;
PC = cia;
value = EXTEND16 (FETCH16(IMM16A, IMM16B));
@@ -794,7 +794,7 @@
{
/* OP_FCCC0000 (); */
- unsigned32 value;
+ uint32_t value;
PC = cia;
value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -812,7 +812,7 @@
{
/* OP_240000 (); */
- unsigned32 value;
+ uint32_t value;
PC = cia;
value = FETCH16(IMM16A, IMM16B);
@@ -1734,7 +1734,7 @@
{
/* OP_F8FE00 (); */
- unsigned32 imm;
+ uint32_t imm;
/* Note: no PSW changes. */
PC = cia;
@@ -1753,7 +1753,7 @@
{
/* OP_FAFE0000 (); */
- unsigned32 imm;
+ uint32_t imm;
/* Note: no PSW changes. */
PC = cia;
@@ -1772,7 +1772,7 @@
{
/* OP_FCFE0000 (); */
- unsigned32 imm;
+ uint32_t imm;
/* Note: no PSW changes. */
PC = cia;
@@ -1792,7 +1792,7 @@
{
/* OP_F140 (); */
int z, c, n, v;
- unsigned32 reg1, reg2, sum;
+ uint32_t reg1, reg2, sum;
PC = cia;
reg1 = State.regs[REG_D0 + DM1];
@@ -1912,7 +1912,7 @@
{
/* OP_F180 (); */
int z, c, n, v;
- unsigned32 reg1, reg2, difference;
+ uint32_t reg1, reg2, difference;
PC = cia;
reg1 = State.regs[REG_D0 + DM1];
@@ -1942,12 +1942,12 @@
{
/* OP_F240 (); */
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
- temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
- * (signed64)(signed32)State.regs[REG_D0 + DM1]);
+ temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
+ * (int64_t)(int32_t)State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
@@ -1967,12 +1967,12 @@
{
/* OP_F250 (); */
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
- temp = ((unsigned64)State.regs[REG_D0 + DN0]
- * (unsigned64)State.regs[REG_D0 + DM1]);
+ temp = ((uint64_t)State.regs[REG_D0 + DN0]
+ * (uint64_t)State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[REG_D0 + DN0] == 0);
@@ -1992,20 +1992,20 @@
{
/* OP_F260 (); */
- signed64 temp;
- signed32 denom;
+ int64_t temp;
+ int32_t denom;
int n, z, v;
PC = cia;
- denom = (signed32)State.regs[REG_D0 + DM1];
+ denom = (int32_t)State.regs[REG_D0 + DM1];
temp = State.regs[REG_MDR];
temp <<= 32;
temp |= State.regs[REG_D0 + DN0];
if ( !(v = (0 == denom)) )
{
- State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
- temp /= (signed32)State.regs[REG_D0 + DM1];
+ State.regs[REG_MDR] = temp % (int32_t)State.regs[REG_D0 + DM1];
+ temp /= (int32_t)State.regs[REG_D0 + DM1];
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
}
else
@@ -2030,12 +2030,12 @@
{
/* OP_F270 (); */
- unsigned64 temp;
- unsigned32 denom;
+ uint64_t temp;
+ uint32_t denom;
int n, z, v;
PC = cia;
- denom = (unsigned32)State.regs[REG_D0 + DM1];
+ denom = (uint32_t)State.regs[REG_D0 + DM1];
temp = State.regs[REG_MDR];
temp <<= 32;
temp |= State.regs[REG_D0 + DN0];
@@ -2067,7 +2067,7 @@
{
/* OP_40 (); */
- unsigned32 imm;
+ uint32_t imm;
PC = cia;
imm = 1;
@@ -2591,7 +2591,7 @@
{
/* OP_F080 (); */
- unsigned32 temp;
+ uint32_t temp;
int z;
PC = cia;
@@ -2615,7 +2615,7 @@
{
/* OP_FE000000 (); */
- unsigned32 temp;
+ uint32_t temp;
int z;
PC = cia;
@@ -2639,7 +2639,7 @@
{
/* OP_FAF00000 (); */
- unsigned32 temp;
+ uint32_t temp;
int z;
PC = cia;
@@ -2662,7 +2662,7 @@
{
/* OP_F090 (); */
- unsigned32 temp;
+ uint32_t temp;
int z;
PC = cia;
@@ -2686,7 +2686,7 @@
{
/* OP_FE010000 (); */
- unsigned32 temp;
+ uint32_t temp;
int z;
PC = cia;
@@ -2710,7 +2710,7 @@
{
/* OP_FAF40000 (); */
- unsigned32 temp;
+ uint32_t temp;
int z;
PC = cia;
@@ -2733,7 +2733,7 @@
{
/* OP_F2B0 (); */
- signed32 temp;
+ int32_t temp;
int z, n, c;
PC = cia;
@@ -2758,7 +2758,7 @@
{
/* OP_F8C800 (); */
- signed32 temp;
+ int32_t temp;
int z, n, c;
PC = cia;
@@ -2892,7 +2892,7 @@
{
/* OP_F284 (); */
- unsigned32 value;
+ uint32_t value;
int c,n,z;
PC = cia;
@@ -2919,7 +2919,7 @@
{
/* OP_F280 (); */
- unsigned32 value;
+ uint32_t value;
int c,n,z;
PC = cia;
@@ -3499,7 +3499,7 @@
{
/* OP_F0F0 (); */
- unsigned32 next_pc, sp;
+ uint32_t next_pc, sp;
PC = cia;
sp = State.regs[REG_SP];
@@ -3521,7 +3521,7 @@
{
/* OP_FAFF0000 (); */
- unsigned32 next_pc, sp;
+ uint32_t next_pc, sp;
PC = cia;
sp = State.regs[REG_SP];
@@ -3543,7 +3543,7 @@
{
/* OP_FCFF0000 (); */
- unsigned32 next_pc, sp;
+ uint32_t next_pc, sp;
PC = cia;
sp = State.regs[REG_SP];
@@ -3565,7 +3565,7 @@
{
/* OP_F0FC (); */
- unsigned32 sp;
+ uint32_t sp;
sp = State.regs[REG_SP];
State.regs[REG_PC] = load_word(sp);
@@ -3583,7 +3583,7 @@
{
/* OP_F0FD (); */
- unsigned32 sp;
+ uint32_t sp;
sp = State.regs[REG_SP];
PSW = load_half(sp);
@@ -3603,7 +3603,7 @@
{
/* OP_F0FE (); */
- unsigned32 sp, next_pc;
+ uint32_t sp, next_pc;
PC = cia;
sp = State.regs[REG_SP];
@@ -3685,12 +3685,12 @@
{
/* OP_F600 (); */
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
- temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
- * (signed64)(signed32)State.regs[REG_D0 + DM1]);
+ temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
+ * (int64_t)(int32_t)State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
@@ -3710,12 +3710,12 @@
{
/* OP_F90000 (); */
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
- temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
- * (signed64)(signed32)EXTEND8 (IMM8));
+ temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
+ * (int64_t)(int32_t)EXTEND8 (IMM8));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
@@ -3735,12 +3735,12 @@
{
/* OP_FB000000 (); */
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
- temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
- * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
+ temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
+ * (int64_t)(int32_t)EXTEND16 (FETCH16(IMM16A, IMM16B)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
@@ -3760,12 +3760,12 @@
{
/* OP_FD000000 (); */
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
- temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
- * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+ temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
+ * (int64_t)(int32_t)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
@@ -3785,12 +3785,12 @@
{
/* OP_F610 (); */
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
- temp = ((unsigned64) State.regs[REG_D0 + DN0]
- * (unsigned64) State.regs[REG_D0 + DM1]);
+ temp = ((uint64_t) State.regs[REG_D0 + DN0]
+ * (uint64_t) State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
@@ -3810,12 +3810,12 @@
{
/* OP_F91400 (); */
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
- temp = ((unsigned64)State.regs[REG_D0 + DN0]
- * (unsigned64)EXTEND8 (IMM8));
+ temp = ((uint64_t)State.regs[REG_D0 + DN0]
+ * (uint64_t)EXTEND8 (IMM8));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
@@ -3835,12 +3835,12 @@
{
/* OP_FB140000 (); */
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
- temp = ((unsigned64)State.regs[REG_D0 + DN0]
- * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
+ temp = ((uint64_t)State.regs[REG_D0 + DN0]
+ * (uint64_t) EXTEND16 (FETCH16(IMM16A, IMM16B)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
@@ -3860,12 +3860,12 @@
{
/* OP_FD140000 (); */
- unsigned64 temp;
+ uint64_t temp;
int n, z;
PC = cia;
- temp = ((unsigned64)State.regs[REG_D0 + DN0]
- * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+ temp = ((uint64_t)State.regs[REG_D0 + DN0]
+ * (uint64_t)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
@@ -3975,8 +3975,8 @@
{
/* OP_CE00 (); */
- unsigned32 sp = State.regs[REG_SP];
- unsigned32 mask;
+ uint32_t sp = State.regs[REG_SP];
+ uint32_t mask;
PC = cia;
mask = REGS;
@@ -4074,8 +4074,8 @@
{
/* OP_CF00 (); */
- unsigned32 sp = State.regs[REG_SP];
- unsigned32 mask;
+ uint32_t sp = State.regs[REG_SP];
+ uint32_t mask;
PC = cia;
mask = REGS;
@@ -4173,8 +4173,8 @@
{
/* OP_CD000000 (); */
- unsigned32 next_pc, sp;
- unsigned32 mask;
+ uint32_t next_pc, sp;
+ uint32_t mask;
PC = cia;
sp = State.regs[REG_SP];
@@ -4282,8 +4282,8 @@
{
/* OP_DD000000 (); */
- unsigned32 next_pc, sp;
- unsigned32 mask;
+ uint32_t next_pc, sp;
+ uint32_t mask;
PC = cia;
sp = State.regs[REG_SP];
@@ -4391,8 +4391,8 @@
{
/* OP_DF0000 (); */
- unsigned32 sp, offset;
- unsigned32 mask;
+ uint32_t sp, offset;
+ uint32_t mask;
PC = cia;
State.regs[REG_SP] += IMM8;
@@ -4496,8 +4496,8 @@
{
/* OP_DE0000 (); */
- unsigned32 sp, offset;
- unsigned32 mask;
+ uint32_t sp, offset;
+ uint32_t mask;
PC = cia;
State.regs[REG_SP] += IMM8;
diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h
index 82306e667d2f..f1ab23ffe4fb 100644
--- a/sim/mn10300/mn10300_sim.h
+++ b/sim/mn10300/mn10300_sim.h
@@ -11,18 +11,11 @@
extern SIM_DESC simulator;
-typedef unsigned8 uint8;
-typedef signed8 int8;
-typedef unsigned16 uint16;
-typedef signed16 int16;
-typedef unsigned32 uint32;
-typedef signed32 int32;
-
typedef struct
{
- uint32 low, high;
+ uint32_t low, high;
} dword;
-typedef uint32 reg_t;
+typedef uint32_t reg_t;
struct simops
{
@@ -160,12 +153,12 @@ u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
PC, read_map, (ADDR)))
static INLINE2 dword
-u642dw (unsigned64 dw)
+u642dw (uint64_t dw)
{
dword r;
- r.low = (unsigned32)dw;
- r.high = (unsigned32)(dw >> 32);
+ r.low = (uint32_t)dw;
+ r.high = (uint32_t)(dw >> 32);
return r;
}
@@ -186,20 +179,20 @@ sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
PC, write_map, (ADDR), dw2u64 (DATA))
-static INLINE2 unsigned64
+static INLINE2 uint64_t
dw2u64 (dword data)
{
- return data.low | (((unsigned64)data.high) << 32);
+ return data.low | (((uint64_t)data.high) << 32);
}
/* Function declarations. */
-INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg);
-INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg);
-INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd);
-INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg);
-INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg);
-INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd);
+INLINE_SIM_MAIN (void) genericAdd (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericSub (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericCmp (uint32_t leftOpnd, uint32_t rightOpnd);
+INLINE_SIM_MAIN (void) genericOr (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericXor (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericBtst (uint32_t leftOpnd, uint32_t rightOpnd);
INLINE_SIM_MAIN (void) do_syscall (SIM_DESC sd);
void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
diff --git a/sim/mn10300/op_utils.c b/sim/mn10300/op_utils.c
index eb4439f5f09c..2fccf2da207f 100644
--- a/sim/mn10300/op_utils.c
+++ b/sim/mn10300/op_utils.c
@@ -25,10 +25,10 @@
INLINE_SIM_MAIN (void)
-genericAdd(unsigned32 source, unsigned32 destReg)
+genericAdd(uint32_t source, uint32_t destReg)
{
int z, c, n, v;
- unsigned32 dest, sum;
+ uint32_t dest, sum;
dest = State.regs[destReg];
sum = source + dest;
@@ -49,10 +49,10 @@ genericAdd(unsigned32 source, unsigned32 destReg)
INLINE_SIM_MAIN (void)
-genericSub(unsigned32 source, unsigned32 destReg)
+genericSub(uint32_t source, uint32_t destReg)
{
int z, c, n, v;
- unsigned32 dest, difference;
+ uint32_t dest, difference;
dest = State.regs[destReg];
difference = dest - source;
@@ -70,10 +70,10 @@ genericSub(unsigned32 source, unsigned32 destReg)
}
INLINE_SIM_MAIN (void)
-genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd)
+genericCmp(uint32_t leftOpnd, uint32_t rightOpnd)
{
int z, c, n, v;
- unsigned32 value;
+ uint32_t value;
value = rightOpnd - leftOpnd;
@@ -90,7 +90,7 @@ genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd)
INLINE_SIM_MAIN (void)
-genericOr(unsigned32 source, unsigned32 destReg)
+genericOr(uint32_t source, uint32_t destReg)
{
int n, z;
@@ -103,7 +103,7 @@ genericOr(unsigned32 source, unsigned32 destReg)
INLINE_SIM_MAIN (void)
-genericXor(unsigned32 source, unsigned32 destReg)
+genericXor(uint32_t source, uint32_t destReg)
{
int n, z;
@@ -116,9 +116,9 @@ genericXor(unsigned32 source, unsigned32 destReg)
INLINE_SIM_MAIN (void)
-genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd)
+genericBtst(uint32_t leftOpnd, uint32_t rightOpnd)
{
- unsigned32 temp;
+ uint32_t temp;
int z, n;
temp = rightOpnd;
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 06/17] sim: erc32: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (3 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 05/17] sim: mn10300: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 07/17] sim: testsuite: " Mike Frysinger
` (10 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.
---
sim/erc32/erc32.c | 234 ++++++++++++++++++++++-----------------------
sim/erc32/exec.c | 114 +++++++++++-----------
sim/erc32/float.c | 2 +-
sim/erc32/func.c | 96 +++++++++----------
sim/erc32/interf.c | 6 +-
sim/erc32/sis.c | 4 +-
sim/erc32/sis.h | 161 +++++++++++++++----------------
7 files changed, 305 insertions(+), 312 deletions(-)
diff --git a/sim/erc32/erc32.c b/sim/erc32/erc32.c
index 8789cbc812a6..0206c02e6f0e 100644
--- a/sim/erc32/erc32.c
+++ b/sim/erc32/erc32.c
@@ -34,8 +34,8 @@
#include "sim-config.h"
extern int ctrl_c;
-extern int32 sis_verbose;
-extern int32 sparclite, sparclite_board;
+extern int32_t sis_verbose;
+extern int32_t sparclite, sparclite_board;
extern int rom8,wrp,uben;
extern char uart_dev1[], uart_dev2[];
@@ -147,45 +147,45 @@ extern int errmec;
/* MEC registers */
static char fname[256];
-static int32 find = 0;
-static uint32 mec_ssa[2]; /* Write protection start address */
-static uint32 mec_sea[2]; /* Write protection end address */
-static uint32 mec_wpr[2]; /* Write protection control fields */
-static uint32 mec_sfsr;
-static uint32 mec_ffar;
-static uint32 mec_ipr;
-static uint32 mec_imr;
-static uint32 mec_isr;
-static uint32 mec_icr;
-static uint32 mec_ifr;
-static uint32 mec_mcr; /* MEC control register */
-static uint32 mec_memcfg; /* Memory control register */
-static uint32 mec_wcr; /* MEC waitstate register */
-static uint32 mec_iocr; /* MEC IO control register */
-static uint32 posted_irq;
-static uint32 mec_ersr; /* MEC error and status register */
-static uint32 mec_tcr; /* MEC test comtrol register */
-
-static uint32 rtc_counter;
-static uint32 rtc_reload;
-static uint32 rtc_scaler;
-static uint32 rtc_scaler_start;
-static uint32 rtc_enabled;
-static uint32 rtc_cr;
-static uint32 rtc_se;
-
-static uint32 gpt_counter;
-static uint32 gpt_reload;
-static uint32 gpt_scaler;
-static uint32 gpt_scaler_start;
-static uint32 gpt_enabled;
-static uint32 gpt_cr;
-static uint32 gpt_se;
-
-static uint32 wdog_scaler;
-static uint32 wdog_counter;
-static uint32 wdog_rst_delay;
-static uint32 wdog_rston;
+static int32_t find = 0;
+static uint32_t mec_ssa[2]; /* Write protection start address */
+static uint32_t mec_sea[2]; /* Write protection end address */
+static uint32_t mec_wpr[2]; /* Write protection control fields */
+static uint32_t mec_sfsr;
+static uint32_t mec_ffar;
+static uint32_t mec_ipr;
+static uint32_t mec_imr;
+static uint32_t mec_isr;
+static uint32_t mec_icr;
+static uint32_t mec_ifr;
+static uint32_t mec_mcr; /* MEC control register */
+static uint32_t mec_memcfg; /* Memory control register */
+static uint32_t mec_wcr; /* MEC waitstate register */
+static uint32_t mec_iocr; /* MEC IO control register */
+static uint32_t posted_irq;
+static uint32_t mec_ersr; /* MEC error and status register */
+static uint32_t mec_tcr; /* MEC test comtrol register */
+
+static uint32_t rtc_counter;
+static uint32_t rtc_reload;
+static uint32_t rtc_scaler;
+static uint32_t rtc_scaler_start;
+static uint32_t rtc_enabled;
+static uint32_t rtc_cr;
+static uint32_t rtc_se;
+
+static uint32_t gpt_counter;
+static uint32_t gpt_reload;
+static uint32_t gpt_scaler;
+static uint32_t gpt_scaler_start;
+static uint32_t gpt_enabled;
+static uint32_t gpt_cr;
+static uint32_t gpt_se;
+
+static uint32_t wdog_scaler;
+static uint32_t wdog_counter;
+static uint32_t wdog_rst_delay;
+static uint32_t wdog_rston;
enum wdog_type {
init, disabled, enabled, stopped
@@ -210,17 +210,17 @@ static enum wdog_type wdog_status;
/* Memory support variables */
-static uint32 mem_ramr_ws; /* RAM read waitstates */
-static uint32 mem_ramw_ws; /* RAM write waitstates */
-static uint32 mem_romr_ws; /* ROM read waitstates */
-static uint32 mem_romw_ws; /* ROM write waitstates */
-static uint32 mem_ramstart; /* RAM start */
-static uint32 mem_ramend; /* RAM end */
-static uint32 mem_rammask; /* RAM address mask */
-static uint32 mem_ramsz; /* RAM size */
-static uint32 mem_romsz; /* ROM size */
-static uint32 mem_accprot; /* RAM write protection enabled */
-static uint32 mem_blockprot; /* RAM block write protection enabled */
+static uint32_t mem_ramr_ws; /* RAM read waitstates */
+static uint32_t mem_ramw_ws; /* RAM write waitstates */
+static uint32_t mem_romr_ws; /* ROM read waitstates */
+static uint32_t mem_romw_ws; /* ROM write waitstates */
+static uint32_t mem_ramstart; /* RAM start */
+static uint32_t mem_ramend; /* RAM end */
+static uint32_t mem_rammask; /* RAM address mask */
+static uint32_t mem_ramsz; /* RAM size */
+static uint32_t mem_romsz; /* ROM size */
+static uint32_t mem_accprot; /* RAM write protection enabled */
+static uint32_t mem_blockprot; /* RAM block write protection enabled */
static unsigned char romb[ROM_SZ];
static unsigned char ramb[RAM_END - RAM_START];
@@ -228,11 +228,11 @@ static unsigned char ramb[RAM_END - RAM_START];
/* UART support variables */
-static int32 fd1, fd2; /* file descriptor for input file */
-static int32 Ucontrol; /* UART status register */
+static int32_t fd1, fd2; /* file descriptor for input file */
+static int32_t Ucontrol; /* UART status register */
static unsigned char aq[UARTBUF], bq[UARTBUF];
-static int32 anum, aind = 0;
-static int32 bnum, bind = 0;
+static int32_t anum, aind = 0;
+static int32_t bnum, bind = 0;
static char wbufa[UARTBUF], wbufb[UARTBUF];
static unsigned wnuma;
static unsigned wnumb;
@@ -243,8 +243,8 @@ static struct termios ioc1, ioc2, iocold1, iocold2;
static int f1open = 0, f2open = 0;
static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
-static uint32 uart_stat_reg;
-static uint32 uarta_data, uartb_data;
+static uint32_t uart_stat_reg;
+static uint32_t uarta_data, uartb_data;
#ifdef ERA
int era = 0;
@@ -263,16 +263,16 @@ static void decode_wcr (void);
static void decode_mcr (void);
static void close_port (void);
static void mec_reset (void);
-static void mec_intack (int32 level);
+static void mec_intack (int32_t level);
static void chk_irq (void);
-static void mec_irq (int32 level);
-static void set_sfsr (uint32 fault, uint32 addr,
- uint32 asi, uint32 read);
-static int32 mec_read (uint32 addr, uint32 asi, uint32 *data);
-static int mec_write (uint32 addr, uint32 data);
+static void mec_irq (int32_t level);
+static void set_sfsr (uint32_t fault, uint32_t addr,
+ uint32_t asi, uint32_t read);
+static int32_t mec_read (uint32_t addr, uint32_t asi, uint32_t *data);
+static int mec_write (uint32_t addr, uint32_t data);
static void port_init (void);
-static uint32 read_uart (uint32 addr);
-static void write_uart (uint32 addr, uint32 data);
+static uint32_t read_uart (uint32_t addr);
+static void write_uart (uint32_t addr, uint32_t data);
static void flush_uart (void);
static void uarta_tx (void);
static void uartb_tx (void);
@@ -283,18 +283,18 @@ static void wdog_intr (void *arg);
static void wdog_start (void);
static void rtc_intr (void *arg);
static void rtc_start (void);
-static uint32 rtc_counter_read (void);
-static void rtc_scaler_set (uint32 val);
-static void rtc_reload_set (uint32 val);
+static uint32_t rtc_counter_read (void);
+static void rtc_scaler_set (uint32_t val);
+static void rtc_reload_set (uint32_t val);
static void gpt_intr (void *arg);
static void gpt_start (void);
-static uint32 gpt_counter_read (void);
-static void gpt_scaler_set (uint32 val);
-static void gpt_reload_set (uint32 val);
-static void timer_ctrl (uint32 val);
-static void * get_mem_ptr (uint32 addr, uint32 size);
-static void store_bytes (unsigned char *mem, uint32 waddr,
- uint32 *data, int sz, int32 *ws);
+static uint32_t gpt_counter_read (void);
+static void gpt_scaler_set (uint32_t val);
+static void gpt_reload_set (uint32_t val);
+static void timer_ctrl (uint32_t val);
+static void * get_mem_ptr (uint32_t addr, uint32_t size);
+static void store_bytes (unsigned char *mem, uint32_t waddr,
+ uint32_t *data, int sz, int32_t *ws);
extern int ext_irl;
@@ -390,7 +390,7 @@ mecparerror(void)
/* IU error mode manager */
void
-error_mode(uint32 pc)
+error_mode(uint32_t pc)
{
mec_ersr |= 0x1;
@@ -551,7 +551,7 @@ mec_reset(void)
static void
-mec_intack(int32 level)
+mec_intack(int32_t level)
{
int irq_test;
@@ -568,8 +568,8 @@ mec_intack(int32 level)
static void
chk_irq(void)
{
- int32 i;
- uint32 itmp;
+ int32_t i;
+ uint32_t itmp;
int old_irl;
old_irl = ext_irl;
@@ -591,14 +591,14 @@ chk_irq(void)
}
static void
-mec_irq(int32 level)
+mec_irq(int32_t level)
{
mec_ipr |= (1 << level);
chk_irq();
}
static void
-set_sfsr(uint32 fault, uint32 addr, uint32 asi, uint32 read)
+set_sfsr(uint32_t fault, uint32_t addr, uint32_t asi, uint32_t read)
{
if ((asi == 0xa) || (asi == 0xb)) {
mec_ffar = addr;
@@ -615,8 +615,8 @@ set_sfsr(uint32 fault, uint32 addr, uint32 asi, uint32 read)
}
}
-static int32
-mec_read(uint32 addr, uint32 asi, uint32 *data)
+static int32_t
+mec_read(uint32_t addr, uint32_t asi, uint32_t *data)
{
switch (addr & 0x0ff) {
@@ -743,7 +743,7 @@ mec_read(uint32 addr, uint32 asi, uint32 *data)
}
static int
-mec_write(uint32 addr, uint32 data)
+mec_write(uint32_t addr, uint32_t data)
{
if (sis_verbose > 1)
printf("MEC write a: %08x, d: %08x\n",addr,data);
@@ -1039,8 +1039,8 @@ port_init(void)
}
-static uint32
-read_uart(uint32 addr)
+static uint32_t
+read_uart(uint32_t addr)
{
unsigned tmp;
@@ -1055,7 +1055,7 @@ read_uart(uint32 addr)
if (aind < anum) {
if ((aind + 1) < anum)
mec_irq(4);
- return (0x700 | (uint32) aq[aind++]);
+ return (0x700 | (uint32_t) aq[aind++]);
} else {
if (f1open) {
anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
@@ -1064,9 +1064,9 @@ read_uart(uint32 addr)
aind = 0;
if ((aind + 1) < anum)
mec_irq(4);
- return (0x700 | (uint32) aq[aind++]);
+ return (0x700 | (uint32_t) aq[aind++]);
} else {
- return (0x600 | (uint32) aq[aind]);
+ return (0x600 | (uint32_t) aq[aind]);
}
}
@@ -1087,7 +1087,7 @@ read_uart(uint32 addr)
if (bind < bnum) {
if ((bind + 1) < bnum)
mec_irq(5);
- return (0x700 | (uint32) bq[bind++]);
+ return (0x700 | (uint32_t) bq[bind++]);
} else {
if (f2open) {
bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
@@ -1096,9 +1096,9 @@ read_uart(uint32 addr)
bind = 0;
if ((bind + 1) < bnum)
mec_irq(5);
- return (0x700 | (uint32) bq[bind++]);
+ return (0x700 | (uint32_t) bq[bind++]);
} else {
- return (0x600 | (uint32) bq[bind]);
+ return (0x600 | (uint32_t) bq[bind]);
}
}
@@ -1161,7 +1161,7 @@ read_uart(uint32 addr)
}
static void
-write_uart(uint32 addr, uint32 data)
+write_uart(uint32_t addr, uint32_t data)
{
unsigned char c;
@@ -1278,7 +1278,7 @@ ATTRIBUTE_UNUSED
static void
uart_rx(void *arg)
{
- int32 rsize;
+ int32_t rsize;
char rxd;
@@ -1411,20 +1411,20 @@ rtc_start(void)
rtc_enabled = 1;
}
-static uint32
+static uint32_t
rtc_counter_read(void)
{
return rtc_counter;
}
static void
-rtc_scaler_set(uint32 val)
+rtc_scaler_set(uint32_t val)
{
rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
}
static void
-rtc_reload_set(uint32 val)
+rtc_reload_set(uint32_t val)
{
rtc_reload = val;
}
@@ -1461,26 +1461,26 @@ gpt_start(void)
gpt_enabled = 1;
}
-static uint32
+static uint32_t
gpt_counter_read(void)
{
return gpt_counter;
}
static void
-gpt_scaler_set(uint32 val)
+gpt_scaler_set(uint32_t val)
{
gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
}
static void
-gpt_reload_set(uint32 val)
+gpt_reload_set(uint32_t val)
{
gpt_reload = val;
}
static void
-timer_ctrl(uint32 val)
+timer_ctrl(uint32_t val)
{
rtc_cr = ((val & TCR_TCRCR) != 0);
@@ -1512,8 +1512,8 @@ timer_ctrl(uint32 val)
wait-states. */
static void
-store_bytes (unsigned char *mem, uint32 waddr, uint32 *data, int32 sz,
- int32 *ws)
+store_bytes (unsigned char *mem, uint32_t waddr, uint32_t *data, int32_t sz,
+ int32_t *ws)
{
switch (sz) {
case 0:
@@ -1543,9 +1543,9 @@ store_bytes (unsigned char *mem, uint32 waddr, uint32 *data, int32 sz,
/* Memory emulation */
int
-memory_iread (uint32 addr, uint32 *data, uint32 *ws)
+memory_iread (uint32_t addr, uint32_t *data, uint32_t *ws)
{
- uint32 asi;
+ uint32_t asi;
if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
*ws = mem_ramr_ws;
@@ -1568,9 +1568,9 @@ memory_iread (uint32 addr, uint32 *data, uint32 *ws)
}
int
-memory_read(int32 asi, uint32 addr, void *data, int32 sz, int32 *ws)
+memory_read(int32_t asi, uint32_t addr, void *data, int32_t sz, int32_t *ws)
{
- int32 mexc;
+ int32_t mexc;
#ifdef ERRINJ
if (errmec) {
@@ -1634,13 +1634,13 @@ memory_read(int32 asi, uint32 addr, void *data, int32 sz, int32 *ws)
}
int
-memory_write(int32 asi, uint32 addr, uint32 *data, int32 sz, int32 *ws)
+memory_write(int32_t asi, uint32_t addr, uint32_t *data, int32_t sz, int32_t *ws)
{
- uint32 byte_addr;
- uint32 byte_mask;
- uint32 waddr;
- uint32 *ram;
- int32 mexc;
+ uint32_t byte_addr;
+ uint32_t byte_mask;
+ uint32_t waddr;
+ uint32_t *ram;
+ int32_t mexc;
int i;
int wphit[2];
@@ -1742,7 +1742,7 @@ memory_write(int32 asi, uint32 addr, uint32 *data, int32 sz, int32 *ws)
}
static void *
-get_mem_ptr(uint32 addr, uint32 size)
+get_mem_ptr(uint32_t addr, uint32_t size)
{
if ((addr + size) < ROM_SZ) {
return &romb[addr];
@@ -1761,7 +1761,7 @@ get_mem_ptr(uint32 addr, uint32 size)
}
int
-sis_memory_write(uint32 addr, const void *data, uint32 length)
+sis_memory_write(uint32_t addr, const void *data, uint32_t length)
{
void *mem;
@@ -1773,7 +1773,7 @@ sis_memory_write(uint32 addr, const void *data, uint32 length)
}
int
-sis_memory_read(uint32 addr, void *data, uint32 length)
+sis_memory_read(uint32_t addr, void *data, uint32_t length)
{
char *mem;
diff --git a/sim/erc32/exec.c b/sim/erc32/exec.c
index cf733cc5f850..ef93692e7a26 100644
--- a/sim/erc32/exec.c
+++ b/sim/erc32/exec.c
@@ -23,7 +23,7 @@
#include <math.h>
#include <stdio.h>
-extern int32 sis_verbose, sparclite;
+extern int32_t sis_verbose, sparclite;
int ext_irl = 0;
/* Load/store interlock delay */
@@ -218,25 +218,25 @@ int ext_irl = 0;
/* Forward declarations */
-static uint32 sub_cc (uint32 psr, int32 operand1, int32 operand2,
- int32 result);
-static uint32 add_cc (uint32 psr, int32 operand1, int32 operand2,
- int32 result);
-static void log_cc (int32 result, struct pstate *sregs);
-static int fpexec (uint32 op3, uint32 rd, uint32 rs1, uint32 rs2,
+static uint32_t sub_cc (uint32_t psr, int32_t operand1, int32_t operand2,
+ int32_t result);
+static uint32_t add_cc (uint32_t psr, int32_t operand1, int32_t operand2,
+ int32_t result);
+static void log_cc (int32_t result, struct pstate *sregs);
+static int fpexec (uint32_t op3, uint32_t rd, uint32_t rs1, uint32_t rs2,
struct pstate *sregs);
-static int chk_asi (struct pstate *sregs, uint32 *asi, uint32 op3);
+static int chk_asi (struct pstate *sregs, uint32_t *asi, uint32_t op3);
extern struct estate ebase;
-extern int32 nfp,ift;
+extern int32_t nfp,ift;
#ifdef ERRINJ
-extern uint32 errtt, errftt;
+extern uint32_t errtt, errftt;
#endif
-static uint32
-sub_cc(uint32 psr, int32 operand1, int32 operand2, int32 result)
+static uint32_t
+sub_cc(uint32_t psr, int32_t operand1, int32_t operand2, int32_t result)
{
psr = ((psr & ~PSR_N) | ((result >> 8) & PSR_N));
if (result)
@@ -250,8 +250,8 @@ sub_cc(uint32 psr, int32 operand1, int32 operand2, int32 result)
return psr;
}
-uint32
-add_cc(uint32 psr, int32 operand1, int32 operand2, int32 result)
+uint32_t
+add_cc(uint32_t psr, int32_t operand1, int32_t operand2, int32_t result)
{
psr = ((psr & ~PSR_N) | ((result >> 8) & PSR_N));
if (result)
@@ -266,7 +266,7 @@ add_cc(uint32 psr, int32 operand1, int32 operand2, int32 result)
}
static void
-log_cc(int32 result, struct pstate *sregs)
+log_cc(int32_t result, struct pstate *sregs)
{
sregs->psr &= ~(PSR_CC); /* Zero CC bits */
sregs->psr = (sregs->psr | ((result >> 8) & PSR_N));
@@ -276,10 +276,10 @@ log_cc(int32 result, struct pstate *sregs)
/* Add two unsigned 32-bit integers, and calculate the carry out. */
-static uint32
-add32 (uint32 n1, uint32 n2, int *carry)
+static uint32_t
+add32 (uint32_t n1, uint32_t n2, int *carry)
{
- uint32 result = n1 + n2;
+ uint32_t result = n1 + n2;
*carry = result < n1 || result < n2;
return result;
@@ -288,9 +288,9 @@ add32 (uint32 n1, uint32 n2, int *carry)
/* Multiply two 32-bit integers. */
static void
-mul64 (uint32 n1, uint32 n2, uint32 *result_hi, uint32 *result_lo, int msigned)
+mul64 (uint32_t n1, uint32_t n2, uint32_t *result_hi, uint32_t *result_lo, int msigned)
{
- uint32 lo, mid1, mid2, hi, reg_lo, reg_hi;
+ uint32_t lo, mid1, mid2, hi, reg_lo, reg_hi;
int carry;
int sign = 0;
@@ -338,52 +338,52 @@ mul64 (uint32 n1, uint32 n2, uint32 *result_hi, uint32 *result_lo, int msigned)
that the host compiler supports long long operations. */
static void
-div64 (uint32 n1_hi, uint32 n1_low, uint32 n2, uint32 *result, int msigned)
+div64 (uint32_t n1_hi, uint32_t n1_low, uint32_t n2, uint32_t *result, int msigned)
{
- uint64 n1;
+ uint64_t n1;
- n1 = ((uint64) n1_hi) << 32;
- n1 |= ((uint64) n1_low) & 0xffffffff;
+ n1 = ((uint64_t) n1_hi) << 32;
+ n1 |= ((uint64_t) n1_low) & 0xffffffff;
if (msigned)
{
- int64 n1_s = (int64) n1;
- int32 n2_s = (int32) n2;
+ int64_t n1_s = (int64_t) n1;
+ int32_t n2_s = (int32_t) n2;
n1_s = n1_s / n2_s;
- n1 = (uint64) n1_s;
+ n1 = (uint64_t) n1_s;
}
else
n1 = n1 / n2;
- *result = (uint32) (n1 & 0xffffffff);
+ *result = (uint32_t) (n1 & 0xffffffff);
}
static int
-extract_short (uint32 data, uint32 address)
+extract_short (uint32_t data, uint32_t address)
{
return ((data >> ((2 - (address & 2)) * 8)) & 0xffff);
}
static int
-extract_short_signed (uint32 data, uint32 address)
+extract_short_signed (uint32_t data, uint32_t address)
{
- uint32 tmp = ((data >> ((2 - (address & 2)) * 8)) & 0xffff);
+ uint32_t tmp = ((data >> ((2 - (address & 2)) * 8)) & 0xffff);
if (tmp & 0x8000)
tmp |= 0xffff0000;
return tmp;
}
static int
-extract_byte (uint32 data, uint32 address)
+extract_byte (uint32_t data, uint32_t address)
{
return ((data >> ((3 - (address & 3)) * 8)) & 0xff);
}
static int
-extract_byte_signed (uint32 data, uint32 address)
+extract_byte_signed (uint32_t data, uint32_t address)
{
- uint32 tmp = ((data >> ((3 - (address & 3)) * 8)) & 0xff);
+ uint32_t tmp = ((data >> ((3 - (address & 3)) * 8)) & 0xff);
if (tmp & 0x80)
tmp |= 0xffffff00;
return tmp;
@@ -393,13 +393,13 @@ int
dispatch_instruction(struct pstate *sregs)
{
- uint32 cwp, op, op2, op3, asi, rd, cond, rs1,
+ uint32_t cwp, op, op2, op3, asi, rd, cond, rs1,
rs2;
- uint32 ldep, icc, data, *rdd;
- int32 operand1, operand2, result, eicc,
+ uint32_t ldep, icc, data, *rdd;
+ int32_t operand1, operand2, result, eicc,
new_cwp;
- int32 pc, npc, address, ws, mexc, fcc;
- uint32 ddata[2];
+ int32_t pc, npc, address, ws, mexc, fcc;
+ uint32_t ddata[2];
sregs->ninst++;
cwp = ((sregs->psr & PSR_CWP) << 4);
@@ -707,7 +707,7 @@ dispatch_instruction(struct pstate *sregs)
case DIVScc:
{
int sign;
- uint32 result, remainder;
+ uint32_t result, remainder;
int c0, y31;
if (!sparclite) {
@@ -733,8 +733,8 @@ dispatch_instruction(struct pstate *sregs)
even in cases where the divisor is subtracted
from the remainder. FIXME: get the true story
from Fujitsu. */
- c0 = result < (uint32) remainder
- || result < (uint32) operand2;
+ c0 = result < (uint32_t) remainder
+ || result < (uint32_t) operand2;
if (result & 0x80000000)
sregs->psr |= PSR_N;
@@ -773,7 +773,7 @@ dispatch_instruction(struct pstate *sregs)
break;
case SMULCC:
{
- uint32 result;
+ uint32_t result;
mul64 (rs1, operand2, &sregs->y, &result, 1);
@@ -797,7 +797,7 @@ dispatch_instruction(struct pstate *sregs)
break;
case UMULCC:
{
- uint32 result;
+ uint32_t result;
mul64 (rs1, operand2, &sregs->y, &result, 0);
@@ -831,7 +831,7 @@ dispatch_instruction(struct pstate *sregs)
break;
case SDIVCC:
{
- uint32 result;
+ uint32_t result;
if (sparclite) {
sregs->trap = TRAP_UNIMP;
@@ -878,7 +878,7 @@ dispatch_instruction(struct pstate *sregs)
break;
case UDIVCC:
{
- uint32 result;
+ uint32_t result;
if (sparclite) {
sregs->trap = TRAP_UNIMP;
@@ -1168,7 +1168,7 @@ dispatch_instruction(struct pstate *sregs)
case SCAN:
{
- uint32 result, mask;
+ uint32_t result, mask;
int i;
if (!sparclite) {
@@ -1528,7 +1528,7 @@ dispatch_instruction(struct pstate *sregs)
if (sregs->frd == rd)
sregs->fhold += (sregs->ftime - ebase.simtime);
}
- mexc = memory_write(asi, address, (uint32 *)&sregs->fsi[rd], 2, &ws);
+ mexc = memory_write(asi, address, (uint32_t *)&sregs->fsi[rd], 2, &ws);
sregs->hold += ws;
if (mexc) {
sregs->trap = TRAP_DEXC;
@@ -1548,7 +1548,7 @@ dispatch_instruction(struct pstate *sregs)
if ((sregs->frd == rd) || (sregs->frd + 1 == rd))
sregs->fhold += (sregs->ftime - ebase.simtime);
}
- mexc = memory_write(asi, address, (uint32 *)&sregs->fsi[rd], 3, &ws);
+ mexc = memory_write(asi, address, (uint32_t *)&sregs->fsi[rd], 3, &ws);
sregs->hold += ws;
sregs->icnt = T_STD;
#ifdef STAT
@@ -1662,11 +1662,11 @@ dispatch_instruction(struct pstate *sregs)
static int
-fpexec(uint32 op3, uint32 rd, uint32 rs1, uint32 rs2, struct pstate *sregs)
+fpexec(uint32_t op3, uint32_t rd, uint32_t rs1, uint32_t rs2, struct pstate *sregs)
{
- uint32 opf, tem, accex;
- int32 fcc;
- uint32 ldadj;
+ uint32_t opf, tem, accex;
+ int32_t fcc;
+ uint32_t ldadj;
if (sregs->fpstate == FP_EXC_MODE) {
sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_SEQ_ERR;
@@ -1941,7 +1941,7 @@ fpexec(uint32 op3, uint32 rd, uint32 rs1, uint32 rs2, struct pstate *sregs)
}
static int
-chk_asi(struct pstate *sregs, uint32 *asi, uint32 op3)
+chk_asi(struct pstate *sregs, uint32_t *asi, uint32_t op3)
{
if (!(sregs->psr & PSR_S)) {
sregs->trap = TRAP_PRIVI;
@@ -1957,7 +1957,7 @@ chk_asi(struct pstate *sregs, uint32 *asi, uint32 op3)
int
execute_trap(struct pstate *sregs)
{
- int32 cwp;
+ int32_t cwp;
if (sregs->trap == 256) {
sregs->pc = 0;
@@ -2042,10 +2042,10 @@ init_regs(struct pstate *sregs)
sregs->g[0] = 0;
#ifdef HOST_LITTLE_ENDIAN
sregs->fdp = (float32 *) sregs->fd;
- sregs->fsi = (int32 *) sregs->fs;
+ sregs->fsi = (int32_t *) sregs->fs;
#else
sregs->fs = (float32 *) sregs->fd;
- sregs->fsi = (int32 *) sregs->fd;
+ sregs->fsi = (int32_t *) sregs->fd;
#endif
sregs->fsr = 0;
sregs->fpu_pres = !nfp;
diff --git a/sim/erc32/float.c b/sim/erc32/float.c
index a79cb1491437..1a0c272d6479 100644
--- a/sim/erc32/float.c
+++ b/sim/erc32/float.c
@@ -62,7 +62,7 @@ clear_accex(void)
/* How to map SPARC FSR onto the host */
void
-set_fsr(uint32 fsr)
+set_fsr(uint32_t fsr)
{
int fround;
diff --git a/sim/erc32/func.c b/sim/erc32/func.c
index d1b7e2e46d83..b4f2b420e345 100644
--- a/sim/erc32/func.c
+++ b/sim/erc32/func.c
@@ -49,28 +49,28 @@ int sparclite_board = 0; /* emulating SPARClite board RAM? */
char uart_dev1[128] = "";
char uart_dev2[128] = "";
extern int ext_irl;
-uint32 last_load_addr = 0;
+uint32_t last_load_addr = 0;
#ifdef ERRINJ
-uint32 errcnt = 0;
-uint32 errper = 0;
-uint32 errtt = 0;
-uint32 errftt = 0;
-uint32 errmec = 0;
+uint32_t errcnt = 0;
+uint32_t errper = 0;
+uint32_t errtt = 0;
+uint32_t errftt = 0;
+uint32_t errmec = 0;
#endif
/* Forward declarations */
static int batch (struct pstate *sregs, char *fname);
-static void set_rega (struct pstate *sregs, char *reg, uint32 rval);
+static void set_rega (struct pstate *sregs, char *reg, uint32_t rval);
static void disp_reg (struct pstate *sregs, char *reg);
-static uint32 limcalc (float32 freq);
-static void int_handler (int32 sig);
+static uint32_t limcalc (float32 freq);
+static void int_handler (int32_t sig);
static void init_event (void);
static int disp_fpu (struct pstate *sregs);
static void disp_regs (struct pstate *sregs, int cwp);
static void disp_ctrl (struct pstate *sregs);
-static void disp_mem (uint32 addr, uint32 len);
+static void disp_mem (uint32_t addr, uint32_t len);
static int
batch(struct pstate *sregs, char *fname)
@@ -98,9 +98,9 @@ batch(struct pstate *sregs, char *fname)
}
void
-set_regi(struct pstate *sregs, int32 reg, uint32 rval)
+set_regi(struct pstate *sregs, int32_t reg, uint32_t rval)
{
- uint32 cwp;
+ uint32_t cwp;
cwp = ((sregs->psr & 0x7) << 4);
if ((reg > 0) && (reg < 8)) {
@@ -139,10 +139,10 @@ set_regi(struct pstate *sregs, int32 reg, uint32 rval)
}
void
-get_regi(struct pstate * sregs, int32 reg, unsigned char *buf)
+get_regi(struct pstate * sregs, int32_t reg, unsigned char *buf)
{
- uint32 cwp;
- uint32 rval = 0;
+ uint32_t cwp;
+ uint32_t rval = 0;
cwp = ((sregs->psr & 0x7) << 4);
if ((reg >= 0) && (reg < 8)) {
@@ -185,10 +185,10 @@ get_regi(struct pstate * sregs, int32 reg, unsigned char *buf)
static void
-set_rega(struct pstate *sregs, char *reg, uint32 rval)
+set_rega(struct pstate *sregs, char *reg, uint32_t rval)
{
- uint32 cwp;
- int32 err = 0;
+ uint32_t cwp;
+ int32_t err = 0;
cwp = ((sregs->psr & 0x7) << 4);
if (strcmp(reg, "psr") == 0)
@@ -329,10 +329,10 @@ errinjstart()
#endif
-static uint32
+static uint32_t
limcalc (float32 freq)
{
- uint32 unit, lim;
+ uint32_t unit, lim;
double flim;
char *cmd1, *cmd2;
@@ -348,7 +348,7 @@ limcalc (float32 freq)
flim = (double) lim * (double) unit * (double) freq +
(double) ebase.simtime;
if ((flim > ebase.simtime) && (flim < 4294967296.0)) {
- lim = (uint32) flim;
+ lim = (uint32_t) flim;
} else {
printf("error in expression\n");
lim = -1;
@@ -361,9 +361,9 @@ int
exec_cmd(struct pstate *sregs, const char *cmd)
{
char *cmd1, *cmd2;
- int32 stat;
- uint32 len, i, clen, j;
- static uint32 daddr = 0;
+ int32_t stat;
+ uint32_t len, i, clen, j;
+ static uint32_t daddr = 0;
char *cmdsave, *cmdsave2 = NULL;
stat = OK;
@@ -563,8 +563,8 @@ exec_cmd(struct pstate *sregs, const char *cmd)
sim_halt();
} else if (strncmp(cmd1, "tlimit", clen) == 0) {
sregs->tlimit = limcalc(sregs->freq);
- if (sregs->tlimit != (uint32) -1)
- printf("simulation limit = %u (%.3f ms)\n",(uint32) sregs->tlimit,
+ if (sregs->tlimit != (uint32_t) -1)
+ printf("simulation limit = %u (%.3f ms)\n",(uint32_t) sregs->tlimit,
sregs->tlimit / sregs->freq / 1000);
} else if (strncmp(cmd1, "tra", clen) == 0) {
if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
@@ -614,8 +614,8 @@ reset_stat(struct pstate *sregs)
void
show_stat(struct pstate *sregs)
{
- uint32 iinst;
- uint32 stime;
+ uint32_t iinst;
+ uint32_t stime;
if (sregs->tottime == 0.0)
sregs->tottime += 1E-6;
@@ -677,7 +677,7 @@ init_bpt(struct pstate *sregs)
}
static void
-int_handler(int32 sig)
+int_handler(int32_t sig)
{
if (sig != 2)
printf("\n\n Signal handler error (%d)\n\n", sig);
@@ -743,7 +743,7 @@ disp_regs(struct pstate *sregs, int cwp)
}
}
-static void print_insn_sparc_sis(uint32 addr, struct disassemble_info *info)
+static void print_insn_sparc_sis(uint32_t addr, struct disassemble_info *info)
{
unsigned char i[4];
@@ -758,7 +758,7 @@ static void
disp_ctrl(struct pstate *sregs)
{
- uint32 i;
+ uint32_t i;
printf("\n psr: %08X wim: %08X tbr: %08X y: %08X\n",
sregs->psr, sregs->wim, sregs->tbr, sregs->y);
@@ -774,15 +774,15 @@ disp_ctrl(struct pstate *sregs)
}
static void
-disp_mem(uint32 addr, uint32 len)
+disp_mem(uint32_t addr, uint32_t len)
{
- uint32 i;
+ uint32_t i;
union {
unsigned char u8[4];
- uint32 u32;
+ uint32_t u32;
} data;
- uint32 mem[4], j;
+ uint32_t mem[4], j;
char *p;
for (i = addr & ~3; i < ((addr + len) & ~3); i += 16) {
@@ -805,12 +805,12 @@ disp_mem(uint32 addr, uint32 len)
}
void
-dis_mem(uint32 addr, uint32 len, struct disassemble_info *info)
+dis_mem(uint32_t addr, uint32_t len, struct disassemble_info *info)
{
- uint32 i;
+ uint32_t i;
union {
unsigned char u8[4];
- uint32 u32;
+ uint32_t u32;
} data;
for (i = addr & -3; i < ((addr & -3) + (len << 2)); i += 4) {
@@ -825,7 +825,7 @@ dis_mem(uint32 addr, uint32 len, struct disassemble_info *info)
/* Add event to event queue */
void
-event(void (*cfunc) (), int32 arg, uint64 delta)
+event(void (*cfunc) (), int32_t arg, uint64_t delta)
{
struct evcell *ev1, *evins;
@@ -863,7 +863,7 @@ stop_event()
void
init_event(void)
{
- int32 i;
+ int32_t i;
ebase.eq.nxt = NULL;
ebase.freeq = evbuf;
@@ -874,7 +874,7 @@ init_event(void)
}
void
-set_int(int32 level, void (*callback) (), int32 arg)
+set_int(int32_t level, void (*callback) (), int32_t arg)
{
irqarr[level & 0x0f].callback = callback;
irqarr[level & 0x0f].arg = arg;
@@ -888,8 +888,8 @@ advance_time(struct pstate *sregs)
struct evcell *evrem;
void (*cfunc) ();
- uint32 arg;
- uint64 endtime;
+ uint32_t arg;
+ uint64_t endtime;
#ifdef STAT
sregs->fholdt += sregs->fhold;
@@ -913,7 +913,7 @@ advance_time(struct pstate *sregs)
}
-uint32
+uint32_t
now(void)
{
return ebase.simtime;
@@ -927,8 +927,8 @@ wait_for_irq(void)
{
struct evcell *evrem;
void (*cfunc) ();
- int32 arg;
- uint64 endtime;
+ int32_t arg;
+ uint64_t endtime;
if (ebase.eq.nxt == NULL)
printf("Warning: event queue empty - power-down mode not entered\n");
@@ -954,11 +954,11 @@ wait_for_irq(void)
int
check_bpt(struct pstate *sregs)
{
- int32 i;
+ int32_t i;
if ((sregs->bphit) || (sregs->annul))
return 0;
- for (i = 0; i < (int32) sregs->bptnum; i++) {
+ for (i = 0; i < (int32_t) sregs->bptnum; i++) {
if (sregs->pc == sregs->bpts[i])
return BPT_HIT;
}
diff --git a/sim/erc32/interf.c b/sim/erc32/interf.c
index 9ab2582c8de2..d04d07c08c86 100644
--- a/sim/erc32/interf.c
+++ b/sim/erc32/interf.c
@@ -62,7 +62,7 @@ int sis_gdb_break = 1;
host_callback *sim_callback;
int
-run_sim(struct pstate *sregs, uint64 icount, int dis)
+run_sim(struct pstate *sregs, uint64_t icount, int dis)
{
int mexc, irq;
@@ -400,13 +400,13 @@ flush_windows (void)
for (win = invwin; ; win = (win - 1) & PSR_CWP)
{
- uint32 sp;
+ uint32_t sp;
int i;
sp = sregs.r[(win * 16 + 14) & 0x7f];
#if 1
if (sis_verbose > 2) {
- uint32 fp = sregs.r[(win * 16 + 30) & 0x7f];
+ uint32_t fp = sregs.r[(win * 16 + 30) & 0x7f];
printf("flush_window: win %d, sp %x, fp %x\n", win, sp, fp);
}
#endif
diff --git a/sim/erc32/sis.c b/sim/erc32/sis.c
index 90573866dada..66a27d075064 100644
--- a/sim/erc32/sis.c
+++ b/sim/erc32/sis.c
@@ -60,14 +60,14 @@ extern int sparclite;
extern int dumbio;
extern char uart_dev1[];
extern char uart_dev2[];
-extern uint32 last_load_addr;
+extern uint32_t last_load_addr;
#ifdef ERA
extern int era;
#endif
int
-run_sim(struct pstate *sregs, uint64 icount, int dis)
+run_sim(struct pstate *sregs, uint64_t icount, int dis)
{
int irq, mexc, deb;
diff --git a/sim/erc32/sis.h b/sim/erc32/sis.h
index b230a0337411..33f16c77ca47 100644
--- a/sim/erc32/sis.h
+++ b/sim/erc32/sis.h
@@ -45,16 +45,9 @@ struct histype {
/* type definitions */
-typedef short int int16; /* 16-bit signed int */
-typedef unsigned short int uint16; /* 16-bit unsigned int */
-typedef int int32; /* 32-bit signed int */
-typedef unsigned int uint32; /* 32-bit unsigned int */
typedef float float32; /* 32-bit float */
typedef double float64; /* 64-bit float */
-typedef uint64_t uint64; /* 64-bit unsigned int */
-typedef int64_t int64; /* 64-bit signed int */
-
struct pstate {
float64 fd[16]; /* FPU registers */
@@ -64,66 +57,66 @@ struct pstate {
#else
float32 *fs;
#endif
- int32 *fsi;
- uint32 fsr;
- int32 fpstate;
- uint32 fpq[FPUQN * 2];
- uint32 fpqn;
- uint32 ftime;
- uint32 flrd;
- uint32 frd;
- uint32 frs1;
- uint32 frs2;
- uint32 fpu_pres; /* FPU present (0 = No, 1 = Yes) */
-
- uint32 psr; /* IU registers */
- uint32 tbr;
- uint32 wim;
- uint32 g[8];
- uint32 r[128];
- uint32 y;
- uint32 asr17; /* Single vector trapping */
- uint32 pc, npc;
-
-
- uint32 trap; /* Current trap type */
- uint32 annul; /* Instruction annul */
- uint32 data; /* Loaded data */
- uint32 inst; /* Current instruction */
- uint32 asi; /* Current ASI */
- uint32 err_mode; /* IU error mode */
- uint32 breakpoint;
- uint32 bptnum;
- uint32 bphit;
- uint32 bpts[BPT_MAX]; /* Breakpoints */
-
- uint32 ltime; /* Load interlock time */
- uint32 hold; /* IU hold cycles in current inst */
- uint32 fhold; /* FPU hold cycles in current inst */
- uint32 icnt; /* Instruction cycles in curr inst */
-
- uint32 histlen; /* Trace history management */
- uint32 histind;
+ int32_t *fsi;
+ uint32_t fsr;
+ int32_t fpstate;
+ uint32_t fpq[FPUQN * 2];
+ uint32_t fpqn;
+ uint32_t ftime;
+ uint32_t flrd;
+ uint32_t frd;
+ uint32_t frs1;
+ uint32_t frs2;
+ uint32_t fpu_pres; /* FPU present (0 = No, 1 = Yes) */
+
+ uint32_t psr; /* IU registers */
+ uint32_t tbr;
+ uint32_t wim;
+ uint32_t g[8];
+ uint32_t r[128];
+ uint32_t y;
+ uint32_t asr17; /* Single vector trapping */
+ uint32_t pc, npc;
+
+
+ uint32_t trap; /* Current trap type */
+ uint32_t annul; /* Instruction annul */
+ uint32_t data; /* Loaded data */
+ uint32_t inst; /* Current instruction */
+ uint32_t asi; /* Current ASI */
+ uint32_t err_mode; /* IU error mode */
+ uint32_t breakpoint;
+ uint32_t bptnum;
+ uint32_t bphit;
+ uint32_t bpts[BPT_MAX]; /* Breakpoints */
+
+ uint32_t ltime; /* Load interlock time */
+ uint32_t hold; /* IU hold cycles in current inst */
+ uint32_t fhold; /* FPU hold cycles in current inst */
+ uint32_t icnt; /* Instruction cycles in curr inst */
+
+ uint32_t histlen; /* Trace history management */
+ uint32_t histind;
struct histype *histbuf;
float32 freq; /* Simulated processor frequency */
double tottime;
- uint64 ninst;
- uint64 fholdt;
- uint64 holdt;
- uint64 icntt;
- uint64 finst;
- uint64 simstart;
+ uint64_t ninst;
+ uint64_t fholdt;
+ uint64_t holdt;
+ uint64_t icntt;
+ uint64_t finst;
+ uint64_t simstart;
double starttime;
- uint64 tlimit; /* Simulation time limit */
- uint64 pwdtime; /* Cycles in power-down mode */
- uint64 nstore; /* Number of load instructions */
- uint64 nload; /* Number of store instructions */
- uint64 nannul; /* Number of annuled instructions */
- uint64 nbranch; /* Number of branch instructions */
- uint32 ildreg; /* Destination of last load instruction */
- uint64 ildtime; /* Last time point for load dependency */
+ uint64_t tlimit; /* Simulation time limit */
+ uint64_t pwdtime; /* Cycles in power-down mode */
+ uint64_t nstore; /* Number of load instructions */
+ uint64_t nload; /* Number of store instructions */
+ uint64_t nannul; /* Number of annuled instructions */
+ uint64_t nbranch; /* Number of branch instructions */
+ uint32_t ildreg; /* Destination of last load instruction */
+ uint64_t ildtime; /* Last time point for load dependency */
int rett_err; /* IU in jmpl/restore error state (Rev.0) */
int jmpltime;
@@ -131,20 +124,20 @@ struct pstate {
struct evcell {
void (*cfunc) ();
- int32 arg;
- uint64 time;
+ int32_t arg;
+ uint64_t time;
struct evcell *nxt;
};
struct estate {
struct evcell eq;
struct evcell *freeq;
- uint64 simtime;
+ uint64_t simtime;
};
struct irqcell {
void (*callback) ();
- int32 arg;
+ int32_t arg;
};
@@ -159,27 +152,27 @@ struct irqcell {
/* erc32.c */
extern void init_sim (void);
extern void reset (void);
-extern void error_mode (uint32 pc);
+extern void error_mode (uint32_t pc);
extern void sim_halt (void);
extern void exit_sim (void);
extern void init_stdio (void);
extern void restore_stdio (void);
-extern int memory_iread (uint32 addr, uint32 *data, uint32 *ws);
-extern int memory_read (int32 asi, uint32 addr, void *data,
- int32 sz, int32 *ws);
-extern int memory_write (int32 asi, uint32 addr, uint32 *data,
- int32 sz, int32 *ws);
-extern int sis_memory_write (uint32 addr,
- const void *data, uint32 length);
-extern int sis_memory_read (uint32 addr, void *data,
- uint32 length);
+extern int memory_iread (uint32_t addr, uint32_t *data, uint32_t *ws);
+extern int memory_read (int32_t asi, uint32_t addr, void *data,
+ int32_t sz, int32_t *ws);
+extern int memory_write (int32_t asi, uint32_t addr, uint32_t *data,
+ int32_t sz, int32_t *ws);
+extern int sis_memory_write (uint32_t addr,
+ const void *data, uint32_t length);
+extern int sis_memory_read (uint32_t addr, void *data,
+ uint32_t length);
extern void boot_init (void);
/* func.c */
extern struct pstate sregs;
-extern void set_regi (struct pstate *sregs, int32 reg,
- uint32 rval);
-extern void get_regi (struct pstate *sregs, int32 reg, unsigned char *buf);
+extern void set_regi (struct pstate *sregs, int32_t reg,
+ uint32_t rval);
+extern void get_regi (struct pstate *sregs, int32_t reg, unsigned char *buf);
extern int exec_cmd (struct pstate *sregs, const char *cmd);
extern void reset_stat (struct pstate *sregs);
extern void show_stat (struct pstate *sregs);
@@ -187,12 +180,12 @@ extern void init_bpt (struct pstate *sregs);
extern void init_signals (void);
struct disassemble_info;
-extern void dis_mem (uint32 addr, uint32 len,
+extern void dis_mem (uint32_t addr, uint32_t len,
struct disassemble_info *info);
-extern void event (void (*cfunc) (), int32 arg, uint64 delta);
-extern void set_int (int32 level, void (*callback) (), int32 arg);
+extern void event (void (*cfunc) (), int32_t arg, uint64_t delta);
+extern void set_int (int32_t level, void (*callback) (), int32_t arg);
extern void advance_time (struct pstate *sregs);
-extern uint32 now (void);
+extern uint32_t now (void);
extern int wait_for_irq (void);
extern int check_bpt (struct pstate *sregs);
extern void reset_all (void);
@@ -209,12 +202,12 @@ extern void init_regs (struct pstate *sregs);
/* interf.c */
extern int run_sim (struct pstate *sregs,
- uint64 icount, int dis);
+ uint64_t icount, int dis);
/* float.c */
extern int get_accex (void);
extern void clear_accex (void);
-extern void set_fsr (uint32 fsr);
+extern void set_fsr (uint32_t fsr);
/* help.c */
extern void usage (void);
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 07/17] sim: testsuite: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (4 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 06/17] sim: erc32: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 08/17] sim: bfin: " Mike Frysinger
` (9 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
This old code setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.
---
sim/testsuite/common/alu-n-tst.h | 2 +-
sim/testsuite/common/alu-tst.c | 16 ++++++++--------
sim/testsuite/common/bits-gen.c | 4 ++--
sim/testsuite/common/fpu-tst.c | 16 ++++++++--------
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/sim/testsuite/common/alu-n-tst.h b/sim/testsuite/common/alu-n-tst.h
index cd218d4339d6..14abe86e8a7d 100644
--- a/sim/testsuite/common/alu-n-tst.h
+++ b/sim/testsuite/common/alu-n-tst.h
@@ -5,7 +5,7 @@
#include "symcat.h"
/* NOTE: see end of file for #undef of these macros */
-#define unsignedN XCONCAT2(unsigned,N)
+#define unsignedN XCONCAT3(uint,N,_t)
#define MAX_INT XCONCAT2(MAX_INT,N)
#define MIN_INT XCONCAT2(MIN_INT,N)
#define alu_N_tests XCONCAT3(alu_,N,_tests)
diff --git a/sim/testsuite/common/alu-tst.c b/sim/testsuite/common/alu-tst.c
index 110427f62d8a..63042cfe6b5e 100644
--- a/sim/testsuite/common/alu-tst.c
+++ b/sim/testsuite/common/alu-tst.c
@@ -27,13 +27,13 @@
typedef struct {
char *op;
- unsigned64 arg;
+ uint64_t arg;
} alu_op;
typedef struct {
- unsigned64 begin;
+ uint64_t begin;
alu_op ops[4];
- unsigned64 result;
+ uint64_t result;
int carry_borrow;
int overflow;
} alu_test;
@@ -51,21 +51,21 @@ typedef struct {
#define MIN_INT64 UNSIGNED64 (0x8000000000000000)
static void
-print_hex (unsigned64 val, int nr_bits)
+print_hex (uint64_t val, int nr_bits)
{
switch (nr_bits)
{
case 8:
- printf ("0x%02lx", (long) (unsigned8) (val));
+ printf ("0x%02lx", (long) (uint8_t) (val));
break;
case 16:
- printf ("0x%04lx", (long) (unsigned16) (val));
+ printf ("0x%04lx", (long) (uint16_t) (val));
break;
case 32:
- printf ("0x%08lx", (long) (unsigned32) (val));
+ printf ("0x%08lx", (long) (uint32_t) (val));
break;
case 64:
- printf ("0x%016llx", (long long) (unsigned64) (val));
+ printf ("0x%016llx", (long long) (uint64_t) (val));
break;
default:
abort ();
diff --git a/sim/testsuite/common/bits-gen.c b/sim/testsuite/common/bits-gen.c
index 5f35247f7f27..d1787fc608ad 100644
--- a/sim/testsuite/common/bits-gen.c
+++ b/sim/testsuite/common/bits-gen.c
@@ -30,8 +30,8 @@ gen_struct (void)
printf (" int line;\n");
printf (" int row;\n");
printf (" int col;\n");
- printf (" unsigned64 val;\n");
- printf (" unsigned64 check;\n");
+ printf (" uint64_t val;\n");
+ printf (" uint64_t check;\n");
printf ("} test_tuples;\n");
printf ("\n");
printf ("typedef struct _test_spec {\n");
diff --git a/sim/testsuite/common/fpu-tst.c b/sim/testsuite/common/fpu-tst.c
index d347e12727d7..5ae1e084d34e 100644
--- a/sim/testsuite/common/fpu-tst.c
+++ b/sim/testsuite/common/fpu-tst.c
@@ -25,7 +25,7 @@ do { \
static int flags;
-int8
+int8_t
syst_float_flags_clear ()
{
int old_flags = 0;
@@ -72,7 +72,7 @@ syst_float_flags_clear ()
sim_fpu_round rounding_mode;
void
-syst_float_set_rounding_mode(int8 mode)
+syst_float_set_rounding_mode(int8_t mode)
{
switch (mode)
{
@@ -93,7 +93,7 @@ syst_float_set_rounding_mode(int8 mode)
float32
-syst_int32_to_float32(int32 a)
+syst_int32_to_float32(int32_t a)
{
float32 z;
sim_fpu s;
@@ -104,7 +104,7 @@ syst_int32_to_float32(int32 a)
}
float64
-syst_int32_to_float64( int32 a )
+syst_int32_to_float64( int32_t a )
{
float64 z;
sim_fpu s;
@@ -113,10 +113,10 @@ syst_int32_to_float64( int32 a )
return z;
}
-int32
+int32_t
syst_float32_to_int32_round_to_zero( float32 a )
{
- int32 z;
+ int32_t z;
sim_fpu s;
sim_fpu_32to (&s, a);
flags |= sim_fpu_to32i (&z, &s, sim_fpu_round_zero);
@@ -312,9 +312,9 @@ flag syst_float32_lt_quiet( float32 a, float32 b )
return is;
}
-int32 syst_float64_to_int32_round_to_zero( float64 a )
+int32_t syst_float64_to_int32_round_to_zero( float64 a )
{
- int32 z;
+ int32_t z;
sim_fpu s;
sim_fpu_64to (&s, a);
flags |= sim_fpu_to32i (&z, &s, sim_fpu_round_zero);
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 08/17] sim: bfin: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (5 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 07/17] sim: testsuite: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 09/17] sim: riscv: " Mike Frysinger
` (8 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
Move off the sim-specific unsignedXX types and to the standard uintXX_t
types that C11 provides.
---
sim/bfin/dv-bfin_ctimer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sim/bfin/dv-bfin_ctimer.c b/sim/bfin/dv-bfin_ctimer.c
index b6fbb34f4c3b..64dc5c5af9ff 100644
--- a/sim/bfin/dv-bfin_ctimer.c
+++ b/sim/bfin/dv-bfin_ctimer.c
@@ -30,7 +30,7 @@ struct bfin_ctimer
{
bu32 base;
struct hw_event *handler;
- signed64 timeout;
+ int64_t timeout;
/* Order after here is important -- matches hardware MMR layout. */
bu32 tcntl, tperiod, tscale, tcount;
@@ -84,7 +84,7 @@ static void
bfin_ctimer_update_count (struct hw *me, struct bfin_ctimer *ctimer)
{
bu32 scale, ticks;
- signed64 timeout;
+ int64_t timeout;
/* If the timer was enabled w/out autoreload and has expired, then
there's nothing to calculate here. */
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 09/17] sim: riscv: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (6 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 08/17] sim: bfin: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 10/17] sim: msp430: " Mike Frysinger
` (7 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
Move off the sim-specific unsignedXX types and to the standard uintXX_t
types that C11 provides.
---
sim/riscv/sim-main.c | 56 ++++++++++++++++++++++----------------------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 7b672f6a91db..62f475671c9d 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -131,14 +131,14 @@ store_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg,
static inline unsigned_word
ashiftrt (unsigned_word val, unsigned_word shift)
{
- unsigned32 sign = (val & 0x80000000) ? ~(0xfffffffful >> shift) : 0;
+ uint32_t sign = (val & 0x80000000) ? ~(0xfffffffful >> shift) : 0;
return (val >> shift) | sign;
}
static inline unsigned_word
ashiftrt64 (unsigned_word val, unsigned_word shift)
{
- unsigned64 sign =
+ uint64_t sign =
(val & 0x8000000000000000ull) ? ~(0xffffffffffffffffull >> shift) : 0;
return (val >> shift) | sign;
}
@@ -155,7 +155,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
const char *rs2_name = riscv_gpr_names_abi[rs2];
unsigned int csr = (iw >> OP_SH_CSR) & OP_MASK_CSR;
unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw);
- unsigned_word u_imm = EXTRACT_UTYPE_IMM ((unsigned64) iw);
+ unsigned_word u_imm = EXTRACT_UTYPE_IMM ((uint64_t) iw);
unsigned_word s_imm = EXTRACT_STYPE_IMM (iw);
unsigned_word sb_imm = EXTRACT_BTYPE_IMM (iw);
unsigned_word shamt_imm = ((iw >> OP_SH_SHAMT) & OP_MASK_SHAMT);
@@ -252,7 +252,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
- (unsigned32) cpu->regs[rs1] << (cpu->regs[rs2] & 0x1f)));
+ (uint32_t) cpu->regs[rs1] << (cpu->regs[rs2] & 0x1f)));
break;
case MATCH_SLLI:
TRACE_INSN (cpu, "slli %s, %s, %" PRIiTW "; // %s = %s << %#" PRIxTW,
@@ -265,7 +265,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
TRACE_INSN (cpu, "slliw %s, %s, %" PRIiTW "; // %s = %s << %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
- store_rd (cpu, rd, EXTEND32 ((unsigned32) cpu->regs[rs1] << shamt_imm));
+ store_rd (cpu, rd, EXTEND32 ((uint32_t) cpu->regs[rs1] << shamt_imm));
break;
case MATCH_SRL:
TRACE_INSN (cpu, "srl %s, %s, %s; // %s = %s >> %s",
@@ -278,7 +278,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
- (unsigned32) cpu->regs[rs1] >> (cpu->regs[rs2] & 0x1f)));
+ (uint32_t) cpu->regs[rs1] >> (cpu->regs[rs2] & 0x1f)));
break;
case MATCH_SRLI:
TRACE_INSN (cpu, "srli %s, %s, %" PRIiTW "; // %s = %s >> %#" PRIxTW,
@@ -291,7 +291,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
TRACE_INSN (cpu, "srliw %s, %s, %" PRIiTW "; // %s = %s >> %#" PRIxTW,
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
- store_rd (cpu, rd, EXTEND32 ((unsigned32) cpu->regs[rs1] >> shamt_imm));
+ store_rd (cpu, rd, EXTEND32 ((uint32_t) cpu->regs[rs1] >> shamt_imm));
break;
case MATCH_SRA:
TRACE_INSN (cpu, "sra %s, %s, %s; // %s = %s >>> %s",
@@ -307,7 +307,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
- ashiftrt ((signed32) cpu->regs[rs1], cpu->regs[rs2] & 0x1f)));
+ ashiftrt ((int32_t) cpu->regs[rs1], cpu->regs[rs2] & 0x1f)));
break;
case MATCH_SRAI:
TRACE_INSN (cpu, "srai %s, %s, %" PRIiTW "; // %s = %s >>> %#" PRIxTW,
@@ -327,7 +327,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
store_rd (cpu, rd, EXTEND32 (
- ashiftrt ((signed32) cpu->regs[rs1], shamt_imm)));
+ ashiftrt ((int32_t) cpu->regs[rs1], shamt_imm)));
break;
case MATCH_SLT:
TRACE_INSN (cpu, "slt");
@@ -600,8 +600,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
return pc;
}
-static unsigned64
-mulhu (unsigned64 a, unsigned64 b)
+static uint64_t
+mulhu (uint64_t a, uint64_t b)
{
#ifdef HAVE___INT128
return ((__int128)a * b) >> 64;
@@ -626,16 +626,16 @@ mulhu (unsigned64 a, unsigned64 b)
#endif
}
-static unsigned64
-mulh (signed64 a, signed64 b)
+static uint64_t
+mulh (int64_t a, int64_t b)
{
int negate = (a < 0) != (b < 0);
uint64_t res = mulhu (a < 0 ? -a : a, b < 0 ? -b : b);
return negate ? ~res + (a * b == 0) : res;
}
-static unsigned64
-mulhsu (signed64 a, unsigned64 b)
+static uint64_t
+mulhsu (int64_t a, uint64_t b)
{
int negate = a < 0;
uint64_t res = mulhu (a < 0 ? -a : a, b);
@@ -695,8 +695,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
TRACE_INSN (cpu, "divuw %s, %s, %s; // %s = %s / %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
- if ((unsigned32) cpu->regs[rs2])
- tmp = (unsigned32) cpu->regs[rs1] / (unsigned32) cpu->regs[rs2];
+ if ((uint32_t) cpu->regs[rs2])
+ tmp = (uint32_t) cpu->regs[rs1] / (uint32_t) cpu->regs[rs2];
else
tmp = -1;
store_rd (cpu, rd, EXTEND32 (tmp));
@@ -710,15 +710,15 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
TRACE_INSN (cpu, "mulw %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
- store_rd (cpu, rd, EXTEND32 ((signed32) cpu->regs[rs1]
- * (signed32) cpu->regs[rs2]));
+ store_rd (cpu, rd, EXTEND32 ((int32_t) cpu->regs[rs1]
+ * (int32_t) cpu->regs[rs2]));
break;
case MATCH_MULH:
TRACE_INSN (cpu, "mulh %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
- store_rd (cpu, rd, ((signed64)(signed_word) cpu->regs[rs1]
- * (signed64)(signed_word) cpu->regs[rs2]) >> 32);
+ store_rd (cpu, rd, ((int64_t)(signed_word) cpu->regs[rs1]
+ * (int64_t)(signed_word) cpu->regs[rs2]) >> 32);
else
store_rd (cpu, rd, mulh (cpu->regs[rs1], cpu->regs[rs2]));
break;
@@ -726,8 +726,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
TRACE_INSN (cpu, "mulhu %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
- store_rd (cpu, rd, ((unsigned64)cpu->regs[rs1]
- * (unsigned64)cpu->regs[rs2]) >> 32);
+ store_rd (cpu, rd, ((uint64_t)cpu->regs[rs1]
+ * (uint64_t)cpu->regs[rs2]) >> 32);
else
store_rd (cpu, rd, mulhu (cpu->regs[rs1], cpu->regs[rs2]));
break;
@@ -735,8 +735,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
TRACE_INSN (cpu, "mulhsu %s, %s, %s; // %s = %s * %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
if (RISCV_XLEN (cpu) == 32)
- store_rd (cpu, rd, ((signed64)(signed_word) cpu->regs[rs1]
- * (unsigned64)cpu->regs[rs2]) >> 32);
+ store_rd (cpu, rd, ((int64_t)(signed_word) cpu->regs[rs1]
+ * (uint64_t)cpu->regs[rs2]) >> 32);
else
store_rd (cpu, rd, mulhsu (cpu->regs[rs1], cpu->regs[rs2]));
break;
@@ -775,8 +775,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
TRACE_INSN (cpu, "remuw %s, %s, %s; // %s = %s %% %s",
rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name);
RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
- if ((unsigned32) cpu->regs[rs2])
- tmp = (unsigned32) cpu->regs[rs1] % (unsigned32) cpu->regs[rs2];
+ if ((uint32_t) cpu->regs[rs2])
+ tmp = (uint32_t) cpu->regs[rs1] % (uint32_t) cpu->regs[rs2];
else
tmp = cpu->regs[rs1];
store_rd (cpu, rd, EXTEND32 (tmp));
@@ -1113,7 +1113,7 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int mhartid)
cpu->csr.misa = 0;
/* RV32 sets this field to 0, and we don't really support RV128 yet. */
if (RISCV_XLEN (cpu) == 64)
- cpu->csr.misa |= (unsigned64)2 << 62;
+ cpu->csr.misa |= (uint64_t)2 << 62;
/* Skip the leading "rv" prefix and the two numbers. */
extensions = MODEL_NAME (CPU_MODEL (cpu)) + 4;
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 10/17] sim: msp430: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (7 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 09/17] sim: riscv: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 11/17] sim: synacor: " Mike Frysinger
` (6 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
Move off the sim-specific unsignedXX types and to the standard uintXX_t
types that C11 provides.
---
sim/msp430/msp430-sim.c | 12 ++++++------
sim/msp430/msp430-sim.h | 18 +++++++++---------
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/sim/msp430/msp430-sim.c b/sim/msp430/msp430-sim.c
index bd911a5cf5f3..2ca5e1716d22 100644
--- a/sim/msp430/msp430-sim.c
+++ b/sim/msp430/msp430-sim.c
@@ -573,7 +573,7 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
/* For unsigned 32-bit multiplication of 16-bit operands, an
explicit cast is required to prevent any implicit
sign-extension. */
- HWMULT (sd, hwmult_result) = (unsigned32) a * (unsigned32) b;
+ HWMULT (sd, hwmult_result) = (uint32_t) a * (uint32_t) b;
HWMULT (sd, hwmult_signed_result) = a * b;
HWMULT (sd, hwmult_accumulator) = HWMULT (sd, hwmult_signed_accumulator) = 0;
break;
@@ -582,7 +582,7 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
a = sign_ext (HWMULT (sd, hwmult_op1), 16);
b = sign_ext (HWMULT (sd, hwmult_op2), 16);
HWMULT (sd, hwmult_signed_result) = a * b;
- HWMULT (sd, hwmult_result) = (unsigned32) a * (unsigned32) b;
+ HWMULT (sd, hwmult_result) = (uint32_t) a * (uint32_t) b;
HWMULT (sd, hwmult_accumulator) = HWMULT (sd, hwmult_signed_accumulator) = 0;
break;
@@ -590,7 +590,7 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
a = HWMULT (sd, hwmult_op1);
b = HWMULT (sd, hwmult_op2);
HWMULT (sd, hwmult_accumulator)
- += (unsigned32) a * (unsigned32) b;
+ += (uint32_t) a * (uint32_t) b;
HWMULT (sd, hwmult_signed_accumulator) += a * b;
HWMULT (sd, hwmult_result) = HWMULT (sd, hwmult_accumulator);
HWMULT (sd, hwmult_signed_result) = HWMULT (sd, hwmult_signed_accumulator);
@@ -600,7 +600,7 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
a = sign_ext (HWMULT (sd, hwmult_op1), 16);
b = sign_ext (HWMULT (sd, hwmult_op2), 16);
HWMULT (sd, hwmult_accumulator)
- += (unsigned32) a * (unsigned32) b;
+ += (uint32_t) a * (uint32_t) b;
HWMULT (sd, hwmult_signed_accumulator) += a * b;
HWMULT (sd, hwmult_result) = HWMULT (sd, hwmult_accumulator);
HWMULT (sd, hwmult_signed_result) = HWMULT (sd, hwmult_signed_accumulator);
@@ -660,8 +660,8 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
{
case UNSIGN_64:
HWMULT (sd, hw32mult_result)
- = (unsigned64) HWMULT (sd, hw32mult_op1)
- * (unsigned64) HWMULT (sd, hw32mult_op2);
+ = (uint64_t) HWMULT (sd, hw32mult_op1)
+ * (uint64_t) HWMULT (sd, hw32mult_op2);
break;
case SIGN_64:
HWMULT (sd, hw32mult_result)
diff --git a/sim/msp430/msp430-sim.h b/sim/msp430/msp430-sim.h
index 833caaa9159d..d453f3980024 100644
--- a/sim/msp430/msp430-sim.h
+++ b/sim/msp430/msp430-sim.h
@@ -31,17 +31,17 @@ struct msp430_cpu_state
int cio_buffer;
hwmult_type hwmult_type;
- unsigned16 hwmult_op1;
- unsigned16 hwmult_op2;
- unsigned32 hwmult_result;
- signed32 hwmult_signed_result;
- unsigned32 hwmult_accumulator;
- signed32 hwmult_signed_accumulator;
+ uint16_t hwmult_op1;
+ uint16_t hwmult_op2;
+ uint32_t hwmult_result;
+ int32_t hwmult_signed_result;
+ uint32_t hwmult_accumulator;
+ int32_t hwmult_signed_accumulator;
hw32mult_type hw32mult_type;
- unsigned32 hw32mult_op1;
- unsigned32 hw32mult_op2;
- unsigned64 hw32mult_result;
+ uint32_t hw32mult_op1;
+ uint32_t hw32mult_op2;
+ uint64_t hw32mult_result;
};
#define HWMULT(SD, FIELD) MSP430_CPU (SD)->state.FIELD
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 11/17] sim: synacor: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (8 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 10/17] sim: msp430: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 12/17] sim: iq2000: " Mike Frysinger
` (5 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
Move off the sim-specific unsignedXX types and to the standard uintXX_t
types that C11 provides.
---
sim/example-synacor/sim-main.c | 50 +++++++++++++++++-----------------
sim/example-synacor/sim-main.h | 4 +--
2 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/sim/example-synacor/sim-main.c b/sim/example-synacor/sim-main.c
index fad49dc9be60..75d5c6bc471c 100644
--- a/sim/example-synacor/sim-main.c
+++ b/sim/example-synacor/sim-main.c
@@ -28,8 +28,8 @@
#include "sim-signal.h"
\f
/* Get the register number from the number. */
-static unsigned16
-register_num (SIM_CPU *cpu, unsigned16 num)
+static uint16_t
+register_num (SIM_CPU *cpu, uint16_t num)
{
SIM_DESC sd = CPU_STATE (cpu);
@@ -40,8 +40,8 @@ register_num (SIM_CPU *cpu, unsigned16 num)
}
/* Helper to process immediates according to the ISA. */
-static unsigned16
-interp_num (SIM_CPU *cpu, unsigned16 num)
+static uint16_t
+interp_num (SIM_CPU *cpu, uint16_t num)
{
SIM_DESC sd = CPU_STATE (cpu);
@@ -69,7 +69,7 @@ interp_num (SIM_CPU *cpu, unsigned16 num)
void step_once (SIM_CPU *cpu)
{
SIM_DESC sd = CPU_STATE (cpu);
- unsigned16 iw1, num1;
+ uint16_t iw1, num1;
sim_cia pc = sim_pc_get (cpu);
iw1 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc);
@@ -86,7 +86,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 1)
{
/* set: 1 a b: Set register <a> to the value of <b>. */
- unsigned16 iw2, iw3, num2, num3;
+ uint16_t iw2, iw3, num2, num3;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -103,7 +103,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 2)
{
/* push: 2 a: Push <a> onto the stack. */
- unsigned16 iw2, num2;
+ uint16_t iw2, num2;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = interp_num (cpu, iw2);
@@ -120,7 +120,7 @@ void step_once (SIM_CPU *cpu)
{
/* pop: 3 a: Remove the top element from the stack and write it into <a>.
Empty stack = error. */
- unsigned16 iw2, num2, result;
+ uint16_t iw2, num2, result;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -139,7 +139,7 @@ void step_once (SIM_CPU *cpu)
{
/* eq: 4 a b c: Set <a> to 1 if <b> is equal to <c>; set it to 0
otherwise. */
- unsigned16 iw2, iw3, iw4, num2, num3, num4, result;
+ uint16_t iw2, iw3, iw4, num2, num3, num4, result;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -161,7 +161,7 @@ void step_once (SIM_CPU *cpu)
{
/* gt: 5 a b c: Set <a> to 1 if <b> is greater than <c>; set it to 0
otherwise. */
- unsigned16 iw2, iw3, iw4, num2, num3, num4, result;
+ uint16_t iw2, iw3, iw4, num2, num3, num4, result;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -182,7 +182,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 6)
{
/* jmp: 6 a: Jump to <a>. */
- unsigned16 iw2, num2;
+ uint16_t iw2, num2;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = interp_num (cpu, iw2);
@@ -197,7 +197,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 7)
{
/* jt: 7 a b: If <a> is nonzero, jump to <b>. */
- unsigned16 iw2, iw3, num2, num3;
+ uint16_t iw2, iw3, num2, num3;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = interp_num (cpu, iw2);
@@ -220,7 +220,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 8)
{
/* jf: 8 a b: If <a> is zero, jump to <b>. */
- unsigned16 iw2, iw3, num2, num3;
+ uint16_t iw2, iw3, num2, num3;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = interp_num (cpu, iw2);
@@ -243,7 +243,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 9)
{
/* add: 9 a b c: Assign <a> the sum of <b> and <c> (modulo 32768). */
- unsigned16 iw2, iw3, iw4, num2, num3, num4, result;
+ uint16_t iw2, iw3, iw4, num2, num3, num4, result;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -266,7 +266,7 @@ void step_once (SIM_CPU *cpu)
{
/* mult: 10 a b c: Store into <a> the product of <b> and <c> (modulo
32768). */
- unsigned16 iw2, iw3, iw4, num2, num3, num4, result;
+ uint16_t iw2, iw3, iw4, num2, num3, num4, result;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -288,7 +288,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 11)
{
/* mod: 11 a b c: Store into <a> the remainder of <b> divided by <c>. */
- unsigned16 iw2, iw3, iw4, num2, num3, num4, result;
+ uint16_t iw2, iw3, iw4, num2, num3, num4, result;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -309,7 +309,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 12)
{
/* and: 12 a b c: Stores into <a> the bitwise and of <b> and <c>. */
- unsigned16 iw2, iw3, iw4, num2, num3, num4, result;
+ uint16_t iw2, iw3, iw4, num2, num3, num4, result;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -330,7 +330,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 13)
{
/* or: 13 a b c: Stores into <a> the bitwise or of <b> and <c>. */
- unsigned16 iw2, iw3, iw4, num2, num3, num4, result;
+ uint16_t iw2, iw3, iw4, num2, num3, num4, result;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -351,7 +351,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 14)
{
/* not: 14 a b: Stores 15-bit bitwise inverse of <b> in <a>. */
- unsigned16 iw2, iw3, num2, num3, result;
+ uint16_t iw2, iw3, num2, num3, result;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -370,7 +370,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 15)
{
/* rmem: 15 a b: Read memory at address <b> and write it to <a>. */
- unsigned16 iw2, iw3, num2, num3, result;
+ uint16_t iw2, iw3, num2, num3, result;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = register_num (cpu, iw2);
@@ -392,7 +392,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 16)
{
/* wmem: 16 a b: Write the value from <b> into memory at address <a>. */
- unsigned16 iw2, iw3, num2, num3;
+ uint16_t iw2, iw3, num2, num3;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = interp_num (cpu, iw2);
@@ -412,7 +412,7 @@ void step_once (SIM_CPU *cpu)
{
/* call: 17 a: Write the address of the next instruction to the stack and
jump to <a>. */
- unsigned16 iw2, num2;
+ uint16_t iw2, num2;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = interp_num (cpu, iw2);
@@ -433,7 +433,7 @@ void step_once (SIM_CPU *cpu)
{
/* ret: 18: Remove the top element from the stack and jump to it; empty
stack = halt. */
- unsigned16 result;
+ uint16_t result;
TRACE_INSN (cpu, "RET");
cpu->sp += 2;
@@ -447,7 +447,7 @@ void step_once (SIM_CPU *cpu)
else if (num1 == 19)
{
/* out: 19 a: Write the character <a> to the terminal. */
- unsigned16 iw2, num2;
+ uint16_t iw2, num2;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
num2 = interp_num (cpu, iw2);
@@ -465,7 +465,7 @@ void step_once (SIM_CPU *cpu)
to <a>. It can be assumed that once input starts, it will continue
until a newline is encountered. This means that you can safely read
lines from the keyboard and trust that they will be fully read. */
- unsigned16 iw2, num2;
+ uint16_t iw2, num2;
char c;
iw2 = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
diff --git a/sim/example-synacor/sim-main.h b/sim/example-synacor/sim-main.h
index 09cd34c5db05..e7e3ddc6d44d 100644
--- a/sim/example-synacor/sim-main.h
+++ b/sim/example-synacor/sim-main.h
@@ -26,12 +26,12 @@
struct _sim_cpu {
/* ... simulator specific members ... */
- unsigned16 regs[8];
+ uint16_t regs[8];
sim_cia pc;
/* This isn't a real register, and the stack is not directly addressable,
so use memory outside of the 16-bit address space. */
- unsigned32 sp;
+ uint32_t sp;
sim_cpu_base base;
};
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 12/17] sim: iq2000: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (9 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 11/17] sim: synacor: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 13/17] sim: cris: " Mike Frysinger
` (4 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
Move off the sim-specific unsignedXX types and to the standard uintXX_t
types that C11 provides.
---
sim/iq2000/iq2000.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sim/iq2000/iq2000.c b/sim/iq2000/iq2000.c
index 6d210f411116..b685a31b07a5 100644
--- a/sim/iq2000/iq2000.c
+++ b/sim/iq2000/iq2000.c
@@ -211,14 +211,14 @@ iq2000bf_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
&& nr < (GPR0_REGNUM + NR_GPR)
&& len == 4)
{
- *((unsigned32*)buf) =
+ *((uint32_t*)buf) =
H2T_4 (iq2000bf_h_gr_get (cpu, nr - GPR0_REGNUM));
return 4;
}
else if (nr == PC_REGNUM
&& len == 4)
{
- *((unsigned32*)buf) = H2T_4 (get_h_pc (cpu));
+ *((uint32_t*)buf) = H2T_4 (get_h_pc (cpu));
return 4;
}
else
@@ -232,13 +232,13 @@ iq2000bf_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
&& nr < (GPR0_REGNUM + NR_GPR)
&& len == 4)
{
- iq2000bf_h_gr_set (cpu, nr - GPR0_REGNUM, T2H_4 (*((unsigned32*)buf)));
+ iq2000bf_h_gr_set (cpu, nr - GPR0_REGNUM, T2H_4 (*((uint32_t*)buf)));
return 4;
}
else if (nr == PC_REGNUM
&& len == 4)
{
- set_h_pc (cpu, T2H_4 (*((unsigned32*)buf)));
+ set_h_pc (cpu, T2H_4 (*((uint32_t*)buf)));
return 4;
}
else
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 13/17] sim: cris: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (10 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 12/17] sim: iq2000: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 14/17] sim: mips: " Mike Frysinger
` (3 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
Move off the sim-specific unsignedXX types and to the standard uintXX_t
types that C11 provides.
---
sim/cris/cris-sim.h | 22 +++++-----
sim/cris/cris-tmpl.c | 2 +-
sim/cris/crisv10f.c | 2 +-
sim/cris/crisv32f.c | 6 +--
sim/cris/dv-cris.c | 24 +++++-----
sim/cris/dv-rv.c | 102 +++++++++++++++++++++----------------------
sim/cris/traps.c | 2 +-
7 files changed, 80 insertions(+), 80 deletions(-)
diff --git a/sim/cris/cris-sim.h b/sim/cris/cris-sim.h
index 28ef4ff9dffe..c2801c91c88c 100644
--- a/sim/cris/cris-sim.h
+++ b/sim/cris/cris-sim.h
@@ -34,22 +34,22 @@ typedef struct {
/* Static cycle count for all insns executed so far, including
non-context-specific stall cycles, for example when adding to PC. */
- unsigned64 basic_cycle_count;
+ uint64_t basic_cycle_count;
/* Stall cycles for unaligned access of memory operands. FIXME:
Should or should not include unaligned [PC+] operands? */
- unsigned64 unaligned_mem_dword_count;
+ uint64_t unaligned_mem_dword_count;
/* Context-specific stall cycles. */
- unsigned64 memsrc_stall_count;
- unsigned64 memraw_stall_count;
- unsigned64 movemsrc_stall_count;
- unsigned64 movemaddr_stall_count;
- unsigned64 movemdst_stall_count;
- unsigned64 mulsrc_stall_count;
- unsigned64 jumpsrc_stall_count;
- unsigned64 branch_stall_count;
- unsigned64 jumptarget_stall_count;
+ uint64_t memsrc_stall_count;
+ uint64_t memraw_stall_count;
+ uint64_t movemsrc_stall_count;
+ uint64_t movemaddr_stall_count;
+ uint64_t movemdst_stall_count;
+ uint64_t mulsrc_stall_count;
+ uint64_t jumpsrc_stall_count;
+ uint64_t branch_stall_count;
+ uint64_t jumptarget_stall_count;
/* What kind of target-specific trace to perform. */
int flags;
diff --git a/sim/cris/cris-tmpl.c b/sim/cris/cris-tmpl.c
index 94a60d95409e..9f0c06e755e3 100644
--- a/sim/cris/cris-tmpl.c
+++ b/sim/cris/cris-tmpl.c
@@ -123,7 +123,7 @@ MY (f_model_insn_before) (SIM_CPU *current_cpu, int first_p ATTRIBUTE_UNUSED)
{
int i;
char flags[7];
- unsigned64 cycle_count;
+ uint64_t cycle_count;
SIM_DESC sd = CPU_STATE (current_cpu);
diff --git a/sim/cris/crisv10f.c b/sim/cris/crisv10f.c
index 847837998d1f..afb203da3f02 100644
--- a/sim/cris/crisv10f.c
+++ b/sim/cris/crisv10f.c
@@ -60,7 +60,7 @@ MY (deliver_interrupt) (SIM_CPU *current_cpu,
unsigned char entryaddr_le[4];
int was_user;
SIM_DESC sd = CPU_STATE (current_cpu);
- unsigned32 entryaddr;
+ uint32_t entryaddr;
/* We haven't implemented other interrupt-types yet. */
if (type != CRIS_INT_INT)
diff --git a/sim/cris/crisv32f.c b/sim/cris/crisv32f.c
index 3b01f0803ddf..002262645178 100644
--- a/sim/cris/crisv32f.c
+++ b/sim/cris/crisv32f.c
@@ -565,11 +565,11 @@ MY (deliver_interrupt) (SIM_CPU *current_cpu,
enum cris_interrupt_type type,
unsigned int vec)
{
- unsigned32 old_ccs, shifted_ccs, new_ccs;
+ uint32_t old_ccs, shifted_ccs, new_ccs;
unsigned char entryaddr_le[4];
int was_user;
SIM_DESC sd = CPU_STATE (current_cpu);
- unsigned32 entryaddr;
+ uint32_t entryaddr;
/* We haven't implemented other interrupt-types yet. */
if (type != CRIS_INT_INT)
@@ -585,7 +585,7 @@ MY (deliver_interrupt) (SIM_CPU *current_cpu,
/* The M bit is handled by code below and the M bit setter function, but
we need to preserve the Q bit. */
- new_ccs = shifted_ccs | (old_ccs & (unsigned32) 0x80000000UL);
+ new_ccs = shifted_ccs | (old_ccs & (uint32_t) 0x80000000UL);
was_user = GET_H_UBIT_V32 ();
/* We need to force kernel mode since the setter method doesn't allow
diff --git a/sim/cris/dv-cris.c b/sim/cris/dv-cris.c
index 472af0e935ac..11434654c88c 100644
--- a/sim/cris/dv-cris.c
+++ b/sim/cris/dv-cris.c
@@ -88,7 +88,7 @@ static const struct hw_port_descriptor cris_ports[] =
struct cris_vec_tr
{
- unsigned32 portval, vec;
+ uint32_t portval, vec;
};
enum cris_multiple_ints
@@ -101,10 +101,10 @@ enum cris_multiple_ints
struct cris_hw
{
struct hw_event *pending_handler;
- unsigned32 pending_vector;
+ uint32_t pending_vector;
struct cris_vec_tr *int_to_vec;
enum cris_multiple_ints multi_int_action;
- unsigned32 multiple_int_vector;
+ uint32_t multiple_int_vector;
};
/* An event function, calling the actual CPU-model-specific
@@ -136,9 +136,9 @@ deliver_cris_interrupt (struct hw *me, void *data)
time we get here, until a new time is seen (supposedly unstuck
re-delivery). (Fixing in SIM/GDB source will hopefully then
also be easier, having a tangible test-case.) */
- static signed64 last_events_time = 0;
- static signed64 delta = 1;
- signed64 this_events_time = hw_event_queue_time (me);
+ static int64_t last_events_time = 0;
+ static int64_t delta = 1;
+ int64_t this_events_time = hw_event_queue_time (me);
if (this_events_time == last_events_time)
delta++;
@@ -164,7 +164,7 @@ cris_port_event (struct hw *me,
int intparam)
{
struct cris_hw *crishw = hw_data (me);
- unsigned32 vec;
+ uint32_t vec;
/* A few placeholders; only the INT port is implemented. */
switch (my_port)
@@ -194,7 +194,7 @@ cris_port_event (struct hw *me,
vec = crishw->int_to_vec[i].vec;
}
else
- vec = (unsigned32) intparam;
+ vec = (uint32_t) intparam;
if (crishw->pending_vector != 0)
{
@@ -245,8 +245,8 @@ cris_finish (struct hw *me)
vec_for_int = hw_find_property (me, "vec-for-int");
if (vec_for_int != NULL)
{
- unsigned32 vecsize;
- unsigned32 i;
+ uint32_t vecsize;
+ uint32_t i;
if (hw_property_type (vec_for_int) != array_property)
hw_abort (me, "property \"vec-for-int\" has the wrong type");
@@ -272,8 +272,8 @@ cris_finish (struct hw *me)
|| vec_sc < 0)
hw_abort (me, "no valid vector translation pair %u", i);
- crishw->int_to_vec[i].portval = (unsigned32) portval_sc;
- crishw->int_to_vec[i].vec = (unsigned32) vec_sc;
+ crishw->int_to_vec[i].portval = (uint32_t) portval_sc;
+ crishw->int_to_vec[i].vec = (uint32_t) vec_sc;
}
crishw->int_to_vec[i].portval = 0;
diff --git a/sim/cris/dv-rv.c b/sim/cris/dv-rv.c
index 5d8c06bc105b..42ef9b169fa9 100644
--- a/sim/cris/dv-rv.c
+++ b/sim/cris/dv-rv.c
@@ -293,43 +293,43 @@ enum rv_command {
typedef struct _hw_rv_device
{
/* Mapping of remote interrupt bit-numbers to local ones. */
- unsigned32 remote_to_local_int[32];
+ uint32_t remote_to_local_int[32];
/* When multiple bits are set, a non-zero value here indicates that
this value should be used instead. */
- unsigned32 intmultiple;
+ uint32_t intmultiple;
/* Local address of registers. */
- unsigned32 reg_address;
+ uint32_t reg_address;
/* Size of register bank in bytes. */
- unsigned32 reg_size;
+ uint32_t reg_size;
/* Remote address of registers. */
- unsigned32 remote_reg_address;
+ uint32_t remote_reg_address;
/* Local address of DMA:able memory. */
- unsigned32 mem_address;
+ uint32_t mem_address;
/* Size of DMA:able memory in bytes. */
- unsigned32 mem_size;
+ uint32_t mem_size;
/* Bitmask for valid DMA request size. */
- unsigned32 mem_burst_mask;
+ uint32_t mem_burst_mask;
/* Remote address of DMA:able memory. */
- unsigned32 remote_mem_address;
+ uint32_t remote_mem_address;
/* (Local) address of mbox; where to put a pointer to the mbox to be
sent. */
- unsigned32 mbox_address;
+ uint32_t mbox_address;
/* Probably not 127.0.0.1:10000. */
const char *host;
int port;
/* If non-NULL, points to memory to use instead of connection. */
- unsigned8 *dummy;
+ uint8_t *dummy;
/* File descriptor for the socket. Set to -1 when error. Only one
of dummy and this is active. */
@@ -341,18 +341,18 @@ typedef struct _hw_rv_device
/* This, plus latency because the CPU might not be checking until a
CTI insn (usually a branch or a jump) is the interval in cycles
between the rv is polled for e.g. DMA requests. */
- unsigned32 max_tick_poll_interval;
+ uint32_t max_tick_poll_interval;
/* Running counter for exponential backoff up to
max_tick_poll_interval to avoid polling the connection
unnecessarily often. Set to 1 when rv activity (read/write
register, DMA request) is detected. */
- unsigned32 next_period;
+ uint32_t next_period;
/* This is the interval in wall-clock seconds between watchdog
packets are sent to the remote side. Zero means no watchdog
packets. */
- unsigned32 watchdog_interval;
+ uint32_t watchdog_interval;
/* Last time we sent a watchdog packet. */
struct timeval last_wdog_time;
@@ -384,7 +384,7 @@ hw_rv_write (struct hw *me,
unsigned int len)
{
hw_rv_device *rv = (hw_rv_device *) hw_data (me);
- unsigned8 *bufp = buf;
+ uint8_t *bufp = buf;
/* If we don't have a valid fd here, it's because we got an error
initially, and we suppressed that error. */
@@ -414,7 +414,7 @@ hw_rv_read (struct hw *me,
unsigned int len)
{
hw_rv_device *rv = (hw_rv_device *) hw_data (me);
- unsigned8 *bufp = buf;
+ uint8_t *bufp = buf;
while (len > 0)
{
@@ -446,8 +446,8 @@ hw_rv_send (struct hw *me,
unsigned int len_noheader)
{
hw_rv_device *rv = (hw_rv_device *) hw_data (me);
- unsigned8 buf[32+3];
- unsigned8 *bufp;
+ uint8_t buf[32+3];
+ uint8_t *bufp;
unsigned int len = len_noheader + 3;
int ret;
@@ -478,12 +478,12 @@ hw_rv_read_mem (struct hw *me, unsigned int len)
{
hw_rv_device *rv = (hw_rv_device *) hw_data (me);
/* If you change this size, please adjust the mem2 testcase. */
- unsigned8 buf[32+8];
- unsigned8 *bufp = buf;
- unsigned32 leaddr;
- unsigned32 addr;
- unsigned32 lelen;
- unsigned32 i;
+ uint8_t buf[32+8];
+ uint8_t *bufp = buf;
+ uint32_t leaddr;
+ uint32_t addr;
+ uint32_t lelen;
+ uint32_t i;
if (len != 8)
hw_abort (me, "expected DMA read request len 8+3, got %d+3", len);
@@ -532,13 +532,13 @@ hw_rv_write_mem (struct hw *me, unsigned int plen)
{
hw_rv_device *rv = (hw_rv_device *) hw_data (me);
/* If you change this size, please adjust the mem2 testcase. */
- unsigned8 buf[32+8];
- unsigned8 *bufp = buf;
- unsigned32 leaddr;
- unsigned32 addr;
- unsigned32 lelen;
- unsigned32 len;
- unsigned32 i;
+ uint8_t buf[32+8];
+ uint8_t *bufp = buf;
+ uint32_t leaddr;
+ uint32_t addr;
+ uint32_t lelen;
+ uint32_t len;
+ uint32_t i;
hw_rv_read (me, &leaddr, 4);
hw_rv_read (me, &lelen, 4);
@@ -582,9 +582,9 @@ static void
hw_rv_irq (struct hw *me, unsigned int len)
{
hw_rv_device *rv = (hw_rv_device *) hw_data (me);
- unsigned32 intbitsle;
- unsigned32 intbits_ext;
- unsigned32 intval = 0;
+ uint32_t intbitsle;
+ uint32_t intbits_ext;
+ uint32_t intval = 0;
int i;
if (len != 4)
@@ -609,11 +609,11 @@ hw_rv_irq (struct hw *me, unsigned int len)
static void
hw_rv_handle_incoming (struct hw *me,
int expected_type,
- unsigned8 *buf,
+ uint8_t *buf,
unsigned int *return_len)
{
hw_rv_device *rv = (hw_rv_device *) hw_data (me);
- unsigned8 cbuf[32];
+ uint8_t cbuf[32];
unsigned int len;
unsigned int cmd;
@@ -765,7 +765,7 @@ static void
do_poll_event (struct hw *me, void *data)
{
hw_rv_device *rv = (hw_rv_device *) hw_data (me);
- unsigned32 new_period;
+ uint32_t new_period;
if (rv->dummy != NULL)
return;
@@ -900,8 +900,8 @@ hw_rv_reg_read (struct hw *me,
unsigned int nr_bytes)
{
hw_rv_device *rv = (hw_rv_device *) hw_data (me);
- unsigned8 addr_data[8] = "";
- unsigned32 a_l = H2LE_4 (addr - rv->reg_address + rv->remote_reg_address);
+ uint8_t addr_data[8] = "";
+ uint32_t a_l = H2LE_4 (addr - rv->reg_address + rv->remote_reg_address);
unsigned int len = 8;
if (nr_bytes != 4)
@@ -937,10 +937,10 @@ hw_rv_reg_read (struct hw *me,
static void
hw_rv_mbox (struct hw *me, unsigned_word address)
{
- unsigned8 buf[256+3];
+ uint8_t buf[256+3];
unsigned int cmd;
unsigned int rlen;
- unsigned32 i;
+ uint32_t i;
unsigned int len
= hw_dma_read_buffer (me, buf, 0, address, 3);
@@ -1002,8 +1002,8 @@ hw_rv_reg_write (struct hw *me,
{
hw_rv_device *rv = (hw_rv_device *) hw_data (me);
- unsigned8 addr_data[8] = "";
- unsigned32 a_l = H2LE_4 (addr - rv->reg_address + rv->remote_reg_address);
+ uint8_t addr_data[8] = "";
+ uint32_t a_l = H2LE_4 (addr - rv->reg_address + rv->remote_reg_address);
unsigned int len = 8;
if (nr_bytes != 4)
@@ -1014,7 +1014,7 @@ hw_rv_reg_write (struct hw *me,
if (addr == rv->mbox_address)
{
- unsigned32 mbox_addr_le;
+ uint32_t mbox_addr_le;
if (rv->dummy != NULL)
hw_abort (me, "mbox not supported for a dummy instance");
memcpy (&mbox_addr_le, source, 4);
@@ -1123,15 +1123,15 @@ hw_rv_finish (struct hw *me)
if (hw_property_type (dummy_prop) == integer_property)
{
- unsigned32 dummyfill = hw_find_integer_property (me, "dummy");
- unsigned8 *dummymem = hw_malloc (me, rv->reg_size);
+ uint32_t dummyfill = hw_find_integer_property (me, "dummy");
+ uint8_t *dummymem = hw_malloc (me, rv->reg_size);
memset (dummymem, dummyfill, rv->reg_size);
rv->dummy = dummymem;
}
else
{
const char *dummyarg = hw_find_string_property (me, "dummy");
- unsigned8 *dummymem = hw_malloc (me, rv->reg_size);
+ uint8_t *dummymem = hw_malloc (me, rv->reg_size);
FILE *f = fopen (dummyarg, "rb");
if (f == NULL)
@@ -1153,10 +1153,10 @@ hw_rv_finish (struct hw *me)
signed_cell attach_address_sc
= hw_find_integer_property (me, "mbox");
- rv->mbox_address = (unsigned32) attach_address_sc;
+ rv->mbox_address = (uint32_t) attach_address_sc;
hw_attach_address (hw_parent (me),
0,
- 0, (unsigned32) attach_address_sc, 4, me);
+ 0, (uint32_t) attach_address_sc, 4, me);
}
else
hw_abort (me, "property \"mbox\" has the wrong type");
@@ -1176,8 +1176,8 @@ hw_rv_finish (struct hw *me)
&& hw_find_integer_array_property (me, "mem", 1, &attach_size_sc))
{
/* Unfortunate choice of types forces us to dance around a bit. */
- rv->mem_address = (unsigned32) attach_address_sc;
- rv->mem_size = (unsigned32) attach_size_sc;
+ rv->mem_address = (uint32_t) attach_address_sc;
+ rv->mem_size = (uint32_t) attach_size_sc;
if ((attach_address_sc & 3) != 0)
hw_abort (me, "memory block must be 4 byte aligned");
}
diff --git a/sim/cris/traps.c b/sim/cris/traps.c
index e17d40527f94..e92fa1aae254 100644
--- a/sim/cris/traps.c
+++ b/sim/cris/traps.c
@@ -803,7 +803,7 @@ dump_statistics (SIM_CPU *current_cpu)
SIM_DESC sd = CPU_STATE (current_cpu);
CRIS_MISC_PROFILE *profp
= CPU_CRIS_MISC_PROFILE (current_cpu);
- unsigned64 total = profp->basic_cycle_count;
+ uint64_t total = profp->basic_cycle_count;
/* Historically, these messages have gone to stderr, so we'll keep it
that way. It's also easier to then tell it from normal program
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 14/17] sim: mips: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (11 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 13/17] sim: cris: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 15/17] sim: igen: " Mike Frysinger
` (2 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
Move off the sim-specific unsignedXX types and to the standard uintXX_t
types that C11 provides.
---
sim/mips/cp1.c | 252 +++++++--------
sim/mips/dsp.igen | 648 ++++++++++++++++++-------------------
sim/mips/dsp2.igen | 216 ++++++-------
sim/mips/interp.c | 50 +--
sim/mips/m16.igen | 4 +-
sim/mips/m16e.igen | 6 +-
sim/mips/mdmx.c | 516 ++++++++++++++---------------
sim/mips/mdmx.igen | 4 +-
sim/mips/micromips.igen | 4 +-
sim/mips/micromipsdsp.igen | 2 +-
sim/mips/mips.igen | 312 +++++++++---------
sim/mips/mips3264r2.igen | 6 +-
sim/mips/sim-main.c | 20 +-
sim/mips/sim-main.h | 98 +++---
sim/mips/smartmips.igen | 8 +-
sim/mips/tx.igen | 12 +-
sim/mips/vr.igen | 8 +-
17 files changed, 1083 insertions(+), 1083 deletions(-)
diff --git a/sim/mips/cp1.c b/sim/mips/cp1.c
index e5c58ca68321..a6d1b56fdb70 100644
--- a/sim/mips/cp1.c
+++ b/sim/mips/cp1.c
@@ -90,8 +90,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Extract packed single values: */
#define FP_PS_upper(v) (((v) >> 32) & (unsigned)0xFFFFFFFF)
#define FP_PS_lower(v) ((v) & (unsigned)0xFFFFFFFF)
-#define FP_PS_cat(u,l) (((unsigned64)((u) & (unsigned)0xFFFFFFFF) << 32) \
- | (unsigned64)((l) & 0xFFFFFFFF))
+#define FP_PS_cat(u,l) (((uint64_t)((u) & (unsigned)0xFFFFFFFF) << 32) \
+ | (uint64_t)((l) & 0xFFFFFFFF))
/* Explicit QNaN values. */
#define FPQNaN_SINGLE (0x7FBFFFFF)
@@ -360,7 +360,7 @@ value_fcr(sim_cpu *cpu,
address_word cia,
int fcr)
{
- unsigned32 value = 0;
+ uint32_t value = 0;
switch (fcr)
{
@@ -393,7 +393,7 @@ store_fcr(sim_cpu *cpu,
int fcr,
unsigned_word value)
{
- unsigned32 v;
+ uint32_t v;
v = VL4_8(value);
switch (fcr)
@@ -523,8 +523,8 @@ denorm_mode(sim_cpu *cpu)
/* Comparison operations. */
static sim_fpu_status
-fp_test(unsigned64 op1,
- unsigned64 op2,
+fp_test(uint64_t op1,
+ uint64_t op2,
FP_formats fmt,
int abs,
int cond,
@@ -584,8 +584,8 @@ fp_test(unsigned64 op1,
void
fp_cmp(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt,
int abs,
int cond,
@@ -628,11 +628,11 @@ fp_cmp(sim_cpu *cpu,
/* Basic arithmetic operations. */
-static unsigned64
+static uint64_t
fp_unary(sim_cpu *cpu,
address_word cia,
int (*sim_fpu_op)(sim_fpu *, const sim_fpu *),
- unsigned64 op,
+ uint64_t op,
FP_formats fmt)
{
sim_fpu wop;
@@ -640,14 +640,14 @@ fp_unary(sim_cpu *cpu,
sim_fpu_round round = rounding_mode (GETRM());
sim_fpu_denorm denorm = denorm_mode (cpu);
sim_fpu_status status = 0;
- unsigned64 result = 0;
+ uint64_t result = 0;
/* The format type has already been checked: */
switch (fmt)
{
case fmt_single:
{
- unsigned32 res;
+ uint32_t res;
sim_fpu_32to (&wop, op);
status |= (*sim_fpu_op) (&ans, &wop);
status |= sim_fpu_round_32 (&ans, round, denorm);
@@ -657,7 +657,7 @@ fp_unary(sim_cpu *cpu,
}
case fmt_double:
{
- unsigned64 res;
+ uint64_t res;
sim_fpu_64to (&wop, op);
status |= (*sim_fpu_op) (&ans, &wop);
status |= sim_fpu_round_64 (&ans, round, denorm);
@@ -668,7 +668,7 @@ fp_unary(sim_cpu *cpu,
case fmt_ps:
{
int status_u = 0, status_l = 0;
- unsigned32 res_u, res_l;
+ uint32_t res_u, res_l;
sim_fpu_32to (&wop, FP_PS_upper(op));
status_u |= (*sim_fpu_op) (&ans, &wop);
sim_fpu_to32 (&res_u, &ans);
@@ -688,12 +688,12 @@ fp_unary(sim_cpu *cpu,
return result;
}
-static unsigned64
+static uint64_t
fp_binary(sim_cpu *cpu,
address_word cia,
int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt)
{
sim_fpu wop1;
@@ -702,14 +702,14 @@ fp_binary(sim_cpu *cpu,
sim_fpu_round round = rounding_mode (GETRM());
sim_fpu_denorm denorm = denorm_mode (cpu);
sim_fpu_status status = 0;
- unsigned64 result = 0;
+ uint64_t result = 0;
/* The format type has already been checked: */
switch (fmt)
{
case fmt_single:
{
- unsigned32 res;
+ uint32_t res;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
@@ -720,7 +720,7 @@ fp_binary(sim_cpu *cpu,
}
case fmt_double:
{
- unsigned64 res;
+ uint64_t res;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
@@ -732,7 +732,7 @@ fp_binary(sim_cpu *cpu,
case fmt_ps:
{
int status_u = 0, status_l = 0;
- unsigned32 res_u, res_l;
+ uint32_t res_u, res_l;
sim_fpu_32to (&wop1, FP_PS_upper(op1));
sim_fpu_32to (&wop2, FP_PS_upper(op2));
status_u |= (*sim_fpu_op) (&ans, &wop1, &wop2);
@@ -757,28 +757,28 @@ fp_binary(sim_cpu *cpu,
/* Common MAC code for single operands (.s or .d), defers setting FCSR. */
static sim_fpu_status
inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
- unsigned64 op1,
- unsigned64 op2,
- unsigned64 op3,
+ uint64_t op1,
+ uint64_t op2,
+ uint64_t op3,
int scale,
int negate,
FP_formats fmt,
sim_fpu_round round,
sim_fpu_denorm denorm,
- unsigned64 *result)
+ uint64_t *result)
{
sim_fpu wop1;
sim_fpu wop2;
sim_fpu ans;
sim_fpu_status status = 0;
sim_fpu_status op_status;
- unsigned64 temp = 0;
+ uint64_t temp = 0;
switch (fmt)
{
case fmt_single:
{
- unsigned32 res;
+ uint32_t res;
sim_fpu_32to (&wop1, op1);
sim_fpu_32to (&wop2, op2);
status |= sim_fpu_mul (&ans, &wop1, &wop2);
@@ -804,7 +804,7 @@ inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
}
case fmt_double:
{
- unsigned64 res;
+ uint64_t res;
sim_fpu_64to (&wop1, op1);
sim_fpu_64to (&wop2, op2);
status |= sim_fpu_mul (&ans, &wop1, &wop2);
@@ -842,13 +842,13 @@ inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
argument is an adjustment to the exponent of the intermediate
product op1*op2. It is currently non-zero for rsqrt2 (-1), which
requires an effective division by 2. */
-static unsigned64
+static uint64_t
fp_mac(sim_cpu *cpu,
address_word cia,
int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
- unsigned64 op1,
- unsigned64 op2,
- unsigned64 op3,
+ uint64_t op1,
+ uint64_t op2,
+ uint64_t op3,
int scale,
int negate,
FP_formats fmt)
@@ -856,7 +856,7 @@ fp_mac(sim_cpu *cpu,
sim_fpu_round round = rounding_mode (GETRM());
sim_fpu_denorm denorm = denorm_mode (cpu);
sim_fpu_status status = 0;
- unsigned64 result = 0;
+ uint64_t result = 0;
/* The format type has already been checked: */
switch (fmt)
@@ -869,7 +869,7 @@ fp_mac(sim_cpu *cpu,
case fmt_ps:
{
int status_u, status_l;
- unsigned64 result_u, result_l;
+ uint64_t result_u, result_l;
status_u = inner_mac(sim_fpu_op, FP_PS_upper(op1), FP_PS_upper(op2),
FP_PS_upper(op3), scale, negate, fmt_single,
round, denorm, &result_u);
@@ -891,23 +891,23 @@ fp_mac(sim_cpu *cpu,
/* Common rsqrt code for single operands (.s or .d), intermediate rounding. */
static sim_fpu_status
-inner_rsqrt(unsigned64 op1,
+inner_rsqrt(uint64_t op1,
FP_formats fmt,
sim_fpu_round round,
sim_fpu_denorm denorm,
- unsigned64 *result)
+ uint64_t *result)
{
sim_fpu wop1;
sim_fpu ans;
sim_fpu_status status = 0;
sim_fpu_status op_status;
- unsigned64 temp = 0;
+ uint64_t temp = 0;
switch (fmt)
{
case fmt_single:
{
- unsigned32 res;
+ uint32_t res;
sim_fpu_32to (&wop1, op1);
status |= sim_fpu_sqrt (&ans, &wop1);
status |= sim_fpu_round_32 (&ans, status, round);
@@ -921,7 +921,7 @@ inner_rsqrt(unsigned64 op1,
}
case fmt_double:
{
- unsigned64 res;
+ uint64_t res;
sim_fpu_64to (&wop1, op1);
status |= sim_fpu_sqrt (&ans, &wop1);
status |= sim_fpu_round_64 (&ans, round, denorm);
@@ -941,16 +941,16 @@ inner_rsqrt(unsigned64 op1,
return status;
}
-static unsigned64
+static uint64_t
fp_inv_sqrt(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
+ uint64_t op1,
FP_formats fmt)
{
sim_fpu_round round = rounding_mode (GETRM());
sim_fpu_round denorm = denorm_mode (cpu);
sim_fpu_status status = 0;
- unsigned64 result = 0;
+ uint64_t result = 0;
/* The format type has already been checked: */
switch (fmt)
@@ -962,7 +962,7 @@ fp_inv_sqrt(sim_cpu *cpu,
case fmt_ps:
{
int status_u, status_l;
- unsigned64 result_u, result_l;
+ uint64_t result_u, result_l;
status_u = inner_rsqrt (FP_PS_upper(op1), fmt_single, round, denorm,
&result_u);
status_l = inner_rsqrt (FP_PS_lower(op1), fmt_single, round, denorm,
@@ -981,130 +981,130 @@ fp_inv_sqrt(sim_cpu *cpu,
}
-unsigned64
+uint64_t
fp_abs(sim_cpu *cpu,
address_word cia,
- unsigned64 op,
+ uint64_t op,
FP_formats fmt)
{
return fp_unary(cpu, cia, &sim_fpu_abs, op, fmt);
}
-unsigned64
+uint64_t
fp_neg(sim_cpu *cpu,
address_word cia,
- unsigned64 op,
+ uint64_t op,
FP_formats fmt)
{
return fp_unary(cpu, cia, &sim_fpu_neg, op, fmt);
}
-unsigned64
+uint64_t
fp_add(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt)
{
return fp_binary(cpu, cia, &sim_fpu_add, op1, op2, fmt);
}
-unsigned64
+uint64_t
fp_sub(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt)
{
return fp_binary(cpu, cia, &sim_fpu_sub, op1, op2, fmt);
}
-unsigned64
+uint64_t
fp_mul(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt)
{
return fp_binary(cpu, cia, &sim_fpu_mul, op1, op2, fmt);
}
-unsigned64
+uint64_t
fp_div(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt)
{
return fp_binary(cpu, cia, &sim_fpu_div, op1, op2, fmt);
}
-unsigned64
+uint64_t
fp_recip(sim_cpu *cpu,
address_word cia,
- unsigned64 op,
+ uint64_t op,
FP_formats fmt)
{
return fp_unary(cpu, cia, &sim_fpu_inv, op, fmt);
}
-unsigned64
+uint64_t
fp_sqrt(sim_cpu *cpu,
address_word cia,
- unsigned64 op,
+ uint64_t op,
FP_formats fmt)
{
return fp_unary(cpu, cia, &sim_fpu_sqrt, op, fmt);
}
-unsigned64
+uint64_t
fp_rsqrt(sim_cpu *cpu,
address_word cia,
- unsigned64 op,
+ uint64_t op,
FP_formats fmt)
{
return fp_inv_sqrt(cpu, cia, op, fmt);
}
-unsigned64
+uint64_t
fp_madd(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
- unsigned64 op3,
+ uint64_t op1,
+ uint64_t op2,
+ uint64_t op3,
FP_formats fmt)
{
return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 0, fmt);
}
-unsigned64
+uint64_t
fp_msub(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
- unsigned64 op3,
+ uint64_t op1,
+ uint64_t op2,
+ uint64_t op3,
FP_formats fmt)
{
return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 0, fmt);
}
-unsigned64
+uint64_t
fp_nmadd(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
- unsigned64 op3,
+ uint64_t op1,
+ uint64_t op2,
+ uint64_t op3,
FP_formats fmt)
{
return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 1, fmt);
}
-unsigned64
+uint64_t
fp_nmsub(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
- unsigned64 op3,
+ uint64_t op1,
+ uint64_t op2,
+ uint64_t op3,
FP_formats fmt)
{
return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 1, fmt);
@@ -1114,12 +1114,12 @@ fp_nmsub(sim_cpu *cpu,
/* MIPS-3D ASE operations. */
/* Variant of fp_binary for *r.ps MIPS-3D operations. */
-static unsigned64
+static uint64_t
fp_binary_r(sim_cpu *cpu,
address_word cia,
int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
- unsigned64 op1,
- unsigned64 op2)
+ uint64_t op1,
+ uint64_t op2)
{
sim_fpu wop1;
sim_fpu wop2;
@@ -1127,8 +1127,8 @@ fp_binary_r(sim_cpu *cpu,
sim_fpu_round round = rounding_mode (GETRM ());
sim_fpu_denorm denorm = denorm_mode (cpu);
sim_fpu_status status_u, status_l;
- unsigned64 result;
- unsigned32 res_u, res_l;
+ uint64_t result;
+ uint32_t res_u, res_l;
/* The format must be fmt_ps. */
status_u = 0;
@@ -1149,21 +1149,21 @@ fp_binary_r(sim_cpu *cpu,
return result;
}
-unsigned64
+uint64_t
fp_add_r(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt)
{
return fp_binary_r (cpu, cia, &sim_fpu_add, op1, op2);
}
-unsigned64
+uint64_t
fp_mul_r(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt)
{
return fp_binary_r (cpu, cia, &sim_fpu_mul, op1, op2);
@@ -1221,10 +1221,10 @@ fpu_inv1_64(sim_fpu *f, const sim_fpu *l)
return fpu_inv1 (f, l);
}
-unsigned64
+uint64_t
fp_recip1(sim_cpu *cpu,
address_word cia,
- unsigned64 op,
+ uint64_t op,
FP_formats fmt)
{
switch (fmt)
@@ -1238,17 +1238,17 @@ fp_recip1(sim_cpu *cpu,
return 0;
}
-unsigned64
+uint64_t
fp_recip2(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt)
{
- static const unsigned64 one_single = UNSIGNED64 (0x3F800000);
- static const unsigned64 one_double = UNSIGNED64 (0x3FF0000000000000);
- static const unsigned64 one_ps = (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000));
- unsigned64 one;
+ static const uint64_t one_single = UNSIGNED64 (0x3F800000);
+ static const uint64_t one_double = UNSIGNED64 (0x3FF0000000000000);
+ static const uint64_t one_ps = (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000));
+ uint64_t one;
/* Implemented as nmsub fd, 1, fs, ft. */
switch (fmt)
@@ -1319,10 +1319,10 @@ fpu_inv_sqrt1_64(sim_fpu *f, const sim_fpu *l)
return fpu_inv_sqrt1 (f, l);
}
-unsigned64
+uint64_t
fp_rsqrt1(sim_cpu *cpu,
address_word cia,
- unsigned64 op,
+ uint64_t op,
FP_formats fmt)
{
switch (fmt)
@@ -1336,17 +1336,17 @@ fp_rsqrt1(sim_cpu *cpu,
return 0;
}
-unsigned64
+uint64_t
fp_rsqrt2(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt)
{
- static const unsigned64 half_single = UNSIGNED64 (0x3F000000);
- static const unsigned64 half_double = UNSIGNED64 (0x3FE0000000000000);
- static const unsigned64 half_ps = (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000));
- unsigned64 half;
+ static const uint64_t half_single = UNSIGNED64 (0x3F000000);
+ static const uint64_t half_double = UNSIGNED64 (0x3FE0000000000000);
+ static const uint64_t half_ps = (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000));
+ uint64_t half;
/* Implemented as (nmsub fd, 0.5, fs, ft)/2, where the divide is
done by scaling the exponent during multiply. */
@@ -1374,8 +1374,8 @@ convert (sim_cpu *cpu,
sim_fpu wop;
sim_fpu_round round = rounding_mode (rm);
sim_fpu_denorm denorm = denorm_mode (cpu);
- unsigned32 result32;
- unsigned64 result64;
+ uint32_t result32;
+ uint64_t result64;
sim_fpu_status status = 0;
/* Convert the input to sim_fpu internal format */
@@ -1438,30 +1438,30 @@ convert (sim_cpu *cpu,
return result64;
}
-unsigned64
+uint64_t
ps_lower(sim_cpu *cpu,
address_word cia,
- unsigned64 op)
+ uint64_t op)
{
return FP_PS_lower (op);
}
-unsigned64
+uint64_t
ps_upper(sim_cpu *cpu,
address_word cia,
- unsigned64 op)
+ uint64_t op)
{
return FP_PS_upper(op);
}
-unsigned64
+uint64_t
pack_ps(sim_cpu *cpu,
address_word cia,
- unsigned64 op1,
- unsigned64 op2,
+ uint64_t op1,
+ uint64_t op2,
FP_formats fmt)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
@@ -1472,7 +1472,7 @@ pack_ps(sim_cpu *cpu,
case fmt_single:
{
sim_fpu wop;
- unsigned32 res_u, res_l;
+ uint32_t res_u, res_l;
sim_fpu_32to (&wop, op1);
sim_fpu_to32 (&res_u, &wop);
sim_fpu_32to (&wop, op2);
@@ -1488,19 +1488,19 @@ pack_ps(sim_cpu *cpu,
return result;
}
-unsigned64
+uint64_t
convert_ps (sim_cpu *cpu,
address_word cia,
int rm,
- unsigned64 op,
+ uint64_t op,
FP_formats from,
FP_formats to)
{
sim_fpu wop_u, wop_l;
sim_fpu_round round = rounding_mode (rm);
sim_fpu_denorm denorm = denorm_mode (cpu);
- unsigned32 res_u, res_l;
- unsigned64 result;
+ uint32_t res_u, res_l;
+ uint64_t result;
sim_fpu_status status_u = 0, status_l = 0;
/* As convert, but used only for paired values (formats PS, PW) */
@@ -1527,7 +1527,7 @@ convert_ps (sim_cpu *cpu,
case fmt_word: /* fmt_pw */
status_u |= sim_fpu_to32u (&res_u, &wop_u, round);
status_l |= sim_fpu_to32u (&res_l, &wop_l, round);
- result = (((unsigned64)res_u) << 32) | (unsigned64)res_l;
+ result = (((uint64_t)res_u) << 32) | (uint64_t)res_l;
break;
case fmt_ps:
status_u |= sim_fpu_round_32 (&wop_u, 0, round);
diff --git a/sim/mips/dsp.igen b/sim/mips/dsp.igen
index bc103e448962..ec11011042ac 100644
--- a/sim/mips/dsp.igen
+++ b/sim/mips/dsp.igen
@@ -25,22 +25,22 @@
:function:::void:do_ph_op:int rd, int rs, int rt, int op, int sat
{
int i;
- signed32 h0 = 0;
- signed16 h1, h2;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 result = 0;
+ int32_t h0 = 0;
+ int16_t h1, h2;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)(v2 & 0xffff);
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)(v2 & 0xffff);
if (op == 0) // ADD
- h0 = (signed32)h1 + (signed32)h2;
+ h0 = (int32_t)h1 + (int32_t)h2;
else if (op == 1) // SUB
- h0 = (signed32)h1 - (signed32)h2;
+ h0 = (int32_t)h1 - (int32_t)h2;
else // MUL
- h0 = (signed32)h1 * (signed32)h2;
- if (h0 > (signed32)0x7fff || h0 < (signed32)0xffff8000)
+ h0 = (int32_t)h1 * (int32_t)h2;
+ if (h0 > (int32_t)0x7fff || h0 < (int32_t)0xffff8000)
{
if (op == 0 || op == 1) // ADD, SUB
DSPCR |= DSPCR_OUFLAG4;
@@ -48,13 +48,13 @@
DSPCR |= DSPCR_OUFLAG5;
if (sat == 1)
{
- if (h0 > (signed32)0x7fff)
+ if (h0 > (int32_t)0x7fff)
h0 = 0x7fff;
else
h0 = 0x8000;
}
}
- result |= ((unsigned32)((unsigned16)h0) << i);
+ result |= ((uint32_t)((uint16_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -62,17 +62,17 @@
// op: 0 = ADD, 1 = SUB
:function:::void:do_w_op:int rd, int rs, int rt, int op
{
- signed64 h0;
- signed32 h1, h2;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 result = 0;
- h1 = (signed32)v1;
- h2 = (signed32)v2;
+ int64_t h0;
+ int32_t h1, h2;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t result = 0;
+ h1 = (int32_t)v1;
+ h2 = (int32_t)v2;
if (op == 0) // ADD
- h0 = (signed64)h1 + (signed64)h2;
+ h0 = (int64_t)h1 + (int64_t)h2;
else // SUB
- h0 = (signed64)h1 - (signed64)h2;
+ h0 = (int64_t)h1 - (int64_t)h2;
if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000))
{
DSPCR |= DSPCR_OUFLAG4;
@@ -89,19 +89,19 @@
:function:::void:do_qb_op:int rd, int rs, int rt, int op, int sat
{
int i;
- unsigned32 h0;
- unsigned8 h1, h2;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 result = 0;
+ uint32_t h0;
+ uint8_t h1, h2;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8)
{
- h1 = (unsigned8)(v1 & 0xff);
- h2 = (unsigned8)(v2 & 0xff);
+ h1 = (uint8_t)(v1 & 0xff);
+ h2 = (uint8_t)(v2 & 0xff);
if (op == 0) // ADD
- h0 = (unsigned32)h1 + (unsigned32)h2;
+ h0 = (uint32_t)h1 + (uint32_t)h2;
else // SUB
- h0 = (unsigned32)h1 - (unsigned32)h2;
+ h0 = (uint32_t)h1 - (uint32_t)h2;
if (h0 & 0x100)
{
DSPCR |= DSPCR_OUFLAG4;
@@ -113,7 +113,7 @@
h0 = 0;
}
}
- result |= ((unsigned32)((unsigned8)h0) << i);
+ result |= ((uint32_t)((uint8_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -122,12 +122,12 @@
:function:::void:do_qb_shift:int rd, int rt, int shift, int op
{
int i, j;
- unsigned8 h0;
- unsigned32 v1 = GPR[rt];
- unsigned32 result = 0;
+ uint8_t h0;
+ uint32_t v1 = GPR[rt];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
- h0 = (unsigned8)(v1 & 0xff);
+ h0 = (uint8_t)(v1 & 0xff);
if (op == 0) // left
{
for (j = 7; j >= 8 - shift; j--)
@@ -142,7 +142,7 @@
}
else // right
h0 = h0 >> shift;
- result |= ((unsigned32)h0 << i);
+ result |= ((uint32_t)h0 << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -152,13 +152,13 @@
:function:::void:do_ph_shift:int rd, int rt, int shift, int op, int sat
{
int i, j;
- signed16 h0;
- unsigned32 v1 = GPR[rt];
- unsigned32 result = 0;
+ int16_t h0;
+ uint32_t v1 = GPR[rt];
+ uint32_t result = 0;
int setcond;
for (i = 0; i < 32; i += 16, v1 >>= 16)
{
- h0 = (signed16)(v1 & 0xffff);
+ h0 = (int16_t)(v1 & 0xffff);
if (op == 0) // left
{
setcond = 0;
@@ -203,7 +203,7 @@
h0 = h0 >> shift;
}
- result |= ((unsigned32)((unsigned16)h0) << i);
+ result |= ((uint32_t)((uint16_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -211,8 +211,8 @@
:function:::void:do_w_shll:int rd, int rt, int shift
{
int i;
- unsigned32 v1 = GPR[rt];
- unsigned32 result = 0;
+ uint32_t v1 = GPR[rt];
+ uint32_t result = 0;
int setcond = 0;
if (v1 & (1 << 31))
{
@@ -250,29 +250,29 @@
:function:::void:do_ph_s_absq:int rd, int rt
{
int i;
- signed16 h0;
- unsigned32 v1 = GPR[rt];
- unsigned32 result = 0;
+ int16_t h0;
+ uint32_t v1 = GPR[rt];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16)
{
- h0 = (signed16)(v1 & 0xffff);
- if (h0 == (signed16)0x8000)
+ h0 = (int16_t)(v1 & 0xffff);
+ if (h0 == (int16_t)0x8000)
{
DSPCR |= DSPCR_OUFLAG4;
h0 = 0x7fff;
}
else if (h0 & 0x8000)
h0 = -h0;
- result |= ((unsigned32)((unsigned16)h0) << i);
+ result |= ((uint32_t)((uint16_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
:function:::void:do_w_s_absq:int rd, int rt
{
- unsigned32 v1 = GPR[rt];
- signed32 h0 = (signed32)v1;
- if (h0 == (signed32)0x80000000)
+ uint32_t v1 = GPR[rt];
+ int32_t h0 = (int32_t)v1;
+ if (h0 == (int32_t)0x80000000)
{
DSPCR |= DSPCR_OUFLAG4;
h0 = 0x7fffffff;
@@ -285,30 +285,30 @@
:function:::void:do_qb_s_absq:int rd, int rt
{
int i;
- signed8 q0;
- unsigned32 v1 = GPR[rt];
- unsigned32 result = 0;
+ int8_t q0;
+ uint32_t v1 = GPR[rt];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
- q0 = (signed8)(v1 & 0xff);
- if (q0 == (signed8)0x80)
+ q0 = (int8_t)(v1 & 0xff);
+ if (q0 == (int8_t)0x80)
{
DSPCR |= DSPCR_OUFLAG4;
q0 = 0x7f;
}
else if (q0 & 0x80)
q0 = -q0;
- result |= ((unsigned32)((unsigned8)q0) << i);
+ result |= ((uint32_t)((uint8_t)q0) << i);
}
GPR[rd] = EXTEND32 (result);
}
:function:::void:do_addsc:int rd, int rs, int rt
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned64 h0;
- h0 = (unsigned64)v1 + (unsigned64)v2;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint64_t h0;
+ h0 = (uint64_t)v1 + (uint64_t)v2;
if (h0 & 0x100000000LL)
DSPCR |= DSPCR_CARRY;
GPR[rd] = EXTEND32 (h0);
@@ -316,13 +316,13 @@
:function:::void:do_addwc:int rd, int rs, int rt
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned64 h0;
- signed32 h1 = (signed32) v1;
- signed32 h2 = (signed32) v2;
- h0 = (signed64)h1 + (signed64)h2
- + (signed64)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK);
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint64_t h0;
+ int32_t h1 = (int32_t) v1;
+ int32_t h2 = (int32_t) v2;
+ h0 = (int64_t)h1 + (int64_t)h2
+ + (int64_t)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK);
if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000))
DSPCR |= DSPCR_OUFLAG4;
GPR[rd] = EXTEND32 (h0);
@@ -331,8 +331,8 @@
:function:::void:do_bitrev:int rd, int rt
{
int i;
- unsigned32 v1 = GPR[rt];
- unsigned32 h1 = 0;
+ uint32_t v1 = GPR[rt];
+ uint32_t h1 = 0;
for (i = 0; i < 16; i++)
{
if (v1 & (1 << i))
@@ -344,30 +344,30 @@
// op: 0 = EXTPV, 1 = EXTPDPV
:function:::void:do_extpv:int rt, int ac, int rs, int op
{
- unsigned32 size = GPR[rs] & 0x1f;
+ uint32_t size = GPR[rs] & 0x1f;
do_extp (SD_, rt, ac, size, op);
}
// op: 0 = EXTRV, 1 = EXTRV_R, 2 = EXTRV_RS
:function:::void:do_extrv:int rt, int ac, int rs, int op
{
- unsigned32 shift = GPR[rs] & 0x1f;
+ uint32_t shift = GPR[rs] & 0x1f;
do_w_extr (SD_, rt, ac, shift, op);
}
:function:::void:do_extrv_s_h:int rt, int ac, int rs
{
- unsigned32 shift = GPR[rs] & 0x1f;
+ uint32_t shift = GPR[rs] & 0x1f;
do_h_extr (SD_, rt, ac, shift);
}
:function:::void:do_insv:int rt, int rs
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
- unsigned32 size = (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK;
- unsigned32 mask1, mask2, mask3, result;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
+ uint32_t size = (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK;
+ uint32_t mask1, mask2, mask3, result;
if (size < 32)
mask1 = (1 << size) - 1;
else
@@ -394,11 +394,11 @@
:function:::void:do_modsub:int rd, int rs, int rt
{
- unsigned32 result = 0;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 decr = v2 & 0xff;
- unsigned32 lastindex = (v2 & 0xffff00) >> 8;
+ uint32_t result = 0;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t decr = v2 & 0xff;
+ uint32_t lastindex = (v2 & 0xffff00) >> 8;
if (v1 == 0)
result = lastindex;
else
@@ -408,7 +408,7 @@
:function:::void:do_mthlip:int rs, int ac
{
- unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
+ uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
DSPHI(ac) = DSPLO(ac);
DSPLO(ac) = GPR[rs];
if (pos >= 32)
@@ -422,29 +422,29 @@
:function:::void:do_mulsaq_s_w_ph:int ac, int rs, int rt
{
int i;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed16 h1, h2;
- signed32 result;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int16_t h1, h2;
+ int32_t result;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)(v2 & 0xffff);
- if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)(v2 & 0xffff);
+ if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
- result = (signed32) 0x7fffffff;
+ result = (int32_t) 0x7fffffff;
}
else
- result = ((signed32)h1 * (signed32)h2) << 1;
+ result = ((int32_t)h1 * (int32_t)h2) << 1;
if (i == 0)
- prod -= (signed64) result;
+ prod -= (int64_t) result;
else
- prod += (signed64) result;
+ prod += (int64_t) result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
@@ -453,26 +453,26 @@
:function:::void:do_ph_packrl:int rd, int rs, int rt
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
GPR[rd] = EXTEND32 ((v1 << 16) + (v2 >> 16));
}
:function:::void:do_qb_pick:int rd, int rs, int rt
{
int i, j;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned8 h1, h2;
- unsigned32 result = 0;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint8_t h1, h2;
+ uint32_t result = 0;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
- h1 = (unsigned8)(v1 & 0xff);
- h2 = (unsigned8)(v2 & 0xff);
+ h1 = (uint8_t)(v1 & 0xff);
+ h2 = (uint8_t)(v2 & 0xff);
if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j)))
- result |= (unsigned32)(h1 << i);
+ result |= (uint32_t)(h1 << i);
else
- result |= (unsigned32)(h2 << i);
+ result |= (uint32_t)(h2 << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -480,18 +480,18 @@
:function:::void:do_ph_pick:int rd, int rs, int rt
{
int i, j;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned16 h1, h2;
- unsigned32 result = 0;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint16_t h1, h2;
+ uint32_t result = 0;
for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16)
{
- h1 = (unsigned16)(v1 & 0xffff);
- h2 = (unsigned16)(v2 & 0xffff);
+ h1 = (uint16_t)(v1 & 0xffff);
+ h2 = (uint16_t)(v2 & 0xffff);
if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j)))
- result |= (unsigned32)(h1 << i);
+ result |= (uint32_t)(h1 << i);
else
- result |= (unsigned32)(h2 << i);
+ result |= (uint32_t)(h2 << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -499,7 +499,7 @@
// op: 0 = QBR, 1 = QBRA, 2 = QBL, 3 = QBLA
:function:::void:do_qb_ph_precequ:int rd, int rt, int op
{
- unsigned32 v1 = GPR[rt];
+ uint32_t v1 = GPR[rt];
if (op == 0)
GPR[rd] = EXTEND32 ((v1 & 0xff00) << 15) | ((v1 & 0xff) << 7);
else if (op == 1)
@@ -513,7 +513,7 @@
// op: 0 = QBR, 1 = QBRA, 2 = QBL, 3 = QBLA
:function:::void:do_qb_ph_preceu:int rd, int rt, int op
{
- unsigned32 v1 = GPR[rt];
+ uint32_t v1 = GPR[rt];
if (op == 0)
GPR[rd] = EXTEND32 ((v1 & 0xff00) << 8) | (v1 & 0xff);
else if (op == 1)
@@ -527,7 +527,7 @@
// op: 0 = .PHL, 1 = PHR
:function:::void:do_w_preceq:int rd, int rt, int op
{
- unsigned32 v1 = GPR[rt];
+ uint32_t v1 = GPR[rt];
if (op == 0)
GPR[rd] = EXTEND32 (v1 & 0xffff0000);
else if (op == 1)
@@ -536,19 +536,19 @@
:function:::void:do_w_ph_precrq:int rd, int rs, int rt
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 tempu = (v1 & 0xffff0000) >> 16;
- unsigned32 tempv = (v2 & 0xffff0000) >> 16;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t tempu = (v1 & 0xffff0000) >> 16;
+ uint32_t tempv = (v2 & 0xffff0000) >> 16;
GPR[rd] = EXTEND32 ((tempu << 16) | tempv);
}
// sat: 0 = PRECRQ.QB.PH, 1 = PRECRQU_S.QB.PH
:function:::void:do_ph_qb_precrq:int rd, int rs, int rt, int sat
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 tempu = 0, tempv = 0, tempw = 0, tempx = 0;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t tempu = 0, tempv = 0, tempw = 0, tempx = 0;
if (sat == 0)
{
tempu = (v1 & 0xff000000) >> 24;
@@ -563,7 +563,7 @@
DSPCR |= DSPCR_OUFLAG6;
tempu = 0;
}
- else if (!(v1 & 0x80000000) && ((v1 >> 16) > (unsigned32)0x7f80))
+ else if (!(v1 & 0x80000000) && ((v1 >> 16) > (uint32_t)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempu = 0xff;
@@ -575,7 +575,7 @@
DSPCR |= DSPCR_OUFLAG6;
tempv = 0;
}
- else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (unsigned32)0x7f80))
+ else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (uint32_t)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempv = 0xff;
@@ -587,7 +587,7 @@
DSPCR |= DSPCR_OUFLAG6;
tempw = 0;
}
- else if (!(v2 & 0x80000000) && ((v2 >> 16) > (unsigned32)0x7f80))
+ else if (!(v2 & 0x80000000) && ((v2 >> 16) > (uint32_t)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempw = 0xff;
@@ -599,7 +599,7 @@
DSPCR |= DSPCR_OUFLAG6;
tempx = 0;
}
- else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (unsigned32)0x7f80))
+ else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (uint32_t)0x7f80))
{
DSPCR |= DSPCR_OUFLAG6;
tempx = 0xff;
@@ -612,48 +612,48 @@
:function:::void:do_w_ph_rs_precrq:int rd, int rs, int rt
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed32 h1 = (signed32)v1;
- signed32 h2 = (signed32)v2;
- signed64 temp1 = (signed64)h1 + (signed64)0x8000;
- signed32 temp2;
- signed64 temp3 = (signed64)h2 + (signed64)0x8000;
- signed32 temp4;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int32_t h1 = (int32_t)v1;
+ int32_t h2 = (int32_t)v2;
+ int64_t temp1 = (int64_t)h1 + (int64_t)0x8000;
+ int32_t temp2;
+ int64_t temp3 = (int64_t)h2 + (int64_t)0x8000;
+ int32_t temp4;
if (((temp1 & 0x100000000LL) >> 1) != (temp1 & 0x80000000))
{
DSPCR |= DSPCR_OUFLAG6;
temp2 = 0x7fff;
}
else
- temp2 = (signed32)((temp1 & 0xffff0000) >> 16);
+ temp2 = (int32_t)((temp1 & 0xffff0000) >> 16);
if (((temp3 & 0x100000000LL) >> 1) != (temp3 & 0x80000000))
{
DSPCR |= DSPCR_OUFLAG6;
temp4 = 0x7fff;
}
else
- temp4 = (signed32)((temp3 & 0xffff0000) >> 16);
+ temp4 = (int32_t)((temp3 & 0xffff0000) >> 16);
GPR[rd] = EXTEND32 ((temp2 << 16) | temp4);
}
:function:::void:do_qb_w_raddu:int rd, int rs
{
int i;
- unsigned8 h0;
- unsigned32 v1 = GPR[rs];
- unsigned32 result = 0;
+ uint8_t h0;
+ uint32_t v1 = GPR[rs];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
- h0 = (unsigned8)(v1 & 0xff);
- result += (unsigned32)h0;
+ h0 = (uint8_t)(v1 & 0xff);
+ result += (uint32_t)h0;
}
GPR[rd] = EXTEND32 (result);
}
:function:::void:do_rddsp:int rd, int mask
{
- unsigned32 result = 0;
+ uint32_t result = 0;
if (mask & 0x1)
{
result &= (~DSPCR_POS_SMASK);
@@ -694,19 +694,19 @@
GPR[rd] = EXTEND32 ((p2 << 24) | (p2 << 16) | (p2 << 8) | p2);
else if (op == 1)
{
- unsigned32 v1 = GPR[p2] & 0xff;
+ uint32_t v1 = GPR[p2] & 0xff;
GPR[rd] = EXTEND32 ((v1 << 24) | (v1 << 16) | (v1 << 8) | v1);
}
else if (op == 2)
{
- signed32 v1 = p2;
+ int32_t v1 = p2;
if (v1 & 0x200)
v1 |= 0xfffffc00;
GPR[rd] = EXTEND32 ((v1 << 16) | (v1 & 0xffff));
}
else if (op == 3)
{
- unsigned32 v1 = GPR[p2];
+ uint32_t v1 = GPR[p2];
v1 = v1 & 0xffff;
GPR[rd] = EXTEND32 ((v1 << 16) | v1);
}
@@ -714,7 +714,7 @@
:function:::void:do_shilov:int ac, int rs
{
- signed32 shift = GPR[rs] & 0x3f;
+ int32_t shift = GPR[rs] & 0x3f;
do_shilo (SD_, ac, shift);
}
@@ -722,38 +722,38 @@
// sat: 0 = normal, 1 = saturate/rounding
:function:::void:do_ph_shl:int rd, int rt, int rs, int op, int sat
{
- unsigned32 shift = GPR[rs] & 0xf;
+ uint32_t shift = GPR[rs] & 0xf;
do_ph_shift (SD_, rd, rt, shift, op, sat);
}
// op: 0 = SHLLV, 1 = SHRLV
:function:::void:do_qb_shl:int rd, int rt, int rs, int op
{
- unsigned32 shift = GPR[rs] & 0x7;
+ uint32_t shift = GPR[rs] & 0x7;
do_qb_shift (SD_, rd, rt, shift, op);
}
:function:::void:do_w_s_shllv:int rd, int rt, int rs
{
- unsigned32 shift = GPR[rs] & 0x1f;
+ uint32_t shift = GPR[rs] & 0x1f;
do_w_shll (SD_, rd, rt, shift);
}
:function:::void:do_ph_shrlv:int rd, int rt, int rs
{
- unsigned32 shift = GPR[rs] & 0xf;
+ uint32_t shift = GPR[rs] & 0xf;
do_ph_shrl (SD_, rd, rt, shift);
}
:function:::void:do_w_r_shrav:int rd, int rt, int rs
{
- unsigned32 shift = GPR[rs] & 0x1f;
+ uint32_t shift = GPR[rs] & 0x1f;
do_w_shra (SD_, rd, rt, shift);
}
:function:::void:do_wrdsp:int rs, int mask
{
- unsigned32 v1 = GPR[rs];
+ uint32_t v1 = GPR[rs];
if (mask & 0x1)
{
DSPCR &= (~DSPCR_POS_SMASK);
@@ -789,25 +789,25 @@
// round: 0 = no rounding, 1 = rounding
:function:::void:do_qb_shrav:int rd, int rt, int rs, int round
{
- unsigned32 shift = GPR[rs] & 0x7;
+ uint32_t shift = GPR[rs] & 0x7;
do_qb_shra (SD_, rd, rt, shift, round);
}
:function:::void:do_append:int rt, int rs, int sa
{
- unsigned32 v0 = GPR[rs];
- unsigned32 v1 = GPR[rt];
- unsigned32 result;
- unsigned32 mask = (1 << sa) - 1;
+ uint32_t v0 = GPR[rs];
+ uint32_t v1 = GPR[rt];
+ uint32_t result;
+ uint32_t mask = (1 << sa) - 1;
result = (v1 << sa) | (v0 & mask);
GPR[rt] = EXTEND32 (result);
}
:function:::void:do_balign:int rt, int rs, int bp
{
- unsigned32 v0 = GPR[rs];
- unsigned32 v1 = GPR[rt];
- unsigned32 result;
+ uint32_t v0 = GPR[rs];
+ uint32_t v1 = GPR[rt];
+ uint32_t result;
if (bp == 0)
result = v1;
else
@@ -818,23 +818,23 @@
:function:::void:do_ph_w_mulsa:int ac, int rs, int rt
{
int i;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed16 h1, h2;
- signed32 result;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int16_t h1, h2;
+ int32_t result;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)(v2 & 0xffff);
- result = (signed32)h1 * (signed32)h2;
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)(v2 & 0xffff);
+ result = (int32_t)h1 * (int32_t)h2;
if (i == 0)
- prod -= (signed64) result;
+ prod -= (int64_t) result;
else
- prod += (signed64) result;
+ prod += (int64_t) result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
@@ -842,20 +842,20 @@
:function:::void:do_ph_qb_precr:int rd, int rs, int rt
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 tempu = (v1 & 0xff0000) >> 16;
- unsigned32 tempv = (v1 & 0xff);
- unsigned32 tempw = (v2 & 0xff0000) >> 16;
- unsigned32 tempx = (v2 & 0xff);
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t tempu = (v1 & 0xff0000) >> 16;
+ uint32_t tempv = (v1 & 0xff);
+ uint32_t tempw = (v2 & 0xff0000) >> 16;
+ uint32_t tempx = (v2 & 0xff);
GPR[rd] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx);
}
:function:::void:do_prepend:int rt, int rs, int sa
{
- unsigned32 v0 = GPR[rs];
- unsigned32 v1 = GPR[rt];
- unsigned32 result;
+ uint32_t v0 = GPR[rs];
+ uint32_t v1 = GPR[rt];
+ uint32_t result;
if (sa == 0)
result = v1;
else
@@ -865,8 +865,8 @@
:function:::void:do_w_shra:int rd, int rt, int shift
{
- unsigned32 result = GPR[rt];
- signed32 h0 = (signed32)result;
+ uint32_t result = GPR[rt];
+ int32_t h0 = (int32_t)result;
if (shift != 0 && (h0 & (1 << (shift-1))))
h0 = (h0 >> shift) + 1;
else
@@ -1200,24 +1200,24 @@
:function:::void:do_qb_muleu:int rd, int rs, int rt, int loc
{
int i;
- unsigned32 result = 0;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned16 h1, h2;
- unsigned32 prod;
+ uint32_t result = 0;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint16_t h1, h2;
+ uint32_t prod;
if (loc == 0)
v1 >>= 16;
for (i = 0; i < 32; i += 16, v1 >>= 8, v2 >>= 16)
{
- h1 = (unsigned16)(v1 & 0xff);
- h2 = (unsigned16)(v2 & 0xffff);
- prod = (unsigned32)h1 * (unsigned32)h2;
+ h1 = (uint16_t)(v1 & 0xff);
+ h2 = (uint16_t)(v2 & 0xffff);
+ prod = (uint32_t)h1 * (uint32_t)h2;
if (prod > 0xffff)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0xffff;
}
- result |= ((unsigned32)prod << i);
+ result |= ((uint32_t)prod << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -1240,27 +1240,27 @@
:function:::void:do_ph_mulq:int rd, int rs, int rt, int round
{
int i;
- unsigned32 result = 0;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed16 h1, h2;
- signed32 prod;
+ uint32_t result = 0;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int16_t h1, h2;
+ int32_t prod;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)(v2 & 0xffff);
- if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)(v2 & 0xffff);
+ if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0x7fffffff;
}
else
{
- prod = ((signed32)h1 * (signed32)h2) << 1;
+ prod = ((int32_t)h1 * (int32_t)h2) << 1;
if (round == 1)
- prod += (signed32)0x8000;
+ prod += (int32_t)0x8000;
}
- result |= (((unsigned32)prod >> 16) << i);
+ result |= (((uint32_t)prod >> 16) << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -1275,27 +1275,27 @@
// loc: 0 = phl, 1 = phr
:function:::void:do_ph_muleq:int rd, int rs, int rt, int loc
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed16 h1, h2;
- signed32 prod;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int16_t h1, h2;
+ int32_t prod;
if (loc == 0)
{
- h1 = (signed16)(v1 >> 16);
- h2 = (signed16)(v2 >> 16);
+ h1 = (int16_t)(v1 >> 16);
+ h2 = (int16_t)(v2 >> 16);
}
else
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)(v2 & 0xffff);
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)(v2 & 0xffff);
}
- if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
+ if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0x7fffffff;
}
else
- prod = ((signed32)h1 * (signed32)h2) << 1;
+ prod = ((int32_t)h1 * (int32_t)h2) << 1;
GPR[rd] = EXTEND32 (prod);
}
@@ -1318,12 +1318,12 @@
:function:::void:do_qb_dot_product:int ac, int rs, int rt, int op, int loc
{
int i;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned8 h1, h2;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint8_t h1, h2;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo;
if (loc == 0)
{
v1 >>= 16;
@@ -1331,12 +1331,12 @@
}
for (i = 0; i < 16; i += 8, v1 >>= 8, v2 >>= 8)
{
- h1 = (unsigned8)(v1 & 0xff);
- h2 = (unsigned8)(v2 & 0xff);
+ h1 = (uint8_t)(v1 & 0xff);
+ h2 = (uint8_t)(v2 & 0xff);
if (op == 0) // DPAU
- prod += (unsigned64)h1 * (unsigned64)h2;
+ prod += (uint64_t)h1 * (uint64_t)h2;
else // DPSU
- prod -= (unsigned64)h1 * (unsigned64)h2;
+ prod -= (uint64_t)h1 * (uint64_t)h2;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
@@ -1374,29 +1374,29 @@
:function:::void:do_ph_dot_product:int ac, int rs, int rt, int op
{
int i;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed16 h1, h2;
- signed32 result;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int16_t h1, h2;
+ int32_t result;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)(v2 & 0xffff);
- if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)(v2 & 0xffff);
+ if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
- result = (signed32)0x7fffffff;
+ result = (int32_t)0x7fffffff;
}
else
- result = ((signed32)h1 * (signed32)h2) << 1;
+ result = ((int32_t)h1 * (int32_t)h2) << 1;
if (op == 0) // DPAQ
- prod += (signed64)result;
+ prod += (int64_t)result;
else // DPSQ
- prod -= (signed64)result;
+ prod -= (int64_t)result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
@@ -1426,41 +1426,41 @@
// op: 0 = DPAQ 1 = DPSQ
:function:::void:do_w_dot_product:int ac, int rs, int rt, int op
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed32 h1, h2;
- signed64 result;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- unsigned32 resultlo;
- unsigned32 resulthi;
- unsigned32 carry;
- unsigned64 temp1;
- signed64 temp2;
- h1 = (signed32) v1;
- h2 = (signed32) v2;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int32_t h1, h2;
+ int64_t result;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ uint32_t resultlo;
+ uint32_t resulthi;
+ uint32_t carry;
+ uint64_t temp1;
+ int64_t temp2;
+ h1 = (int32_t) v1;
+ h2 = (int32_t) v2;
if (h1 == 0x80000000 && h2 == 0x80000000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
- result = (signed64) 0x7fffffffffffffffLL;
+ result = (int64_t) 0x7fffffffffffffffLL;
}
else
- result = ((signed64)h1 * (signed64)h2) << 1;
- resultlo = (unsigned32)(result);
- resulthi = (unsigned32)(result >> 32);
+ result = ((int64_t)h1 * (int64_t)h2) << 1;
+ resultlo = (uint32_t)(result);
+ resulthi = (uint32_t)(result >> 32);
if (op ==0) // DPAQ
{
- temp1 = (unsigned64)lo + (unsigned64)resultlo;
- carry = (unsigned32)((temp1 >> 32) & 1);
- temp2 = (signed64)((signed32)hi) + (signed64)((signed32)resulthi) +
- (signed64)((signed32)carry);
+ temp1 = (uint64_t)lo + (uint64_t)resultlo;
+ carry = (uint32_t)((temp1 >> 32) & 1);
+ temp2 = (int64_t)((int32_t)hi) + (int64_t)((int32_t)resulthi) +
+ (int64_t)((int32_t)carry);
}
else // DPSQ
{
- temp1 = (unsigned64)lo - (unsigned64)resultlo;
- carry = (unsigned32)((temp1 >> 32) & 1);
- temp2 = (signed64)((signed32)hi) - (signed64)((signed32)resulthi) -
- (signed64)((signed32)carry);
+ temp1 = (uint64_t)lo - (uint64_t)resultlo;
+ carry = (uint32_t)((temp1 >> 32) & 1);
+ temp2 = (int64_t)((int32_t)hi) - (int64_t)((int32_t)resulthi) -
+ (int64_t)((int32_t)carry);
}
if (((temp2 & 0x100000000LL) >> 1) != (temp2 & 0x80000000LL))
{
@@ -1502,38 +1502,38 @@
:function:::void:do_ph_maq:int ac, int rs, int rt, int op, int loc
{
int i;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed16 h1, h2;
- signed32 result;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int16_t h1, h2;
+ int32_t result;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
if (loc == 0)
{
- h1 = (signed16)(v1 >> 16);
- h2 = (signed16)(v2 >> 16);
+ h1 = (int16_t)(v1 >> 16);
+ h2 = (int16_t)(v2 >> 16);
}
else
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)(v2 & 0xffff);
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)(v2 & 0xffff);
}
- if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
+ if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
- result = (signed32)0x7fffffff;
+ result = (int32_t)0x7fffffff;
}
else
- result = ((signed32)h1 * (signed32)h2) << 1;
- prod += (signed64)result;
+ result = ((int32_t)h1 * (int32_t)h2) << 1;
+ prod += (int64_t)result;
if (op == 1) // MAQ_SA
{
if (prod & 0x8000000000000000LL)
{
for (i = 62; i >= 31; i--)
{
- if (!(prod & ((signed64)1 << i)))
+ if (!(prod & ((int64_t)1 << i)))
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
prod = 0xffffffff80000000LL;
@@ -1545,7 +1545,7 @@
{
for (i = 62; i >= 31; i--)
{
- if (prod & ((signed64)1 << i))
+ if (prod & ((int64_t)1 << i))
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
prod = 0x7fffffff;
@@ -1632,14 +1632,14 @@
:function:::void:do_qb_cmpu:int rs, int rt, int op
{
int i, j;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned8 h1, h2;
- unsigned32 mask;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint8_t h1, h2;
+ uint32_t mask;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
- h1 = (unsigned8)(v1 & 0xff);
- h2 = (unsigned8)(v2 & 0xff);
+ h1 = (uint8_t)(v1 & 0xff);
+ h2 = (uint8_t)(v2 & 0xff);
mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
DSPCR &= mask;
if (op == 0) // EQ
@@ -1676,14 +1676,14 @@
:function:::void:do_qb_cmpgu:int rd, int rs, int rt, int op
{
int i, j;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned8 h1, h2;
- unsigned32 result = 0;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint8_t h1, h2;
+ uint32_t result = 0;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
- h1 = (unsigned8)(v1 & 0xff);
- h2 = (unsigned8)(v2 & 0xff);
+ h1 = (uint8_t)(v1 & 0xff);
+ h2 = (uint8_t)(v2 & 0xff);
if (op == 0) // EQ
result |= ((h1 == h2) << j);
else if (op == 1) // LT
@@ -1719,14 +1719,14 @@
:function:::void:do_ph_cmpu:int rs, int rt, int op
{
int i, j;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed16 h1, h2;
- unsigned32 mask;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int16_t h1, h2;
+ uint32_t mask;
for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16)
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)(v2 & 0xffff);
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)(v2 & 0xffff);
mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
DSPCR &= mask;
if (op == 0) // EQ
@@ -1784,16 +1784,16 @@
:function:::void:do_w_extr:int rt, int ac, int shift, int op
{
int i;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
- signed64 result = (signed64)prod;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo;
+ int64_t result = (int64_t)prod;
int setcond = 0;
if (!(prod & 0x8000000000000000LL))
{
for (i = 62; i >= (shift + 31); i--)
{
- if (prod & ((unsigned64)1 << i))
+ if (prod & ((uint64_t)1 << i))
{
DSPCR |= DSPCR_OUFLAG7;
setcond = 1;
@@ -1810,7 +1810,7 @@
{
for (i = 62; i >= (shift + 31); i--)
{
- if (!(prod & ((unsigned64)1 << i)))
+ if (!(prod & ((uint64_t)1 << i)))
{
DSPCR |= DSPCR_OUFLAG7;
setcond = 2;
@@ -1889,11 +1889,11 @@
:function:::void:do_h_extr:int rt, int ac, int shift
{
int i;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
- signed64 result = (signed64)prod;
- signed64 value = 0xffffffffffff8000LL;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo;
+ int64_t result = (int64_t)prod;
+ int64_t value = 0xffffffffffff8000LL;
result >>= shift;
if (result > 0x7fff)
{
@@ -1925,15 +1925,15 @@
// op: 0 = EXTP, 1 = EXTPDP
:function:::void:do_extp:int rt, int ac, int size, int op
{
- signed32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
- unsigned64 result = 0;
+ int32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo;
+ uint64_t result = 0;
if (pos - (size + 1) >= -1)
{
prod >>= (pos - size);
- result = prod & (((unsigned64)1 << (size + 1)) - 1);
+ result = prod & (((uint64_t)1 << (size + 1)) - 1);
DSPCR &= (~DSPCR_EFI_SMASK);
if (op == 1) // EXTPDP
{
@@ -1986,9 +1986,9 @@
:function:::void:do_shilo:int ac, int shift
{
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo;
if (shift > 31)
shift = shift - 64;
if (shift >= 0)
@@ -2061,7 +2061,7 @@
"bposge32 <OFFSET>"
*dsp:
{
- unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
+ uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
address_word offset = EXTEND16 (OFFSET) << 2;
if (pos >= 32)
{
diff --git a/sim/mips/dsp2.igen b/sim/mips/dsp2.igen
index 299eb2f001fc..032ef1e043f8 100644
--- a/sim/mips/dsp2.igen
+++ b/sim/mips/dsp2.igen
@@ -26,20 +26,20 @@
:function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat
{
int i;
- unsigned32 h0;
- unsigned16 h1, h2;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 result = 0;
+ uint32_t h0;
+ uint16_t h1, h2;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
- h1 = (unsigned16)(v1 & 0xffff);
- h2 = (unsigned16)(v2 & 0xffff);
+ h1 = (uint16_t)(v1 & 0xffff);
+ h2 = (uint16_t)(v2 & 0xffff);
if (op == 0) // ADD
- h0 = (unsigned32)h1 + (unsigned32)h2;
+ h0 = (uint32_t)h1 + (uint32_t)h2;
else // SUB
- h0 = (unsigned32)h1 - (unsigned32)h2;
- if (op == 0 && (h0 > (unsigned32)0x0000ffff)) // ADD SAT
+ h0 = (uint32_t)h1 - (uint32_t)h2;
+ if (op == 0 && (h0 > (uint32_t)0x0000ffff)) // ADD SAT
{
DSPCR |= DSPCR_OUFLAG4;
if (sat == 1)
@@ -51,7 +51,7 @@
if (sat == 1)
h0 = 0x0;
}
- result |= ((unsigned32)((unsigned16)h0) << i);
+ result |= ((uint32_t)((uint16_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -61,24 +61,24 @@
:function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round
{
int i;
- unsigned32 h0;
- unsigned8 h1, h2;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 result = 0;
+ uint32_t h0;
+ uint8_t h1, h2;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8)
{
- h1 = (unsigned8)(v1 & 0xff);
- h2 = (unsigned8)(v2 & 0xff);
+ h1 = (uint8_t)(v1 & 0xff);
+ h2 = (uint8_t)(v2 & 0xff);
if (op == 0) // ADD
- h0 = (unsigned32)h1 + (unsigned32)h2;
+ h0 = (uint32_t)h1 + (uint32_t)h2;
else // SUB
- h0 = (unsigned32)h1 - (unsigned32)h2;
+ h0 = (uint32_t)h1 - (uint32_t)h2;
if (round == 1)
h0 = (h0 + 1) >> 1;
else
h0 = h0 >> 1;
- result |= ((unsigned32)((unsigned8)h0) << i);
+ result |= ((uint32_t)((uint8_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -87,15 +87,15 @@
:function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op
{
int i, j;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned8 h1, h2;
- unsigned32 result = 0;
- unsigned32 mask;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint8_t h1, h2;
+ uint32_t result = 0;
+ uint32_t mask;
for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
{
- h1 = (unsigned8)(v1 & 0xff);
- h2 = (unsigned8)(v2 & 0xff);
+ h1 = (uint8_t)(v1 & 0xff);
+ h2 = (uint8_t)(v2 & 0xff);
mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
DSPCR &= mask;
if (op == 0) // EQ
@@ -121,22 +121,22 @@
:function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op
{
int i;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed16 h1, h2;
- signed32 result;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int16_t h1, h2;
+ int32_t result;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)(v2 & 0xffff);
- result = (signed32)h1 * (signed32)h2;
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)(v2 & 0xffff);
+ result = (int32_t)h1 * (int32_t)h2;
if (op == 0) // DPA
- prod += (signed64)result;
+ prod += (int64_t)result;
else // DPS
- prod -= (signed64)result;
+ prod -= (int64_t)result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
@@ -145,37 +145,37 @@
// round: 0 = no rounding, 1 = rounding
:function:::void:do_w_mulq:int rd, int rs, int rt, int round
{
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed32 w1, w2;
- signed64 prod;
- unsigned32 result;
- w1 = (signed32) v1;
- w2 = (signed32) v2;
- if (w1 == (signed32) 0x80000000 && w2 == (signed32) 0x80000000)
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int32_t w1, w2;
+ int64_t prod;
+ uint32_t result;
+ w1 = (int32_t) v1;
+ w2 = (int32_t) v2;
+ if (w1 == (int32_t) 0x80000000 && w2 == (int32_t) 0x80000000)
{
DSPCR |= DSPCR_OUFLAG5;
prod = 0x7fffffff;
}
else
{
- prod = ((signed64) w1 * (signed64) w2) << 1;
+ prod = ((int64_t) w1 * (int64_t) w2) << 1;
if (round == 1)
prod += 0x0000000080000000LL;
prod = prod >> 32;
}
- result = (unsigned32) prod;
+ result = (uint32_t) prod;
GPR[rd] = EXTEND32 (result);
}
// round: 0 = no rounding, 1 = rounding
:function:::void:do_precr_sra:int rt, int rs, int sa, int round
{
- unsigned32 v1 = GPR[rt];
- unsigned32 v2 = GPR[rs];
- signed32 w1 = (signed32) v1;
- signed32 w2 = (signed32) v2;
- signed32 result;
+ uint32_t v1 = GPR[rt];
+ uint32_t v2 = GPR[rs];
+ int32_t w1 = (int32_t) v1;
+ int32_t w2 = (int32_t) v2;
+ int32_t result;
if (sa != 0)
{
if (round == 1 && (w1 & (1 << (sa - 1))))
@@ -196,12 +196,12 @@
:function:::void:do_qb_shra:int rd, int rt, int shift, int round
{
int i, j;
- signed8 q0;
- unsigned32 v1 = GPR[rt];
- unsigned32 result = 0;
+ int8_t q0;
+ uint32_t v1 = GPR[rt];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 8, v1 >>= 8)
{
- q0 = (signed8)(v1 & 0xff);
+ q0 = (int8_t)(v1 & 0xff);
if (shift != 0)
{
if (round == 1 && (q0 & (1 << (shift - 1))))
@@ -209,7 +209,7 @@
else
q0 = q0 >> shift;
}
- result |= ((unsigned32)((unsigned8)q0) << i);
+ result |= ((uint32_t)((uint8_t)q0) << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -217,14 +217,14 @@
:function:::void:do_ph_shrl:int rd, int rt, int shift
{
int i, j;
- unsigned16 h0;
- unsigned32 v1 = GPR[rt];
- unsigned32 result = 0;
+ uint16_t h0;
+ uint32_t v1 = GPR[rt];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16)
{
- h0 = (unsigned16)(v1 & 0xffff);
+ h0 = (uint16_t)(v1 & 0xffff);
h0 = h0 >> shift;
- result |= ((unsigned32)h0 << i);
+ result |= ((uint32_t)h0 << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -234,24 +234,24 @@
:function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round
{
int i;
- signed32 h0;
- signed16 h1, h2;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- unsigned32 result = 0;
+ int32_t h0;
+ int16_t h1, h2;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ uint32_t result = 0;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)(v2 & 0xffff);
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)(v2 & 0xffff);
if (op == 0) // ADD
- h0 = (signed32)h1 + (signed32)h2;
+ h0 = (int32_t)h1 + (int32_t)h2;
else // SUB
- h0 = (signed32)h1 - (signed32)h2;
+ h0 = (int32_t)h1 - (int32_t)h2;
if (round == 1)
h0 = (h0 + 1) >> 1;
else
h0 = h0 >> 1;
- result |= ((unsigned32)((unsigned16)h0) << i);
+ result |= ((uint32_t)((uint16_t)h0) << i);
}
GPR[rd] = EXTEND32 (result);
}
@@ -261,13 +261,13 @@
:function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round
{
int i;
- signed64 v0;
- signed32 v1 = (signed32)GPR[rs];
- signed32 v2 = (signed32)GPR[rt];
+ int64_t v0;
+ int32_t v1 = (int32_t)GPR[rs];
+ int32_t v2 = (int32_t)GPR[rt];
if (op == 0) // ADD
- v0 = (signed64)v1 + (signed64)v2;
+ v0 = (int64_t)v1 + (int64_t)v2;
else // SUB
- v0 = (signed64)v1 - (signed64)v2;
+ v0 = (int64_t)v1 - (int64_t)v2;
if (round == 1)
v0 = (v0 + 1) >> 1;
else
@@ -279,22 +279,22 @@
:function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op
{
int i;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed16 h1, h2;
- signed32 result;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int16_t h1, h2;
+ int32_t result;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)((v2 & 0xffff0000) >> 16);
- result = (signed32)h1 * (signed32)h2;
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)((v2 & 0xffff0000) >> 16);
+ result = (int32_t)h1 * (int32_t)h2;
if (op == 0) // DPAX
- prod += (signed64)result;
+ prod += (int64_t)result;
else // DPSX
- prod -= (signed64)result;
+ prod -= (int64_t)result;
}
DSPLO(ac) = EXTEND32 (prod);
DSPHI(ac) = EXTEND32 (prod >> 32);
@@ -305,35 +305,35 @@
:function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat
{
int i;
- unsigned32 v1 = GPR[rs];
- unsigned32 v2 = GPR[rt];
- signed16 h1, h2;
- signed32 result;
- unsigned32 lo = DSPLO(ac);
- unsigned32 hi = DSPHI(ac);
- signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
- signed64 max, min;
+ uint32_t v1 = GPR[rs];
+ uint32_t v2 = GPR[rt];
+ int16_t h1, h2;
+ int32_t result;
+ uint32_t lo = DSPLO(ac);
+ uint32_t hi = DSPHI(ac);
+ int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo);
+ int64_t max, min;
for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
{
- h1 = (signed16)(v1 & 0xffff);
- h2 = (signed16)((v2 & 0xffff0000) >> 16);
- if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
+ h1 = (int16_t)(v1 & 0xffff);
+ h2 = (int16_t)((v2 & 0xffff0000) >> 16);
+ if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
result = 0x7fffffff;
}
else
- result = ((signed32)h1 * (signed32)h2) << 1;
+ result = ((int32_t)h1 * (int32_t)h2) << 1;
if (op == 0) // DPAQX
- prod += (signed64)result;
+ prod += (int64_t)result;
else // DPSQX
- prod -= (signed64)result;
+ prod -= (int64_t)result;
}
// Saturation on the accumulator.
if (sat == 1)
{
- max = (signed64) 0x7fffffffLL;
- min = (signed64) 0xffffffff80000000LL;
+ max = (int64_t) 0x7fffffffLL;
+ min = (int64_t) 0xffffffff80000000LL;
if (prod > max)
{
DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index ede1e261d743..65015623ee52 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -718,7 +718,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
for (loop = 0; (loop < idt_monitor_size); loop += 4)
{
address_word vaddr = (idt_monitor_base + loop);
- unsigned32 insn = (RSVD_INSTRUCTION |
+ uint32_t insn = (RSVD_INSTRUCTION |
(((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
<< RSVD_INSTRUCTION_ARG_SHIFT));
H2T (insn);
@@ -737,7 +737,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
unsigned loop;
for (loop = 0; (loop < 24); loop++)
{
- unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
+ uint32_t value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
switch (loop)
{
case 0: /* read */
@@ -787,7 +787,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
(pmon_monitor_base != 0) ||
(lsipmon_monitor_base != 0))
{
- unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
+ uint32_t halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
HALT_INSTRUCTION /* BREAK */ };
H2T (halt[0]);
H2T (halt[1]);
@@ -869,12 +869,12 @@ mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
if (length == 8)
{
cpu->fgr[rn - FGR_BASE] =
- (unsigned32) T2H_8 (*(unsigned64*)memory);
+ (uint32_t) T2H_8 (*(uint64_t*)memory);
return 8;
}
else
{
- cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
+ cpu->fgr[rn - FGR_BASE] = T2H_4 (*(uint32_t*)memory);
return 4;
}
}
@@ -882,12 +882,12 @@ mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
if (length == 8)
{
- cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
+ cpu->fgr[rn - FGR_BASE] = T2H_8 (*(uint64_t*)memory);
return 8;
}
else
{
- cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
+ cpu->fgr[rn - FGR_BASE] = T2H_4 (*(uint32_t*)memory);
return 4;
}
}
@@ -898,12 +898,12 @@ mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
if (length == 8)
{
cpu->registers[rn] =
- (unsigned32) T2H_8 (*(unsigned64*)memory);
+ (uint32_t) T2H_8 (*(uint64_t*)memory);
return 8;
}
else
{
- cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
+ cpu->registers[rn] = T2H_4 (*(uint32_t*)memory);
return 4;
}
}
@@ -911,12 +911,12 @@ mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
if (length == 8)
{
- cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
+ cpu->registers[rn] = T2H_8 (*(uint64_t*)memory);
return 8;
}
else
{
- cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
+ cpu->registers[rn] = (int32_t) T2H_4(*(uint32_t*)memory);
return 4;
}
}
@@ -943,13 +943,13 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
if (length == 8)
{
- *(unsigned64*)memory =
- H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
+ *(uint64_t*)memory =
+ H2T_8 ((uint32_t) (cpu->fgr[rn - FGR_BASE]));
return 8;
}
else
{
- *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
+ *(uint32_t*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
return 4;
}
}
@@ -957,12 +957,12 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
if (length == 8)
{
- *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
+ *(uint64_t*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
return 8;
}
else
{
- *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
+ *(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->fgr[rn - FGR_BASE]));
return 4;
}
}
@@ -972,13 +972,13 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
if (length == 8)
{
- *(unsigned64*)memory =
- H2T_8 ((unsigned32) (cpu->registers[rn]));
+ *(uint64_t*)memory =
+ H2T_8 ((uint32_t) (cpu->registers[rn]));
return 8;
}
else
{
- *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
+ *(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->registers[rn]));
return 4;
}
}
@@ -986,13 +986,13 @@ mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
if (length == 8)
{
- *(unsigned64*)memory =
- H2T_8 ((unsigned64) (cpu->registers[rn]));
+ *(uint64_t*)memory =
+ H2T_8 ((uint64_t) (cpu->registers[rn]));
return 8;
}
else
{
- *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
+ *(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->registers[rn]));
return 4;
}
}
@@ -1028,7 +1028,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
These addresses work as is on 64-bit targets but
can be truncated for 32-bit targets. */
if (WITH_TARGET_WORD_BITSIZE == 32)
- pc = (unsigned32) pc;
+ pc = (uint32_t) pc;
CPU_PC_SET (cpu, pc);
}
@@ -2321,7 +2321,7 @@ decode_coproc (SIM_DESC sd,
/* CPR[0,rd] = GPR[rt]; */
default:
if (op == cp0_mfc0 || op == cp0_dmfc0)
- GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
+ GPR[rt] = (signed_word) (int32_t) COP0_GPR[rd];
else
COP0_GPR[rd] = GPR[rt];
#if 0
@@ -2336,7 +2336,7 @@ decode_coproc (SIM_DESC sd,
&& rd == 16)
{
/* [D]MFC0 RT,C0_CONFIG,SEL */
- signed32 cfg = 0;
+ int32_t cfg = 0;
switch (sel)
{
case 0:
diff --git a/sim/mips/m16.igen b/sim/mips/m16.igen
index 3641e3652bc1..1d53d187596e 100644
--- a/sim/mips/m16.igen
+++ b/sim/mips/m16.igen
@@ -454,7 +454,7 @@
*mips16:
*vr4100:
{
- unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2);
+ uint32_t temp = (basepc (SD_) & ~3) + (IMMED << 2);
GPR[TRX] = EXTEND32 (temp);
}
@@ -463,7 +463,7 @@
*mips16:
*vr4100:
{
- unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
+ uint32_t temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
GPR[TRX] = EXTEND32 (temp);
}
diff --git a/sim/mips/m16e.igen b/sim/mips/m16e.igen
index afd0e1f8f6c4..cb8948906707 100644
--- a/sim/mips/m16e.igen
+++ b/sim/mips/m16e.igen
@@ -55,7 +55,7 @@
*mips16e:
{
TRACE_ALU_INPUT1 (GPR[TRX]);
- GPR[TRX] = (unsigned_word)(unsigned8)(GPR[TRX]);
+ GPR[TRX] = (unsigned_word)(uint8_t)(GPR[TRX]);
TRACE_ALU_RESULT (GPR[TRX]);
}
@@ -64,7 +64,7 @@
*mips16e:
{
TRACE_ALU_INPUT1 (GPR[TRX]);
- GPR[TRX] = (unsigned_word)(unsigned16)(GPR[TRX]);
+ GPR[TRX] = (unsigned_word)(uint16_t)(GPR[TRX]);
TRACE_ALU_RESULT (GPR[TRX]);
}
@@ -74,7 +74,7 @@
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT1 (GPR[TRX]);
- GPR[TRX] = (unsigned_word)(unsigned32)(GPR[TRX]);
+ GPR[TRX] = (unsigned_word)(uint32_t)(GPR[TRX]);
TRACE_ALU_RESULT (GPR[TRX]);
}
diff --git a/sim/mips/mdmx.c b/sim/mips/mdmx.c
index 41830ecb7690..e355da9193bc 100644
--- a/sim/mips/mdmx.c
+++ b/sim/mips/mdmx.c
@@ -54,10 +54,10 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
the (not guaranteed portable) assumption that right shifts of signed
quantities in C do sign extension. */
-typedef unsigned64 unsigned48;
+typedef uint64_t unsigned48;
#define MASK48 (UNSIGNED64 (0xffffffffffff))
-typedef unsigned32 unsigned24;
+typedef uint32_t unsigned24;
#define MASK24 (UNSIGNED32 (0xffffff))
typedef enum {
@@ -71,12 +71,12 @@ typedef enum {
sel_imm /* immediate select */
} VT_select;
-#define OB_MAX ((unsigned8)0xFF)
-#define QH_MIN ((signed16)0x8000)
-#define QH_MAX ((signed16)0x7FFF)
+#define OB_MAX ((uint8_t)0xFF)
+#define QH_MIN ((int16_t)0x8000)
+#define QH_MAX ((int16_t)0x7FFF)
-#define OB_CLAMP(x) ((unsigned8)((x) > OB_MAX ? OB_MAX : (x)))
-#define QH_CLAMP(x) ((signed16)((x) < QH_MIN ? QH_MIN : \
+#define OB_CLAMP(x) ((uint8_t)((x) > OB_MAX ? OB_MAX : (x)))
+#define QH_CLAMP(x) ((int16_t)((x) < QH_MIN ? QH_MIN : \
((x) > QH_MAX ? QH_MAX : (x))))
#define MX_FMT(fmtsel) (((fmtsel) & 0x1) == 0 ? mdmx_ob : mdmx_qh)
@@ -84,170 +84,170 @@ typedef enum {
(((fmtsel) & 0x18) == 0x10 ? sel_vect : sel_imm))
#define QH_ELEM(v,fmtsel) \
- ((signed16)(((v) >> (((fmtsel) & 0xC) << 2)) & 0xFFFF))
+ ((int16_t)(((v) >> (((fmtsel) & 0xC) << 2)) & 0xFFFF))
#define OB_ELEM(v,fmtsel) \
- ((unsigned8)(((v) >> (((fmtsel) & 0xE) << 2)) & 0xFF))
+ ((uint8_t)(((v) >> (((fmtsel) & 0xE) << 2)) & 0xFF))
-typedef signed16 (*QH_FUNC)(signed16, signed16);
-typedef unsigned8 (*OB_FUNC)(unsigned8, unsigned8);
+typedef int16_t (*QH_FUNC)(int16_t, int16_t);
+typedef uint8_t (*OB_FUNC)(uint8_t, uint8_t);
/* vectorized logical operators */
-static signed16
-AndQH(signed16 ts, signed16 tt)
+static int16_t
+AndQH(int16_t ts, int16_t tt)
{
- return (signed16)((unsigned16)ts & (unsigned16)tt);
+ return (int16_t)((uint16_t)ts & (uint16_t)tt);
}
-static unsigned8
-AndOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+AndOB(uint8_t ts, uint8_t tt)
{
return ts & tt;
}
-static signed16
-NorQH(signed16 ts, signed16 tt)
+static int16_t
+NorQH(int16_t ts, int16_t tt)
{
- return (signed16)(((unsigned16)ts | (unsigned16)tt) ^ 0xFFFF);
+ return (int16_t)(((uint16_t)ts | (uint16_t)tt) ^ 0xFFFF);
}
-static unsigned8
-NorOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+NorOB(uint8_t ts, uint8_t tt)
{
return (ts | tt) ^ 0xFF;
}
-static signed16
-OrQH(signed16 ts, signed16 tt)
+static int16_t
+OrQH(int16_t ts, int16_t tt)
{
- return (signed16)((unsigned16)ts | (unsigned16)tt);
+ return (int16_t)((uint16_t)ts | (uint16_t)tt);
}
-static unsigned8
-OrOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+OrOB(uint8_t ts, uint8_t tt)
{
return ts | tt;
}
-static signed16
-XorQH(signed16 ts, signed16 tt)
+static int16_t
+XorQH(int16_t ts, int16_t tt)
{
- return (signed16)((unsigned16)ts ^ (unsigned16)tt);
+ return (int16_t)((uint16_t)ts ^ (uint16_t)tt);
}
-static unsigned8
-XorOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+XorOB(uint8_t ts, uint8_t tt)
{
return ts ^ tt;
}
-static signed16
-SLLQH(signed16 ts, signed16 tt)
+static int16_t
+SLLQH(int16_t ts, int16_t tt)
{
- unsigned32 s = (unsigned32)tt & 0xF;
- return (signed16)(((unsigned32)ts << s) & 0xFFFF);
+ uint32_t s = (uint32_t)tt & 0xF;
+ return (int16_t)(((uint32_t)ts << s) & 0xFFFF);
}
-static unsigned8
-SLLOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+SLLOB(uint8_t ts, uint8_t tt)
{
- unsigned32 s = tt & 0x7;
+ uint32_t s = tt & 0x7;
return (ts << s) & 0xFF;
}
-static signed16
-SRLQH(signed16 ts, signed16 tt)
+static int16_t
+SRLQH(int16_t ts, int16_t tt)
{
- unsigned32 s = (unsigned32)tt & 0xF;
- return (signed16)((unsigned16)ts >> s);
+ uint32_t s = (uint32_t)tt & 0xF;
+ return (int16_t)((uint16_t)ts >> s);
}
-static unsigned8
-SRLOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+SRLOB(uint8_t ts, uint8_t tt)
{
- unsigned32 s = tt & 0x7;
+ uint32_t s = tt & 0x7;
return ts >> s;
}
/* Vectorized arithmetic operators. */
-static signed16
-AddQH(signed16 ts, signed16 tt)
+static int16_t
+AddQH(int16_t ts, int16_t tt)
{
- signed32 t = (signed32)ts + (signed32)tt;
+ int32_t t = (int32_t)ts + (int32_t)tt;
return QH_CLAMP(t);
}
-static unsigned8
-AddOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+AddOB(uint8_t ts, uint8_t tt)
{
- unsigned32 t = (unsigned32)ts + (unsigned32)tt;
+ uint32_t t = (uint32_t)ts + (uint32_t)tt;
return OB_CLAMP(t);
}
-static signed16
-SubQH(signed16 ts, signed16 tt)
+static int16_t
+SubQH(int16_t ts, int16_t tt)
{
- signed32 t = (signed32)ts - (signed32)tt;
+ int32_t t = (int32_t)ts - (int32_t)tt;
return QH_CLAMP(t);
}
-static unsigned8
-SubOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+SubOB(uint8_t ts, uint8_t tt)
{
- signed32 t;
- t = (signed32)ts - (signed32)tt;
+ int32_t t;
+ t = (int32_t)ts - (int32_t)tt;
if (t < 0)
t = 0;
- return (unsigned8)t;
+ return (uint8_t)t;
}
-static signed16
-MinQH(signed16 ts, signed16 tt)
+static int16_t
+MinQH(int16_t ts, int16_t tt)
{
return (ts < tt ? ts : tt);
}
-static unsigned8
-MinOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+MinOB(uint8_t ts, uint8_t tt)
{
return (ts < tt ? ts : tt);
}
-static signed16
-MaxQH(signed16 ts, signed16 tt)
+static int16_t
+MaxQH(int16_t ts, int16_t tt)
{
return (ts > tt ? ts : tt);
}
-static unsigned8
-MaxOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+MaxOB(uint8_t ts, uint8_t tt)
{
return (ts > tt ? ts : tt);
}
-static signed16
-MulQH(signed16 ts, signed16 tt)
+static int16_t
+MulQH(int16_t ts, int16_t tt)
{
- signed32 t = (signed32)ts * (signed32)tt;
+ int32_t t = (int32_t)ts * (int32_t)tt;
return QH_CLAMP(t);
}
-static unsigned8
-MulOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+MulOB(uint8_t ts, uint8_t tt)
{
- unsigned32 t = (unsigned32)ts * (unsigned32)tt;
+ uint32_t t = (uint32_t)ts * (uint32_t)tt;
return OB_CLAMP(t);
}
/* "msgn" and "sra" are defined only for QH format. */
-static signed16
-MsgnQH(signed16 ts, signed16 tt)
+static int16_t
+MsgnQH(int16_t ts, int16_t tt)
{
- signed16 t;
+ int16_t t;
if (ts < 0)
t = (tt == QH_MIN ? QH_MAX : -tt);
else if (ts == 0)
@@ -257,26 +257,26 @@ MsgnQH(signed16 ts, signed16 tt)
return t;
}
-static signed16
-SRAQH(signed16 ts, signed16 tt)
+static int16_t
+SRAQH(int16_t ts, int16_t tt)
{
- unsigned32 s = (unsigned32)tt & 0xF;
- return (signed16)((signed32)ts >> s);
+ uint32_t s = (uint32_t)tt & 0xF;
+ return (int16_t)((int32_t)ts >> s);
}
/* "pabsdiff" and "pavg" are defined only for OB format. */
-static unsigned8
-AbsDiffOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+AbsDiffOB(uint8_t ts, uint8_t tt)
{
return (ts >= tt ? ts - tt : tt - ts);
}
-static unsigned8
-AvgOB(unsigned8 ts, unsigned8 tt)
+static uint8_t
+AvgOB(uint8_t ts, uint8_t tt)
{
- return ((unsigned32)ts + (unsigned32)tt + 1) >> 1;
+ return ((uint32_t)ts + (uint32_t)tt + 1) >> 1;
}
@@ -297,35 +297,35 @@ static const OB_FUNC ob_func[] = {
/* Auxiliary functions for CPR updates. */
/* Vector mapping for QH format. */
-static unsigned64
-qh_vector_op(unsigned64 v1, unsigned64 v2, QH_FUNC func)
+static uint64_t
+qh_vector_op(uint64_t v1, uint64_t v2, QH_FUNC func)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i;
- signed16 h, h1, h2;
+ int16_t h, h1, h2;
for (i = 0; i < 64; i += 16)
{
- h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16;
- h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16;
+ h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16;
+ h2 = (int16_t)(v2 & 0xFFFF); v2 >>= 16;
h = (*func)(h1, h2);
- result |= ((unsigned64)((unsigned16)h) << i);
+ result |= ((uint64_t)((uint16_t)h) << i);
}
return result;
}
-static unsigned64
-qh_map_op(unsigned64 v1, signed16 h2, QH_FUNC func)
+static uint64_t
+qh_map_op(uint64_t v1, int16_t h2, QH_FUNC func)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i;
- signed16 h, h1;
+ int16_t h, h1;
for (i = 0; i < 64; i += 16)
{
- h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16;
+ h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16;
h = (*func)(h1, h2);
- result |= ((unsigned64)((unsigned16)h) << i);
+ result |= ((uint64_t)((uint16_t)h) << i);
}
return result;
}
@@ -333,51 +333,51 @@ qh_map_op(unsigned64 v1, signed16 h2, QH_FUNC func)
/* Vector operations for OB format. */
-static unsigned64
-ob_vector_op(unsigned64 v1, unsigned64 v2, OB_FUNC func)
+static uint64_t
+ob_vector_op(uint64_t v1, uint64_t v2, OB_FUNC func)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i;
- unsigned8 b, b1, b2;
+ uint8_t b, b1, b2;
for (i = 0; i < 64; i += 8)
{
b1 = v1 & 0xFF; v1 >>= 8;
b2 = v2 & 0xFF; v2 >>= 8;
b = (*func)(b1, b2);
- result |= ((unsigned64)b << i);
+ result |= ((uint64_t)b << i);
}
return result;
}
-static unsigned64
-ob_map_op(unsigned64 v1, unsigned8 b2, OB_FUNC func)
+static uint64_t
+ob_map_op(uint64_t v1, uint8_t b2, OB_FUNC func)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i;
- unsigned8 b, b1;
+ uint8_t b, b1;
for (i = 0; i < 64; i += 8)
{
b1 = v1 & 0xFF; v1 >>= 8;
b = (*func)(b1, b2);
- result |= ((unsigned64)b << i);
+ result |= ((uint64_t)b << i);
}
return result;
}
/* Primary entry for operations that update CPRs. */
-unsigned64
+uint64_t
mdmx_cpr_op(sim_cpu *cpu,
address_word cia,
int op,
- unsigned64 op1,
+ uint64_t op1,
int vt,
MX_fmtsel fmtsel)
{
- unsigned64 op2;
- unsigned64 result = 0;
+ uint64_t op2;
+ uint64_t result = 0;
switch (MX_FMT (fmtsel))
{
@@ -422,16 +422,16 @@ mdmx_cpr_op(sim_cpu *cpu,
/* Operations that update CCs */
static void
-qh_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond)
+qh_vector_test(sim_cpu *cpu, uint64_t v1, uint64_t v2, int cond)
{
int i;
- signed16 h1, h2;
+ int16_t h1, h2;
int boolean;
for (i = 0; i < 4; i++)
{
- h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16;
- h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16;
+ h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16;
+ h2 = (int16_t)(v2 & 0xFFFF); v2 >>= 16;
boolean = ((cond & MX_C_EQ) && (h1 == h2)) ||
((cond & MX_C_LT) && (h1 < h2));
SETFCC(i, boolean);
@@ -439,15 +439,15 @@ qh_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond)
}
static void
-qh_map_test(sim_cpu *cpu, unsigned64 v1, signed16 h2, int cond)
+qh_map_test(sim_cpu *cpu, uint64_t v1, int16_t h2, int cond)
{
int i;
- signed16 h1;
+ int16_t h1;
int boolean;
for (i = 0; i < 4; i++)
{
- h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16;
+ h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16;
boolean = ((cond & MX_C_EQ) && (h1 == h2)) ||
((cond & MX_C_LT) && (h1 < h2));
SETFCC(i, boolean);
@@ -455,10 +455,10 @@ qh_map_test(sim_cpu *cpu, unsigned64 v1, signed16 h2, int cond)
}
static void
-ob_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond)
+ob_vector_test(sim_cpu *cpu, uint64_t v1, uint64_t v2, int cond)
{
int i;
- unsigned8 b1, b2;
+ uint8_t b1, b2;
int boolean;
for (i = 0; i < 8; i++)
@@ -472,15 +472,15 @@ ob_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond)
}
static void
-ob_map_test(sim_cpu *cpu, unsigned64 v1, unsigned8 b2, int cond)
+ob_map_test(sim_cpu *cpu, uint64_t v1, uint8_t b2, int cond)
{
int i;
- unsigned8 b1;
+ uint8_t b1;
int boolean;
for (i = 0; i < 8; i++)
{
- b1 = (unsigned8)(v1 & 0xFF); v1 >>= 8;
+ b1 = (uint8_t)(v1 & 0xFF); v1 >>= 8;
boolean = ((cond & MX_C_EQ) && (b1 == b2)) ||
((cond & MX_C_LT) && (b1 < b2));
SETFCC(i, boolean);
@@ -492,11 +492,11 @@ void
mdmx_cc_op(sim_cpu *cpu,
address_word cia,
int cond,
- unsigned64 v1,
+ uint64_t v1,
int vt,
MX_fmtsel fmtsel)
{
- unsigned64 op2;
+ uint64_t op2;
switch (MX_FMT (fmtsel))
{
@@ -538,89 +538,89 @@ mdmx_cc_op(sim_cpu *cpu,
/* Pick operations. */
-static unsigned64
-qh_vector_pick(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int tf)
+static uint64_t
+qh_vector_pick(sim_cpu *cpu, uint64_t v1, uint64_t v2, int tf)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i, s;
- unsigned16 h;
+ uint16_t h;
s = 0;
for (i = 0; i < 4; i++)
{
h = ((GETFCC(i) == tf) ? (v1 & 0xFFFF) : (v2 & 0xFFFF));
v1 >>= 16; v2 >>= 16;
- result |= ((unsigned64)h << s);
+ result |= ((uint64_t)h << s);
s += 16;
}
return result;
}
-static unsigned64
-qh_map_pick(sim_cpu *cpu, unsigned64 v1, signed16 h2, int tf)
+static uint64_t
+qh_map_pick(sim_cpu *cpu, uint64_t v1, int16_t h2, int tf)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i, s;
- unsigned16 h;
+ uint16_t h;
s = 0;
for (i = 0; i < 4; i++)
{
- h = (GETFCC(i) == tf) ? (v1 & 0xFFFF) : (unsigned16)h2;
+ h = (GETFCC(i) == tf) ? (v1 & 0xFFFF) : (uint16_t)h2;
v1 >>= 16;
- result |= ((unsigned64)h << s);
+ result |= ((uint64_t)h << s);
s += 16;
}
return result;
}
-static unsigned64
-ob_vector_pick(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int tf)
+static uint64_t
+ob_vector_pick(sim_cpu *cpu, uint64_t v1, uint64_t v2, int tf)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i, s;
- unsigned8 b;
+ uint8_t b;
s = 0;
for (i = 0; i < 8; i++)
{
b = (GETFCC(i) == tf) ? (v1 & 0xFF) : (v2 & 0xFF);
v1 >>= 8; v2 >>= 8;
- result |= ((unsigned64)b << s);
+ result |= ((uint64_t)b << s);
s += 8;
}
return result;
}
-static unsigned64
-ob_map_pick(sim_cpu *cpu, unsigned64 v1, unsigned8 b2, int tf)
+static uint64_t
+ob_map_pick(sim_cpu *cpu, uint64_t v1, uint8_t b2, int tf)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i, s;
- unsigned8 b;
+ uint8_t b;
s = 0;
for (i = 0; i < 8; i++)
{
b = (GETFCC(i) == tf) ? (v1 & 0xFF) : b2;
v1 >>= 8;
- result |= ((unsigned64)b << s);
+ result |= ((uint64_t)b << s);
s += 8;
}
return result;
}
-unsigned64
+uint64_t
mdmx_pick_op(sim_cpu *cpu,
address_word cia,
int tf,
- unsigned64 v1,
+ uint64_t v1,
int vt,
MX_fmtsel fmtsel)
{
- unsigned64 result = 0;
- unsigned64 op2;
+ uint64_t result = 0;
+ uint64_t op2;
switch (MX_FMT (fmtsel))
{
@@ -663,111 +663,111 @@ mdmx_pick_op(sim_cpu *cpu,
/* Accumulators. */
-typedef void (*QH_ACC)(signed48 *a, signed16 ts, signed16 tt);
+typedef void (*QH_ACC)(signed48 *a, int16_t ts, int16_t tt);
static void
-AccAddAQH(signed48 *a, signed16 ts, signed16 tt)
+AccAddAQH(signed48 *a, int16_t ts, int16_t tt)
{
*a += (signed48)ts + (signed48)tt;
}
static void
-AccAddLQH(signed48 *a, signed16 ts, signed16 tt)
+AccAddLQH(signed48 *a, int16_t ts, int16_t tt)
{
*a = (signed48)ts + (signed48)tt;
}
static void
-AccMulAQH(signed48 *a, signed16 ts, signed16 tt)
+AccMulAQH(signed48 *a, int16_t ts, int16_t tt)
{
*a += (signed48)ts * (signed48)tt;
}
static void
-AccMulLQH(signed48 *a, signed16 ts, signed16 tt)
+AccMulLQH(signed48 *a, int16_t ts, int16_t tt)
{
*a = (signed48)ts * (signed48)tt;
}
static void
-SubMulAQH(signed48 *a, signed16 ts, signed16 tt)
+SubMulAQH(signed48 *a, int16_t ts, int16_t tt)
{
*a -= (signed48)ts * (signed48)tt;
}
static void
-SubMulLQH(signed48 *a, signed16 ts, signed16 tt)
+SubMulLQH(signed48 *a, int16_t ts, int16_t tt)
{
*a = -((signed48)ts * (signed48)tt);
}
static void
-AccSubAQH(signed48 *a, signed16 ts, signed16 tt)
+AccSubAQH(signed48 *a, int16_t ts, int16_t tt)
{
*a += (signed48)ts - (signed48)tt;
}
static void
-AccSubLQH(signed48 *a, signed16 ts, signed16 tt)
+AccSubLQH(signed48 *a, int16_t ts, int16_t tt)
{
*a = (signed48)ts - (signed48)tt;
}
-typedef void (*OB_ACC)(signed24 *acc, unsigned8 ts, unsigned8 tt);
+typedef void (*OB_ACC)(signed24 *acc, uint8_t ts, uint8_t tt);
static void
-AccAddAOB(signed24 *a, unsigned8 ts, unsigned8 tt)
+AccAddAOB(signed24 *a, uint8_t ts, uint8_t tt)
{
*a += (signed24)ts + (signed24)tt;
}
static void
-AccAddLOB(signed24 *a, unsigned8 ts, unsigned8 tt)
+AccAddLOB(signed24 *a, uint8_t ts, uint8_t tt)
{
*a = (signed24)ts + (signed24)tt;
}
static void
-AccMulAOB(signed24 *a, unsigned8 ts, unsigned8 tt)
+AccMulAOB(signed24 *a, uint8_t ts, uint8_t tt)
{
*a += (signed24)ts * (signed24)tt;
}
static void
-AccMulLOB(signed24 *a, unsigned8 ts, unsigned8 tt)
+AccMulLOB(signed24 *a, uint8_t ts, uint8_t tt)
{
*a = (signed24)ts * (signed24)tt;
}
static void
-SubMulAOB(signed24 *a, unsigned8 ts, unsigned8 tt)
+SubMulAOB(signed24 *a, uint8_t ts, uint8_t tt)
{
*a -= (signed24)ts * (signed24)tt;
}
static void
-SubMulLOB(signed24 *a, unsigned8 ts, unsigned8 tt)
+SubMulLOB(signed24 *a, uint8_t ts, uint8_t tt)
{
*a = -((signed24)ts * (signed24)tt);
}
static void
-AccSubAOB(signed24 *a, unsigned8 ts, unsigned8 tt)
+AccSubAOB(signed24 *a, uint8_t ts, uint8_t tt)
{
*a += (signed24)ts - (signed24)tt;
}
static void
-AccSubLOB(signed24 *a, unsigned8 ts, unsigned8 tt)
+AccSubLOB(signed24 *a, uint8_t ts, uint8_t tt)
{
*a = (signed24)ts - (signed24)tt;
}
static void
-AccAbsDiffOB(signed24 *a, unsigned8 ts, unsigned8 tt)
+AccAbsDiffOB(signed24 *a, uint8_t ts, uint8_t tt)
{
- unsigned8 t = (ts >= tt ? ts - tt : tt - ts);
+ uint8_t t = (ts >= tt ? ts - tt : tt - ts);
*a += (signed24)t;
}
@@ -788,37 +788,37 @@ static const OB_ACC ob_acc[] = {
static void
-qh_vector_acc(signed48 a[], unsigned64 v1, unsigned64 v2, QH_ACC acc)
+qh_vector_acc(signed48 a[], uint64_t v1, uint64_t v2, QH_ACC acc)
{
int i;
- signed16 h1, h2;
+ int16_t h1, h2;
for (i = 0; i < 4; i++)
{
- h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16;
- h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16;
+ h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16;
+ h2 = (int16_t)(v2 & 0xFFFF); v2 >>= 16;
(*acc)(&a[i], h1, h2);
}
}
static void
-qh_map_acc(signed48 a[], unsigned64 v1, signed16 h2, QH_ACC acc)
+qh_map_acc(signed48 a[], uint64_t v1, int16_t h2, QH_ACC acc)
{
int i;
- signed16 h1;
+ int16_t h1;
for (i = 0; i < 4; i++)
{
- h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16;
+ h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16;
(*acc)(&a[i], h1, h2);
}
}
static void
-ob_vector_acc(signed24 a[], unsigned64 v1, unsigned64 v2, OB_ACC acc)
+ob_vector_acc(signed24 a[], uint64_t v1, uint64_t v2, OB_ACC acc)
{
int i;
- unsigned8 b1, b2;
+ uint8_t b1, b2;
for (i = 0; i < 8; i++)
{
@@ -829,10 +829,10 @@ ob_vector_acc(signed24 a[], unsigned64 v1, unsigned64 v2, OB_ACC acc)
}
static void
-ob_map_acc(signed24 a[], unsigned64 v1, unsigned8 b2, OB_ACC acc)
+ob_map_acc(signed24 a[], uint64_t v1, uint8_t b2, OB_ACC acc)
{
int i;
- unsigned8 b1;
+ uint8_t b1;
for (i = 0; i < 8; i++)
{
@@ -847,11 +847,11 @@ void
mdmx_acc_op(sim_cpu *cpu,
address_word cia,
int op,
- unsigned64 op1,
+ uint64_t op1,
int vt,
MX_fmtsel fmtsel)
{
- unsigned64 op2;
+ uint64_t op2;
switch (MX_FMT (fmtsel))
{
@@ -893,13 +893,13 @@ mdmx_acc_op(sim_cpu *cpu,
/* Reading and writing accumulator (no conversion). */
-unsigned64
+uint64_t
mdmx_rac_op(sim_cpu *cpu,
address_word cia,
int op,
int fmt)
{
- unsigned64 result;
+ uint64_t result;
unsigned int shift;
int i;
@@ -934,8 +934,8 @@ void
mdmx_wacl(sim_cpu *cpu,
address_word cia,
int fmt,
- unsigned64 vs,
- unsigned64 vt)
+ uint64_t vs,
+ uint64_t vt)
{
int i;
@@ -944,7 +944,7 @@ mdmx_wacl(sim_cpu *cpu,
case MX_FMT_QH:
for (i = 0; i < 4; i++)
{
- signed32 s = (signed16)(vs & 0xFFFF);
+ int32_t s = (int16_t)(vs & 0xFFFF);
ACC.qh[i] = ((signed48)s << 16) | (vt & 0xFFFF);
vs >>= 16; vt >>= 16;
}
@@ -952,7 +952,7 @@ mdmx_wacl(sim_cpu *cpu,
case MX_FMT_OB:
for (i = 0; i < 8; i++)
{
- signed16 s = (signed8)(vs & 0xFF);
+ int16_t s = (int8_t)(vs & 0xFF);
ACC.ob[i] = ((signed24)s << 8) | (vt & 0xFF);
vs >>= 8; vt >>= 8;
}
@@ -966,7 +966,7 @@ void
mdmx_wach(sim_cpu *cpu,
address_word cia,
int fmt,
- unsigned64 vs)
+ uint64_t vs)
{
int i;
@@ -975,7 +975,7 @@ mdmx_wach(sim_cpu *cpu,
case MX_FMT_QH:
for (i = 0; i < 4; i++)
{
- signed32 s = (signed16)(vs & 0xFFFF);
+ int32_t s = (int16_t)(vs & 0xFFFF);
ACC.qh[i] &= ~((signed48)0xFFFF << 32);
ACC.qh[i] |= ((signed48)s << 32);
vs >>= 16;
@@ -998,16 +998,16 @@ mdmx_wach(sim_cpu *cpu,
/* Reading and writing accumulator (rounding conversions).
Enumerating function guarantees s >= 0 for QH ops. */
-typedef signed16 (*QH_ROUND)(signed48 a, signed16 s);
+typedef int16_t (*QH_ROUND)(signed48 a, int16_t s);
#define QH_BIT(n) ((unsigned48)1 << (n))
#define QH_ONES(n) (((unsigned48)1 << (n))-1)
-static signed16
-RNASQH(signed48 a, signed16 s)
+static int16_t
+RNASQH(signed48 a, int16_t s)
{
signed48 t;
- signed16 result = 0;
+ int16_t result = 0;
if (s > 48)
result = 0;
@@ -1031,16 +1031,16 @@ RNASQH(signed48 a, signed16 s)
if (t < QH_MIN)
t = QH_MIN;
}
- result = (signed16)t;
+ result = (int16_t)t;
}
return result;
}
-static signed16
-RNAUQH(signed48 a, signed16 s)
+static int16_t
+RNAUQH(signed48 a, int16_t s)
{
unsigned48 t;
- signed16 result;
+ int16_t result;
if (s > 48)
result = 0;
@@ -1053,16 +1053,16 @@ RNAUQH(signed48 a, signed16 s)
t++;
if (t > 0xFFFF)
t = 0xFFFF;
- result = (signed16)t;
+ result = (int16_t)t;
}
return result;
}
-static signed16
-RNESQH(signed48 a, signed16 s)
+static int16_t
+RNESQH(signed48 a, int16_t s)
{
signed48 t;
- signed16 result = 0;
+ int16_t result = 0;
if (s > 47)
result = 0;
@@ -1086,16 +1086,16 @@ RNESQH(signed48 a, signed16 s)
if (t < QH_MIN)
t = QH_MIN;
}
- result = (signed16)t;
+ result = (int16_t)t;
}
return result;
}
-static signed16
-RNEUQH(signed48 a, signed16 s)
+static int16_t
+RNEUQH(signed48 a, int16_t s)
{
unsigned48 t;
- signed16 result;
+ int16_t result;
if (s > 48)
result = 0;
@@ -1113,16 +1113,16 @@ RNEUQH(signed48 a, signed16 s)
}
if (t > 0xFFFF)
t = 0xFFFF;
- result = (signed16)t;
+ result = (int16_t)t;
}
return result;
}
-static signed16
-RZSQH(signed48 a, signed16 s)
+static int16_t
+RZSQH(signed48 a, int16_t s)
{
signed48 t;
- signed16 result = 0;
+ int16_t result = 0;
if (s > 47)
result = 0;
@@ -1139,16 +1139,16 @@ RZSQH(signed48 a, signed16 s)
if (t < QH_MIN)
t = QH_MIN;
}
- result = (signed16)t;
+ result = (int16_t)t;
}
return result;
}
-static signed16
-RZUQH(signed48 a, signed16 s)
+static int16_t
+RZUQH(signed48 a, int16_t s)
{
unsigned48 t;
- signed16 result = 0;
+ int16_t result = 0;
if (s > 48)
result = 0;
@@ -1159,21 +1159,21 @@ RZUQH(signed48 a, signed16 s)
t = ((unsigned48)a & MASK48) >> s;
if (t > 0xFFFF)
t = 0xFFFF;
- result = (signed16)t;
+ result = (int16_t)t;
}
return result;
}
-typedef unsigned8 (*OB_ROUND)(signed24 a, unsigned8 s);
+typedef uint8_t (*OB_ROUND)(signed24 a, uint8_t s);
#define OB_BIT(n) ((unsigned24)1 << (n))
#define OB_ONES(n) (((unsigned24)1 << (n))-1)
-static unsigned8
-RNAUOB(signed24 a, unsigned8 s)
+static uint8_t
+RNAUOB(signed24 a, uint8_t s)
{
- unsigned8 result;
+ uint8_t result;
unsigned24 t;
if (s > 24)
@@ -1190,10 +1190,10 @@ RNAUOB(signed24 a, unsigned8 s)
return result;
}
-static unsigned8
-RNEUOB(signed24 a, unsigned8 s)
+static uint8_t
+RNEUOB(signed24 a, uint8_t s)
{
- unsigned8 result;
+ uint8_t result;
unsigned24 t;
if (s > 24)
@@ -1215,10 +1215,10 @@ RNEUOB(signed24 a, unsigned8 s)
return result;
}
-static unsigned8
-RZUOB(signed24 a, unsigned8 s)
+static uint8_t
+RZUOB(signed24 a, uint8_t s)
{
- unsigned8 result;
+ uint8_t result;
unsigned24 t;
if (s >= 24)
@@ -1241,17 +1241,17 @@ static const OB_ROUND ob_round[] = {
};
-static unsigned64
-qh_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, QH_ROUND round)
+static uint64_t
+qh_vector_round(sim_cpu *cpu, address_word cia, uint64_t v2, QH_ROUND round)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i, s;
- signed16 h, h2;
+ int16_t h, h2;
s = 0;
for (i = 0; i < 4; i++)
{
- h2 = (signed16)(v2 & 0xFFFF);
+ h2 = (int16_t)(v2 & 0xFFFF);
if (h2 >= 0)
h = (*round)(ACC.qh[i], h2);
else
@@ -1260,18 +1260,18 @@ qh_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, QH_ROUND round)
h = 0xdead;
}
v2 >>= 16;
- result |= ((unsigned64)((unsigned16)h) << s);
+ result |= ((uint64_t)((uint16_t)h) << s);
s += 16;
}
return result;
}
-static unsigned64
-qh_map_round(sim_cpu *cpu, address_word cia, signed16 h2, QH_ROUND round)
+static uint64_t
+qh_map_round(sim_cpu *cpu, address_word cia, int16_t h2, QH_ROUND round)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i, s;
- signed16 h;
+ int16_t h;
s = 0;
for (i = 0; i < 4; i++)
@@ -1283,57 +1283,57 @@ qh_map_round(sim_cpu *cpu, address_word cia, signed16 h2, QH_ROUND round)
UnpredictableResult ();
h = 0xdead;
}
- result |= ((unsigned64)((unsigned16)h) << s);
+ result |= ((uint64_t)((uint16_t)h) << s);
s += 16;
}
return result;
}
-static unsigned64
-ob_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, OB_ROUND round)
+static uint64_t
+ob_vector_round(sim_cpu *cpu, address_word cia, uint64_t v2, OB_ROUND round)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i, s;
- unsigned8 b, b2;
+ uint8_t b, b2;
s = 0;
for (i = 0; i < 8; i++)
{
b2 = v2 & 0xFF; v2 >>= 8;
b = (*round)(ACC.ob[i], b2);
- result |= ((unsigned64)b << s);
+ result |= ((uint64_t)b << s);
s += 8;
}
return result;
}
-static unsigned64
-ob_map_round(sim_cpu *cpu, address_word cia, unsigned8 b2, OB_ROUND round)
+static uint64_t
+ob_map_round(sim_cpu *cpu, address_word cia, uint8_t b2, OB_ROUND round)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i, s;
- unsigned8 b;
+ uint8_t b;
s = 0;
for (i = 0; i < 8; i++)
{
b = (*round)(ACC.ob[i], b2);
- result |= ((unsigned64)b << s);
+ result |= ((uint64_t)b << s);
s += 8;
}
return result;
}
-unsigned64
+uint64_t
mdmx_round_op(sim_cpu *cpu,
address_word cia,
int rm,
int vt,
MX_fmtsel fmtsel)
{
- unsigned64 op2;
- unsigned64 result = 0;
+ uint64_t op2;
+ uint64_t result = 0;
switch (MX_FMT (fmtsel))
{
@@ -1409,14 +1409,14 @@ static const sh_map qh_shuffle[][4] = {
};
-unsigned64
+uint64_t
mdmx_shuffle(sim_cpu *cpu,
address_word cia,
int shop,
- unsigned64 op1,
- unsigned64 op2)
+ uint64_t op1,
+ uint64_t op2)
{
- unsigned64 result = 0;
+ uint64_t result = 0;
int i, s;
int op;
@@ -1426,7 +1426,7 @@ mdmx_shuffle(sim_cpu *cpu,
s = 0;
for (i = 0; i < 4; i++)
{
- unsigned64 v;
+ uint64_t v;
switch (qh_shuffle[op][i].source)
{
@@ -1450,7 +1450,7 @@ mdmx_shuffle(sim_cpu *cpu,
s = 0;
for (i = 0; i < 8; i++)
{
- unsigned8 b;
+ uint8_t b;
unsigned int ishift = 8*ob_shuffle[op][i].index;
switch (ob_shuffle[op][i].source)
@@ -1468,7 +1468,7 @@ mdmx_shuffle(sim_cpu *cpu,
Unpredictable ();
b = 0;
}
- result |= ((unsigned64)b << s);
+ result |= ((uint64_t)b << s);
s += 8;
}
}
diff --git a/sim/mips/mdmx.igen b/sim/mips/mdmx.igen
index fb9bef3bac1e..0fd870c09f56 100644
--- a/sim/mips/mdmx.igen
+++ b/sim/mips/mdmx.igen
@@ -188,7 +188,7 @@
*mdmx:
*sb1:
{
- unsigned64 result;
+ uint64_t result;
int s;
check_mdmx (SD_, instruction_0);
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
@@ -205,7 +205,7 @@
*mdmx:
*sb1:
{
- unsigned64 result;
+ uint64_t result;
int s;
check_mdmx (SD_, instruction_0);
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
diff --git a/sim/mips/micromips.igen b/sim/mips/micromips.igen
index b2ebe2fc7f97..acbff6f2db21 100644
--- a/sim/mips/micromips.igen
+++ b/sim/mips/micromips.igen
@@ -81,7 +81,7 @@
}
-:function:::unsigned32:compute_movep_src_reg:int reg
+:function:::uint32_t:compute_movep_src_reg:int reg
*micromips32:
*micromips64:
{
@@ -99,7 +99,7 @@
}
}
-:function:::unsigned32:compute_andi16_imm:int encoded_imm
+:function:::uint32_t:compute_andi16_imm:int encoded_imm
*micromips32:
*micromips64:
{
diff --git a/sim/mips/micromipsdsp.igen b/sim/mips/micromipsdsp.igen
index e00a3fc97ae8..a68d25007b83 100644
--- a/sim/mips/micromipsdsp.igen
+++ b/sim/mips/micromipsdsp.igen
@@ -169,7 +169,7 @@
"bposge32 <IMMEDIATE>"
*micromipsdsp:
{
- unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
+ uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
if (pos >= 32)
NIA = delayslot_micromips (SD_, NIA + (EXTEND12 (IMMEDIATE) << 1), NIA,
MICROMIPS_DELAYSLOT_SIZE_ANY);
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index a033fce9d042..c5db5c2304fa 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -161,7 +161,7 @@
Programmers Volume III, Revision 0.95, section 4.9. */
if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
== (ksu_user << status_KSU_shift))
- return (address_word)((signed32)base + (signed32)offset);
+ return (address_word)((int32_t)base + (int32_t)offset);
#endif
return base + offset;
}
@@ -263,7 +263,7 @@
// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
// to check for restrictions (2) and (3) above.
//
-:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
+:function:::int:check_mf_cycles:hilo_history *history, int64_t time, const char *new
{
if (history->mf.timestamp + 3 > time)
{
@@ -289,7 +289,7 @@
*vr4100:
*vr5000:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = check_mf_cycles (SD_, history, time, "MT");
history->mt.timestamp = time;
history->mt.cia = CIA;
@@ -300,7 +300,7 @@
*mipsIV:
*mipsV:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
|| check_mf_cycles (SD_, history, time, "MT"));
history->mt.timestamp = time;
@@ -317,7 +317,7 @@
*micromips32:
*micromips64:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
history->mt.timestamp = time;
history->mt.cia = CIA;
return 1;
@@ -345,7 +345,7 @@
*micromips32:
*micromips64:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = 1;
if (peer != NULL
&& peer->mt.timestamp > history->op.timestamp
@@ -383,7 +383,7 @@
*vr4100:
*vr5000:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
hi->op.timestamp = time;
@@ -397,7 +397,7 @@
*mipsIV:
*mipsV:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
|| (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP")));
@@ -418,7 +418,7 @@
*micromips64:
{
/* FIXME: could record the fact that a stall occured if we want */
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
@@ -440,7 +440,7 @@
*vr5000:
*r3900:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
hi->op.timestamp = time;
@@ -454,7 +454,7 @@
*mipsIV:
*mipsV:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
|| (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP")));
@@ -473,7 +473,7 @@
*micromips32:
*micromips64:
{
- signed64 time = sim_events_time (SD);
+ int64_t time = sim_events_time (SD);
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
@@ -538,7 +538,7 @@
TRACE_ALU_RESULT (GPR[rd]);
}
-:function:::void:do_addi:int rs, int rt, unsigned16 immediate
+:function:::void:do_addi:int rs, int rt, uint16_t immediate
{
if (NotWordValue (GPR[rs]))
Unpredictable ();
@@ -592,7 +592,7 @@
{
int s = 32 + shift;
TRACE_ALU_INPUT2 (GPR[rt], s);
- GPR[rd] = ((signed64) GPR[rt]) >> s;
+ GPR[rd] = ((int64_t) GPR[rt]) >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
@@ -600,7 +600,7 @@
{
int s = 32 + shift;
TRACE_ALU_INPUT2 (GPR[rt], s);
- GPR[rd] = (unsigned64) GPR[rt] >> s;
+ GPR[rd] = (uint64_t) GPR[rt] >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
@@ -655,12 +655,12 @@
:function:::void:do_clo:int rd, int rs
{
- unsigned32 temp = GPR[rs];
- unsigned32 i, mask;
+ uint32_t temp = GPR[rs];
+ uint32_t i, mask;
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[rs]);
- for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+ for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i)
{
if ((temp & mask) == 0)
break;
@@ -672,12 +672,12 @@
:function:::void:do_clz:int rd, int rs
{
- unsigned32 temp = GPR[rs];
- unsigned32 i, mask;
+ uint32_t temp = GPR[rs];
+ uint32_t i, mask;
if (NotWordValue (GPR[rs]))
Unpredictable ();
TRACE_ALU_INPUT1 (GPR[rs]);
- for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+ for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i)
{
if ((temp & mask) != 0)
break;
@@ -689,11 +689,11 @@
:function:::void:do_dclo:int rd, int rs
{
- unsigned64 temp = GPR[rs];
- unsigned32 i;
- unsigned64 mask;
+ uint64_t temp = GPR[rs];
+ uint32_t i;
+ uint64_t mask;
TRACE_ALU_INPUT1 (GPR[rs]);
- for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+ for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) == 0)
break;
@@ -705,11 +705,11 @@
:function:::void:do_dclz:int rd, int rs
{
- unsigned64 temp = GPR[rs];
- unsigned32 i;
- unsigned64 mask;
+ uint64_t temp = GPR[rs];
+ uint32_t i;
+ uint64_t mask;
TRACE_ALU_INPUT1 (GPR[rs]);
- for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+ for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) != 0)
break;
@@ -791,9 +791,9 @@
}
else
{
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ uint64_t memval = 0;
+ uint64_t memval1 = 0;
+ uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
unsigned int shift = 2;
unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
@@ -823,8 +823,8 @@
}
else
{
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
+ uint64_t memval = 0;
+ uint64_t memval1 = 0;
LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr,
isDATA, isREAL);
GPR[rt] = memval;
@@ -842,13 +842,13 @@
:function:::void:do_madd:int rs, int rt
{
- signed64 temp;
+ int64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
@@ -856,14 +856,14 @@
:function:::void:do_dsp_madd:int ac, int rs, int rt
{
- signed64 temp;
+ int64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
@@ -872,13 +872,13 @@
:function:::void:do_maddu:int rs, int rt
{
- unsigned64 temp;
+ uint64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
@@ -887,14 +887,14 @@
:function:::void:do_dsp_maddu:int ac, int rs, int rt
{
- unsigned64 temp;
+ uint64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
if (ac == 0)
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
DSPLO(ac) = EXTEND32 (temp);
@@ -939,13 +939,13 @@
:function:::void:do_msub:int rs, int rt
{
- signed64 temp;
+ int64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
@@ -953,14 +953,14 @@
:function:::void:do_dsp_msub:int ac, int rs, int rt
{
- signed64 temp;
+ int64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
@@ -969,13 +969,13 @@
:function:::void:do_msubu:int rs, int rt
{
- unsigned64 temp;
+ uint64_t temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
@@ -983,14 +983,14 @@
:function:::void:do_dsp_msubu:int ac, int rs, int rt
{
- unsigned64 temp;
+ uint64_t temp;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
- - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
DSPLO(ac) = EXTEND32 (temp);
DSPHI(ac) = EXTEND32 (VH4_8 (temp));
if (ac == 0)
@@ -1025,26 +1025,26 @@
:function:::void:do_mul:int rd, int rs, int rt
{
- signed64 prod;
+ int64_t prod;
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- prod = (((signed64)(signed32) GPR[rs])
- * ((signed64)(signed32) GPR[rt]));
+ prod = (((int64_t)(int32_t) GPR[rs])
+ * ((int64_t)(int32_t) GPR[rt]));
GPR[rd] = EXTEND32 (VL4_8 (prod));
TRACE_ALU_RESULT (GPR[rd]);
}
:function:::void:do_dsp_mult:int ac, int rs, int rt
{
- signed64 prod;
+ int64_t prod;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- prod = ((signed64)(signed32) GPR[rs])
- * ((signed64)(signed32) GPR[rt]);
+ prod = ((int64_t)(int32_t) GPR[rs])
+ * ((int64_t)(int32_t) GPR[rt]);
DSPLO(ac) = EXTEND32 (VL4_8 (prod));
DSPHI(ac) = EXTEND32 (VH4_8 (prod));
if (ac == 0)
@@ -1056,14 +1056,14 @@
:function:::void:do_dsp_multu:int ac, int rs, int rt
{
- unsigned64 prod;
+ uint64_t prod;
if (ac == 0)
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- prod = ((unsigned64)(unsigned32) GPR[rs])
- * ((unsigned64)(unsigned32) GPR[rt]);
+ prod = ((uint64_t)(uint32_t) GPR[rs])
+ * ((uint64_t)(uint32_t) GPR[rt]);
DSPLO(ac) = EXTEND32 (VL4_8 (prod));
DSPHI(ac) = EXTEND32 (VH4_8 (prod));
if (ac == 0)
@@ -1083,7 +1083,7 @@
:function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0
{
- unsigned32 instruction = instruction_0;
+ uint32_t instruction = instruction_0;
address_word base = GPR[basereg];
address_word offset = EXTEND16 (offsetarg);
{
@@ -1097,9 +1097,9 @@
}
else
{
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ uint64_t memval = 0;
+ uint64_t memval1 = 0;
+ uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian =
(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
address_word bigendiancpu =
@@ -1107,7 +1107,7 @@
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
- memval = ((unsigned64) GPR[rt] << (8 * byte));
+ memval = ((uint64_t) GPR[rt] << (8 * byte));
if (LLBIT)
StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
isREAL);
@@ -1131,8 +1131,8 @@
}
else
{
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
+ uint64_t memval = 0;
+ uint64_t memval1 = 0;
memval = GPR[rt];
if (LLBIT)
StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr,
@@ -1248,9 +1248,9 @@
:function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0
{
- unsigned64 fsx;
- unsigned64 ftx;
- unsigned64 fdx;
+ uint64_t fsx;
+ uint64_t ftx;
+ uint64_t fdx;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
fsx = ValueFPR (fs, fmt_ps);
@@ -1493,7 +1493,7 @@
}
else
{
- unsigned64 fdx;
+ uint64_t fdx;
fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd,
fmt_ps)),
PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd,
@@ -1730,9 +1730,9 @@
}
else
{
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ uint64_t memval = 0;
+ uint64_t memval1 = 0;
+ uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian =
(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
address_word bigendiancpu =
@@ -1740,7 +1740,7 @@
unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
- memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
+ memval = (((uint64_t)COP_SW(1,fs)) << (8 * byte));
StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
isREAL);
}
@@ -1794,7 +1794,7 @@
-:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
+:function:::void:do_addiu:int rs, int rt, uint16_t immediate
{
if (NotWordValue (GPR[rs]))
Unpredictable ();
@@ -2395,7 +2395,7 @@
-:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
+:function:::void:do_daddiu:int rs, int rt, uint16_t immediate
{
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = GPR[rs] + EXTEND16 (immediate);
@@ -2474,10 +2474,10 @@
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- signed64 n = GPR[rs];
- signed64 d = GPR[rt];
- signed64 hi;
- signed64 lo;
+ int64_t n = GPR[rs];
+ int64_t d = GPR[rt];
+ int64_t hi;
+ int64_t lo;
if (d == 0)
{
lo = SIGNED64 (0x8000000000000000);
@@ -2520,10 +2520,10 @@
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- unsigned64 n = GPR[rs];
- unsigned64 d = GPR[rt];
- unsigned64 hi;
- unsigned64 lo;
+ uint64_t n = GPR[rs];
+ uint64_t d = GPR[rt];
+ uint64_t hi;
+ uint64_t lo;
if (d == 0)
{
lo = SIGNED64 (0x8000000000000000);
@@ -2559,8 +2559,8 @@
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- signed32 n = GPR[rs];
- signed32 d = GPR[rt];
+ int32_t n = GPR[rs];
+ int32_t d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
@@ -2605,8 +2605,8 @@
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
{
- unsigned32 n = GPR[rs];
- unsigned32 d = GPR[rt];
+ uint32_t n = GPR[rs];
+ uint32_t d = GPR[rt];
if (d == 0)
{
LO = EXTEND32 (0x80000000);
@@ -2642,47 +2642,47 @@
:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
{
- unsigned64 lo;
- unsigned64 hi;
- unsigned64 m00;
- unsigned64 m01;
- unsigned64 m10;
- unsigned64 m11;
- unsigned64 mid;
+ uint64_t lo;
+ uint64_t hi;
+ uint64_t m00;
+ uint64_t m01;
+ uint64_t m10;
+ uint64_t m11;
+ uint64_t mid;
int sign;
- unsigned64 op1 = GPR[rs];
- unsigned64 op2 = GPR[rt];
+ uint64_t op1 = GPR[rs];
+ uint64_t op2 = GPR[rt];
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
/* make signed multiply unsigned */
sign = 0;
if (signed_p)
{
- if ((signed64) op1 < 0)
+ if ((int64_t) op1 < 0)
{
op1 = - op1;
++sign;
}
- if ((signed64) op2 < 0)
+ if ((int64_t) op2 < 0)
{
op2 = - op2;
++sign;
}
}
/* multiply out the 4 sub products */
- m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
- m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
- m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
- m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
+ m00 = ((uint64_t) VL4_8 (op1) * (uint64_t) VL4_8 (op2));
+ m10 = ((uint64_t) VH4_8 (op1) * (uint64_t) VL4_8 (op2));
+ m01 = ((uint64_t) VL4_8 (op1) * (uint64_t) VH4_8 (op2));
+ m11 = ((uint64_t) VH4_8 (op1) * (uint64_t) VH4_8 (op2));
/* add the products */
- mid = ((unsigned64) VH4_8 (m00)
- + (unsigned64) VL4_8 (m10)
- + (unsigned64) VL4_8 (m01));
+ mid = ((uint64_t) VH4_8 (m00)
+ + (uint64_t) VL4_8 (m10)
+ + (uint64_t) VL4_8 (m01));
lo = U8_4 (mid, m00);
hi = (m11
- + (unsigned64) VH4_8 (mid)
- + (unsigned64) VH4_8 (m01)
- + (unsigned64) VH4_8 (m10));
+ + (uint64_t) VH4_8 (mid)
+ + (uint64_t) VH4_8 (m01)
+ + (uint64_t) VH4_8 (m10));
/* fix the sign */
if (sign & 1)
{
@@ -2757,9 +2757,9 @@
}
-:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
+:function:::uint64_t:do_dror:uint64_t x,uint64_t y
{
- unsigned64 result;
+ uint64_t result;
y &= 63;
TRACE_ALU_INPUT2 (x, y);
@@ -2860,7 +2860,7 @@
:function:::void:do_dsra:int rt, int rd, int shift
{
TRACE_ALU_INPUT2 (GPR[rt], shift);
- GPR[rd] = ((signed64) GPR[rt]) >> shift;
+ GPR[rd] = ((int64_t) GPR[rt]) >> shift;
TRACE_ALU_RESULT (GPR[rd]);
}
@@ -2899,7 +2899,7 @@
{
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
- GPR[rd] = ((signed64) GPR[rt]) >> s;
+ GPR[rd] = ((int64_t) GPR[rt]) >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
@@ -2920,7 +2920,7 @@
:function:::void:do_dsrl:int rt, int rd, int shift
{
TRACE_ALU_INPUT2 (GPR[rt], shift);
- GPR[rd] = (unsigned64) GPR[rt] >> shift;
+ GPR[rd] = (uint64_t) GPR[rt] >> shift;
TRACE_ALU_RESULT (GPR[rd]);
}
@@ -2959,7 +2959,7 @@
{
int s = MASKED64 (GPR[rs], 5, 0);
TRACE_ALU_INPUT2 (GPR[rt], s);
- GPR[rd] = (unsigned64) GPR[rt] >> s;
+ GPR[rd] = (uint64_t) GPR[rt] >> s;
TRACE_ALU_RESULT (GPR[rd]);
}
@@ -3126,7 +3126,7 @@
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
@@ -3148,7 +3148,7 @@
unsigned int byte;
unsigned int word;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
int nr_lhs_bits;
int nr_rhs_bits;
@@ -3168,8 +3168,8 @@
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
- (long) ((unsigned64) vaddr >> 32), (long) vaddr,
- (long) ((unsigned64) paddr >> 32), (long) paddr,
+ (long) ((uint64_t) vaddr >> 32), (long) vaddr,
+ (long) ((uint64_t) paddr >> 32), (long) paddr,
word, byte, nr_lhs_bits, nr_rhs_bits); */
LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL);
@@ -3187,9 +3187,9 @@
rt = (rt & ~lhs_mask) | (temp & lhs_mask);
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
- (long) ((unsigned64) memval >> 32), (long) memval,
- (long) ((unsigned64) temp >> 32), (long) temp,
- (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
+ (long) ((uint64_t) memval >> 32), (long) memval,
+ (long) ((uint64_t) temp >> 32), (long) temp,
+ (long) ((uint64_t) lhs_mask >> 32), (long) lhs_mask,
(long) (rt >> 32), (long) rt); */
return rt;
}
@@ -3201,7 +3201,7 @@
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
@@ -3763,13 +3763,13 @@
:function:::void:do_mult:int rs, int rt, int rd
{
- signed64 prod;
+ int64_t prod;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- prod = (((signed64)(signed32) GPR[rs])
- * ((signed64)(signed32) GPR[rt]));
+ prod = (((int64_t)(int32_t) GPR[rs])
+ * ((int64_t)(int32_t) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
ACX = 0; /* SmartMIPS */
@@ -3816,13 +3816,13 @@
:function:::void:do_multu:int rs, int rt, int rd
{
- unsigned64 prod;
+ uint64_t prod;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
- prod = (((unsigned64)(unsigned32) GPR[rs])
- * ((unsigned64)(unsigned32) GPR[rt]));
+ prod = (((uint64_t)(uint32_t) GPR[rs])
+ * ((uint64_t)(uint32_t) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
if (rd != 0)
@@ -3959,9 +3959,9 @@
}
-:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
+:function:::uint64_t:do_ror:uint32_t x,uint32_t y
{
- unsigned64 result;
+ uint64_t result;
y &= 31;
TRACE_ALU_INPUT2 (x, y);
@@ -4000,7 +4000,7 @@
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
@@ -4022,7 +4022,7 @@
unsigned int byte;
unsigned int word;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
int nr_lhs_bits;
int nr_rhs_bits;
@@ -4039,8 +4039,8 @@
nr_rhs_bits = 8 * access - 8 * byte;
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
- (long) ((unsigned64) vaddr >> 32), (long) vaddr,
- (long) ((unsigned64) paddr >> 32), (long) paddr,
+ (long) ((uint64_t) vaddr >> 32), (long) vaddr,
+ (long) ((uint64_t) paddr >> 32), (long) paddr,
word, byte, nr_lhs_bits, nr_rhs_bits); */
if (word == 0)
@@ -4052,8 +4052,8 @@
memval = (rt << nr_lhs_bits);
}
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
- (long) ((unsigned64) rt >> 32), (long) rt,
- (long) ((unsigned64) memval >> 32), (long) memval); */
+ (long) ((uint64_t) rt >> 32), (long) rt,
+ (long) ((uint64_t) memval >> 32), (long) memval); */
StoreMemory (byte, memval, 0, paddr, vaddr, isREAL);
}
@@ -4064,7 +4064,7 @@
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
address_word vaddr;
paddr = vaddr = loadstore_ea (SD_, base, offset);
@@ -4212,7 +4212,7 @@
:function:::void:do_sll:int rt, int rd, int shift
{
- unsigned32 temp = (GPR[rt] << shift);
+ uint32_t temp = (GPR[rt] << shift);
TRACE_ALU_INPUT2 (GPR[rt], shift);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
@@ -4255,7 +4255,7 @@
:function:::void:do_sllv:int rs, int rt, int rd
{
int s = MASKED (GPR[rs], 4, 0);
- unsigned32 temp = (GPR[rt] << s);
+ uint32_t temp = (GPR[rt] << s);
TRACE_ALU_INPUT2 (GPR[rt], s);
GPR[rd] = EXTEND32 (temp);
TRACE_ALU_RESULT (GPR[rd]);
@@ -4306,7 +4306,7 @@
}
-:function:::void:do_slti:int rs, int rt, unsigned16 immediate
+:function:::void:do_slti:int rs, int rt, uint16_t immediate
{
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
@@ -4332,7 +4332,7 @@
}
-:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
+:function:::void:do_sltiu:int rs, int rt, uint16_t immediate
{
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
@@ -4387,7 +4387,7 @@
:function:::void:do_sra:int rt, int rd, int shift
{
- signed32 temp = (signed32) GPR[rt] >> shift;
+ int32_t temp = (int32_t) GPR[rt] >> shift;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], shift);
@@ -4418,7 +4418,7 @@
:function:::void:do_srav:int rs, int rt, int rd
{
int s = MASKED (GPR[rs], 4, 0);
- signed32 temp = (signed32) GPR[rt] >> s;
+ int32_t temp = (int32_t) GPR[rt] >> s;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], s);
@@ -4448,7 +4448,7 @@
:function:::void:do_srl:int rt, int rd, int shift
{
- unsigned32 temp = (unsigned32) GPR[rt] >> shift;
+ uint32_t temp = (uint32_t) GPR[rt] >> shift;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], shift);
@@ -4478,7 +4478,7 @@
:function:::void:do_srlv:int rs, int rt, int rd
{
int s = MASKED (GPR[rs], 4, 0);
- unsigned32 temp = (unsigned32) GPR[rt] >> s;
+ uint32_t temp = (uint32_t) GPR[rt] >> s;
if (NotWordValue (GPR[rt]))
Unpredictable ();
TRACE_ALU_INPUT2 (GPR[rt], s);
@@ -4896,7 +4896,7 @@
}
-:function:::void:do_xori:int rs, int rt, unsigned16 immediate
+:function:::void:do_xori:int rs, int rt, uint16_t immediate
{
TRACE_ALU_INPUT2 (GPR[rs], immediate);
GPR[rt] = GPR[rs] ^ immediate;
@@ -5060,7 +5060,7 @@
// unsigned_word, which is limited to the size of the machine's registers.
//
-:function:::unsigned64:do_load_double:address_word base, address_word offset
+:function:::uint64_t:do_load_double:address_word base, address_word offset
*mipsII:
*mips32:
*mips32r2:
@@ -5069,8 +5069,8 @@
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
address_word vaddr;
address_word paddr;
- unsigned64 memval;
- unsigned64 v;
+ uint64_t memval;
+ uint64_t v;
paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
@@ -5080,7 +5080,7 @@
sim_core_unaligned_signal);
}
LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL);
- v = (unsigned64)memval;
+ v = (uint64_t)memval;
LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA,
isREAL);
return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
@@ -5094,7 +5094,7 @@
// unsigned_word, which is limited to the size of the machine's registers.
//
-:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
+:function:::void:do_store_double:address_word base, address_word offset, uint64_t v
*mipsII:
*mips32:
*mips32r2:
@@ -5103,7 +5103,7 @@
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
address_word vaddr;
address_word paddr;
- unsigned64 memval;
+ uint64_t memval;
paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
@@ -5504,7 +5504,7 @@
"dmfc1 r<RT>, f<FS>"
*mipsIII:
{
- unsigned64 v;
+ uint64_t v;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
if (SizeFGR () == 64)
@@ -5537,7 +5537,7 @@
"dmtc1 r<RT>, f<FS>"
*mipsIII:
{
- unsigned64 v;
+ uint64_t v;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
if (SizeFGR () == 64)
@@ -5724,7 +5724,7 @@
*mipsII:
*mipsIII:
{
- unsigned64 v;
+ uint64_t v;
check_fpu (SD_);
v = EXTEND32 (FGR[FS]);
PENDING_FILL (RT, v);
diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen
index be0772bf8743..e0b838c4df23 100644
--- a/sim/mips/mips3264r2.igen
+++ b/sim/mips/mips3264r2.igen
@@ -21,7 +21,7 @@
:function:::void:do_dsbh:int rd, int rt
{
- union { unsigned64 d; unsigned16 h[4]; } u;
+ union { uint64_t d; uint16_t h[4]; } u;
TRACE_ALU_INPUT1 (GPR[rt]);
u.d = GPR[rt];
u.h[0] = SWAP_2 (u.h[0]);
@@ -34,7 +34,7 @@
:function:::void:do_dshd:int rd, int rt
{
- unsigned64 d;
+ uint64_t d;
TRACE_ALU_INPUT1 (GPR[rt]);
d = GPR[rt];
GPR[rd] = ((d >> 48)
@@ -181,7 +181,7 @@
:function:::void:do_wsbh:int rd, int rt
{
- union { unsigned32 w; unsigned16 h[2]; } u;
+ union { uint32_t w; uint16_t h[2]; } u;
TRACE_ALU_INPUT1 (GPR[rt]);
u.w = GPR[rt];
u.h[0] = SWAP_2 (u.h[0]);
diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c
index 876593b33f83..250310eceb37 100644
--- a/sim/mips/sim-main.c
+++ b/sim/mips/sim-main.c
@@ -254,7 +254,7 @@ store_memory (SIM_DESC SD,
}
-INLINE_SIM_MAIN (unsigned32)
+INLINE_SIM_MAIN (uint32_t)
ifetch32 (SIM_DESC SD,
sim_cpu *CPU,
address_word cia,
@@ -267,7 +267,7 @@ ifetch32 (SIM_DESC SD,
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr = vaddr;
- unsigned64 memval;
+ uint64_t memval;
if ((vaddr & access) != 0)
SignalExceptionInstructionFetch ();
@@ -278,7 +278,7 @@ ifetch32 (SIM_DESC SD,
}
-INLINE_SIM_MAIN (unsigned16)
+INLINE_SIM_MAIN (uint16_t)
ifetch16 (SIM_DESC SD,
sim_cpu *CPU,
address_word cia,
@@ -291,7 +291,7 @@ ifetch16 (SIM_DESC SD,
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr = vaddr;
- unsigned64 memval;
+ uint64_t memval;
if ((vaddr & access) != 0)
SignalExceptionInstructionFetch ();
@@ -433,18 +433,18 @@ pending_tick (SIM_DESC SD,
{
case 4:
if (PENDING_SLOT_VALUE[index])
- *(unsigned32*)PENDING_SLOT_DEST[index] |=
+ *(uint32_t*)PENDING_SLOT_DEST[index] |=
BIT32 (PENDING_SLOT_BIT[index]);
else
- *(unsigned32*)PENDING_SLOT_DEST[index] &=
+ *(uint32_t*)PENDING_SLOT_DEST[index] &=
BIT32 (PENDING_SLOT_BIT[index]);
break;
case 8:
if (PENDING_SLOT_VALUE[index])
- *(unsigned64*)PENDING_SLOT_DEST[index] |=
+ *(uint64_t*)PENDING_SLOT_DEST[index] |=
BIT64 (PENDING_SLOT_BIT[index]);
else
- *(unsigned64*)PENDING_SLOT_DEST[index] &=
+ *(uint64_t*)PENDING_SLOT_DEST[index] &=
BIT64 (PENDING_SLOT_BIT[index]);
break;
}
@@ -452,11 +452,11 @@ pending_tick (SIM_DESC SD,
switch (PENDING_SLOT_SIZE[index])
{
case 4:
- *(unsigned32*)PENDING_SLOT_DEST[index] =
+ *(uint32_t*)PENDING_SLOT_DEST[index] =
PENDING_SLOT_VALUE[index];
break;
case 8:
- *(unsigned64*)PENDING_SLOT_DEST[index] =
+ *(uint64_t*)PENDING_SLOT_DEST[index] =
PENDING_SLOT_VALUE[index];
break;
}
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index faba11668001..d724688a4348 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -33,8 +33,8 @@ mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ER
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
-typedef signed64 word64;
-typedef unsigned64 uword64;
+typedef int64_t word64;
+typedef uint64_t uword64;
#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
@@ -115,7 +115,7 @@ typedef enum {
more details. */
typedef struct _hilo_access {
- signed64 timestamp;
+ int64_t timestamp;
address_word cia;
} hilo_access;
@@ -135,7 +135,7 @@ typedef struct _hilo_history {
#define ALU32_END(ANS) \
if (ALU32_HAD_OVERFLOW) \
SignalExceptionIntegerOverflow (); \
- (ANS) = (signed32) ALU32_OVERFLOW_RESULT
+ (ANS) = (int32_t) ALU32_OVERFLOW_RESULT
#define ALU64_END(ANS) \
@@ -163,7 +163,7 @@ typedef struct _pending_write_queue {
int slot_size[PSLOTS];
int slot_bit[PSLOTS];
void *slot_dest[PSLOTS];
- unsigned64 slot_value[PSLOTS];
+ uint64_t slot_value[PSLOTS];
} pending_write_queue;
#ifndef PENDING_TRACE
@@ -243,8 +243,8 @@ enum float_operation
32 or 64 bits. Since the accumulators are 2's complement with
overflow suppressed, high-order bits can be ignored in most contexts. */
-typedef signed32 signed24;
-typedef signed64 signed48;
+typedef int32_t signed24;
+typedef int64_t signed48;
typedef union {
signed24 ob[8];
@@ -700,15 +700,15 @@ int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
/* FPR access. */
-unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
+uint64_t value_fpr (SIM_STATE, int fpr, FP_formats);
#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
-void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
+void store_fpr (SIM_STATE, int fpr, FP_formats fmt, uint64_t value);
#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
-unsigned64 ps_lower (SIM_STATE, unsigned64 op);
+uint64_t ps_lower (SIM_STATE, uint64_t op);
#define PSLower(op) ps_lower (SIM_ARGS, op)
-unsigned64 ps_upper (SIM_STATE, unsigned64 op);
+uint64_t ps_upper (SIM_STATE, uint64_t op);
#define PSUpper(op) ps_upper (SIM_ARGS, op)
-unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
+uint64_t pack_ps (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats from);
#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
@@ -722,41 +722,41 @@ void test_fcsr (SIM_STATE);
/* FPU operations. */
-void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
+void fp_cmp (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt, int abs, int cond, int cc);
#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
-unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
+uint64_t fp_abs (SIM_STATE, uint64_t op, FP_formats fmt);
#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
-unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
+uint64_t fp_neg (SIM_STATE, uint64_t op, FP_formats fmt);
#define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
-unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+uint64_t fp_add (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+uint64_t fp_sub (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+uint64_t fp_mul (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+uint64_t fp_div (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
+uint64_t fp_recip (SIM_STATE, uint64_t op, FP_formats fmt);
#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
-unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
+uint64_t fp_sqrt (SIM_STATE, uint64_t op, FP_formats fmt);
#define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
-unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
+uint64_t fp_rsqrt (SIM_STATE, uint64_t op, FP_formats fmt);
#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
-unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
- unsigned64 op3, FP_formats fmt);
+uint64_t fp_madd (SIM_STATE, uint64_t op1, uint64_t op2,
+ uint64_t op3, FP_formats fmt);
#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
-unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
- unsigned64 op3, FP_formats fmt);
+uint64_t fp_msub (SIM_STATE, uint64_t op1, uint64_t op2,
+ uint64_t op3, FP_formats fmt);
#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
-unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
- unsigned64 op3, FP_formats fmt);
+uint64_t fp_nmadd (SIM_STATE, uint64_t op1, uint64_t op2,
+ uint64_t op3, FP_formats fmt);
#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
-unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
- unsigned64 op3, FP_formats fmt);
+uint64_t fp_nmsub (SIM_STATE, uint64_t op1, uint64_t op2,
+ uint64_t op3, FP_formats fmt);
#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
-unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
+uint64_t convert (SIM_STATE, int rm, uint64_t op, FP_formats from, FP_formats to);
#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
-unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
+uint64_t convert_ps (SIM_STATE, int rm, uint64_t op, FP_formats from,
FP_formats to);
#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
@@ -764,17 +764,17 @@ unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
/* MIPS-3D ASE operations. */
#define CompareAbs(op1,op2,fmt,cond,cc) \
fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
-unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+uint64_t fp_add_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+uint64_t fp_mul_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
+uint64_t fp_recip1 (SIM_STATE, uint64_t op, FP_formats fmt);
#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
-unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+uint64_t fp_recip2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
+uint64_t fp_rsqrt1 (SIM_STATE, uint64_t op, FP_formats fmt);
#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
-unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
+uint64_t fp_rsqrt2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
@@ -802,7 +802,7 @@ typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
#define MX_VECT_ABSD (13) /* SB-1 only. */
#define MX_VECT_AVG (14) /* SB-1 only. */
-unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
+uint64_t mdmx_cpr_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel);
#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
#define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
#define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
@@ -822,10 +822,10 @@ unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmt
#define MX_C_EQ 0x1
#define MX_C_LT 0x4
-void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
+void mdmx_cc_op (SIM_STATE, int cond, uint64_t op1, int vt, MX_fmtsel fmtsel);
#define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
-unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
+uint64_t mdmx_pick_op (SIM_STATE, int tf, uint64_t op1, int vt, MX_fmtsel fmtsel);
#define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
#define MX_VECT_ADDA (0)
@@ -838,7 +838,7 @@ unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fm
#define MX_VECT_SUBL (7)
#define MX_VECT_ABSDA (8) /* SB-1 only. */
-void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
+void mdmx_acc_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel);
#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
#define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
#define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
@@ -857,12 +857,12 @@ void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
#define MX_RAC_M (1)
#define MX_RAC_H (2)
-unsigned64 mdmx_rac_op (SIM_STATE, int, int);
+uint64_t mdmx_rac_op (SIM_STATE, int, int);
#define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
-void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
+void mdmx_wacl (SIM_STATE, int, uint64_t, uint64_t);
#define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
-void mdmx_wach (SIM_STATE, int, unsigned64);
+void mdmx_wach (SIM_STATE, int, uint64_t);
#define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
#define MX_RND_AS (0)
@@ -872,7 +872,7 @@ void mdmx_wach (SIM_STATE, int, unsigned64);
#define MX_RND_ZS (4)
#define MX_RND_ZU (5)
-unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
+uint64_t mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
#define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
#define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
#define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
@@ -880,7 +880,7 @@ unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
#define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
#define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
-unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
+uint64_t mdmx_shuffle (SIM_STATE, int, uint64_t, uint64_t);
#define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
@@ -937,9 +937,9 @@ void unpredictable_action (sim_cpu *cpu, address_word cia);
#define Unpredictable() unpredictable (SD_)
#define UnpredictableResult() /* For now, do nothing. */
-INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
+INLINE_SIM_MAIN (uint32_t) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
-INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
+INLINE_SIM_MAIN (uint16_t) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
#define IMEM32_MICROMIPS(CIA) \
diff --git a/sim/mips/smartmips.igen b/sim/mips/smartmips.igen
index 947568e0331d..ef9bf81aaebf 100644
--- a/sim/mips/smartmips.igen
+++ b/sim/mips/smartmips.igen
@@ -31,8 +31,8 @@
"maddp r<RS>, r<RT>"
*smartmips:
{
- unsigned64 res;
- unsigned64 rs, rt;
+ uint64_t res;
+ uint64_t rs, rt;
int i;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -83,8 +83,8 @@
"multp r<RS>, r<RT>"
*smartmips:
{
- unsigned64 res;
- unsigned64 rs, rt;
+ uint64_t res;
+ uint64_t rs, rt;
int i;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
diff --git a/sim/mips/tx.igen b/sim/mips/tx.igen
index c4cc524731df..2e84452ba103 100644
--- a/sim/mips/tx.igen
+++ b/sim/mips/tx.igen
@@ -8,9 +8,9 @@
"madd r<RD>, r<RS>, r<RT>"
*r3900
{
- signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- + ((signed64) EXTEND32 (GPR[RT])
- * (signed64) EXTEND32 (GPR[RS])));
+ int64_t prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ + ((int64_t) EXTEND32 (GPR[RT])
+ * (int64_t) EXTEND32 (GPR[RS])));
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
LO = EXTEND32 (prod);
@@ -26,9 +26,9 @@
"maddu r<RD>, r<RS>, r<RT>"
*r3900
{
- unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- + ((unsigned64) VL4_8 (GPR[RS])
- * (unsigned64) VL4_8 (GPR[RT])));
+ uint64_t prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ + ((uint64_t) VL4_8 (GPR[RS])
+ * (uint64_t) VL4_8 (GPR[RT])));
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
LO = EXTEND32 (prod);
diff --git a/sim/mips/vr.igen b/sim/mips/vr.igen
index 9266ae6dc613..1d87da225353 100644
--- a/sim/mips/vr.igen
+++ b/sim/mips/vr.igen
@@ -40,7 +40,7 @@
// concatenation of the low 32 bits of HI and LO.
:function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p
{
- unsigned64 lhs, x, y, xcut, ycut, product, result;
+ uint64_t lhs, x, y, xcut, ycut, product, result;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -82,10 +82,10 @@
/* Saturate the result to 32 bits. An unsigned, unsaturated
result is zero-extended to 64 bits, but unsigned overflow
causes all 64 bits to be set. */
- if (!unsigned_p && (unsigned64) EXTEND32 (result) != result)
- result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff);
+ if (!unsigned_p && (uint64_t) EXTEND32 (result) != result)
+ result = ((int64_t) result < 0 ? -0x7fffffff - 1 : 0x7fffffff);
else if (unsigned_p && (result >> 32) != 0)
- result = (unsigned64) 0 - 1;
+ result = (uint64_t) 0 - 1;
}
TRACE_ALU_RESULT (result);
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 15/17] sim: igen: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (12 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 14/17] sim: mips: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 16/17] sim: common: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 17/17] sim: ppc: " Mike Frysinger
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
Move off the custom local 64-bit types and to the standard uintXX_t
types that C11 provides.
---
sim/igen/gen-idecode.c | 4 ++--
sim/igen/igen.c | 2 +-
sim/igen/ld-decode.c | 2 +-
sim/igen/ld-insn.c | 2 +-
sim/igen/ld-insn.h | 2 +-
sim/igen/misc.h | 24 +++---------------------
6 files changed, 9 insertions(+), 27 deletions(-)
diff --git a/sim/igen/gen-idecode.c b/sim/igen/gen-idecode.c
index 5e87e15b344d..d16cab54b29d 100644
--- a/sim/igen/gen-idecode.c
+++ b/sim/igen/gen-idecode.c
@@ -984,8 +984,8 @@ print_idecode_globals (lf *file)
lf_printf (file, "\n");
lf_printf (file, "typedef struct _idecode_table_entry {\n");
lf_printf (file, " int shift;\n");
- lf_printf (file, " unsigned%d mask;\n", options.insn_bit_size);
- lf_printf (file, " unsigned%d value;\n", options.insn_bit_size);
+ lf_printf (file, " uint%d_t mask;\n", options.insn_bit_size);
+ lf_printf (file, " uint%d_t value;\n", options.insn_bit_size);
lf_printf (file, " void *function_or_table;\n");
lf_printf (file, "} idecode_table_entry;\n");
}
diff --git a/sim/igen/igen.c b/sim/igen/igen.c
index 2389ccd711de..ba856401fa94 100644
--- a/sim/igen/igen.c
+++ b/sim/igen/igen.c
@@ -759,7 +759,7 @@ static void
gen_idecode_h (lf *file,
gen_table *gen, insn_table *insns, cache_entry *cache_rules)
{
- lf_printf (file, "typedef unsigned%d %sinstruction_word;\n",
+ lf_printf (file, "typedef uint%d_t %sinstruction_word;\n",
options.insn_bit_size, options.module.global.prefix.l);
if (options.gen.delayed_branch)
{
diff --git a/sim/igen/ld-decode.c b/sim/igen/ld-decode.c
index 3875bdb53c40..da0e9da93c34 100644
--- a/sim/igen/ld-decode.c
+++ b/sim/igen/ld-decode.c
@@ -70,7 +70,7 @@ static const name_map decode_search_map[] = {
static void
-set_bits (int bit[max_insn_bit_size], unsigned64 value)
+set_bits (int bit[max_insn_bit_size], uint64_t value)
{
int bit_nr;
for (bit_nr = 0; bit_nr < max_insn_bit_size; bit_nr++)
diff --git a/sim/igen/ld-insn.c b/sim/igen/ld-insn.c
index 6727d9f6cbd7..20c1f77b33fb 100644
--- a/sim/igen/ld-insn.c
+++ b/sim/igen/ld-insn.c
@@ -203,7 +203,7 @@ parse_insn_word (line_ref *line, char *string, int word_nr)
{
/* when the length/pos field is omited, an integer field
is always binary */
- unsigned64 val = 0;
+ uint64_t val = 0;
int i;
for (i = 0; i < strlen_val; i++)
{
diff --git a/sim/igen/ld-insn.h b/sim/igen/ld-insn.h
index dba2e63e6c2d..4859bae3b09e 100644
--- a/sim/igen/ld-insn.h
+++ b/sim/igen/ld-insn.h
@@ -21,7 +21,7 @@
-typedef unsigned64 insn_uint;
+typedef uint64_t insn_uint;
/* Common among most entries:
diff --git a/sim/igen/misc.h b/sim/igen/misc.h
index 48c21263c65f..a1cae768179f 100644
--- a/sim/igen/misc.h
+++ b/sim/igen/misc.h
@@ -30,29 +30,11 @@ enum
};
-/* Define a 64bit data type */
-
-#if defined __GNUC__ || defined _WIN32
-#ifdef __GNUC__
-
-typedef long long signed64;
-typedef unsigned long long unsigned64;
-
-#else /* _WIN32 */
-
-typedef __int64 signed64;
-typedef unsigned __int64 unsigned64;
-
-#endif /* _WIN32 */
-#else /* Not GNUC or WIN32 */
-/* Not supported */
-#endif
-
-
-#include <stdio.h>
#include <ctype.h>
-#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
#include <stdlib.h>
+#include <string.h>
#if !defined (__attribute__) && (!defined(__GNUC__) || __GNUC__ < 2 || (__GNUC__ == 2 && __GNUC_MINOR__ < 7))
#define __attribute__(arg)
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 16/17] sim: common: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (13 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 15/17] sim: igen: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
2022-01-01 20:55 ` [PATCH 17/17] sim: ppc: " Mike Frysinger
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
Drop the sim-specific unsignedXX types and move to the standard uintXX_t
types that C11 provides.
---
sim/common/cgen-accfp.c | 64 ++++++-------
sim/common/cgen-par.h | 2 +-
sim/common/cgen-trace.c | 6 +-
sim/common/cgen-types.h | 18 ++--
sim/common/dv-pal.c | 14 +--
sim/common/hw-events.c | 12 +--
sim/common/hw-events.h | 10 +-
sim/common/hw-properties.c | 2 +-
sim/common/hw-tree.c | 4 +-
sim/common/sim-alu.h | 192 ++++++++++++++++++-------------------
sim/common/sim-bits.h | 128 ++++++++++++-------------
sim/common/sim-core.c | 8 +-
sim/common/sim-events.c | 38 ++++----
sim/common/sim-events.h | 28 +++---
sim/common/sim-fpu.c | 156 +++++++++++++++---------------
sim/common/sim-fpu.h | 46 ++++-----
sim/common/sim-memopt.c | 8 +-
sim/common/sim-n-bits.h | 4 +-
sim/common/sim-profile.c | 4 +-
sim/common/sim-trace.c | 20 ++--
sim/common/sim-trace.h | 12 +--
sim/common/sim-types.h | 81 +++++++---------
22 files changed, 425 insertions(+), 432 deletions(-)
diff --git a/sim/common/cgen-accfp.c b/sim/common/cgen-accfp.c
index 345cfe81eb28..e19b09ba7f0a 100644
--- a/sim/common/cgen-accfp.c
+++ b/sim/common/cgen-accfp.c
@@ -25,7 +25,7 @@ addsf (CGEN_FPU* fpu, SF x, SF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -44,7 +44,7 @@ subsf (CGEN_FPU* fpu, SF x, SF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -63,7 +63,7 @@ mulsf (CGEN_FPU* fpu, SF x, SF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -82,7 +82,7 @@ divsf (CGEN_FPU* fpu, SF x, SF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -101,7 +101,7 @@ remsf (CGEN_FPU* fpu, SF x, SF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -119,7 +119,7 @@ negsf (CGEN_FPU* fpu, SF x)
{
sim_fpu op1;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -136,7 +136,7 @@ abssf (CGEN_FPU* fpu, SF x)
{
sim_fpu op1;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -153,7 +153,7 @@ sqrtsf (CGEN_FPU* fpu, SF x)
{
sim_fpu op1;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -170,7 +170,7 @@ invsf (CGEN_FPU* fpu, SF x)
{
sim_fpu op1;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -188,7 +188,7 @@ minsf (CGEN_FPU* fpu, SF x, SF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -207,7 +207,7 @@ maxsf (CGEN_FPU* fpu, SF x, SF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
@@ -322,7 +322,7 @@ static DF
fextsfdf (CGEN_FPU* fpu, int how UNUSED, SF x)
{
sim_fpu op1;
- unsigned64 res;
+ uint64_t res;
sim_fpu_32to (&op1, x);
sim_fpu_to64 (&res, &op1);
@@ -334,7 +334,7 @@ static SF
ftruncdfsf (CGEN_FPU* fpu, int how UNUSED, DF x)
{
sim_fpu op1;
- unsigned32 res;
+ uint32_t res;
sim_fpu_64to (&op1, x);
sim_fpu_to32 (&res, &op1);
@@ -346,7 +346,7 @@ static SF
floatsisf (CGEN_FPU* fpu, int how UNUSED, SI x)
{
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_i32to (&ans, x, sim_fpu_round_near);
sim_fpu_to32 (&res, &ans);
@@ -357,7 +357,7 @@ static DF
floatsidf (CGEN_FPU* fpu, int how UNUSED, SI x)
{
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_i32to (&ans, x, sim_fpu_round_near);
sim_fpu_to64 (&res, &ans);
@@ -368,7 +368,7 @@ static DF
floatdidf (CGEN_FPU* fpu, int how UNUSED, DI x)
{
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_i64to (&ans, x, sim_fpu_round_near);
sim_fpu_to64 (&res, &ans);
@@ -379,7 +379,7 @@ static SF
ufloatsisf (CGEN_FPU* fpu, int how UNUSED, USI x)
{
sim_fpu ans;
- unsigned32 res;
+ uint32_t res;
sim_fpu_u32to (&ans, x, sim_fpu_round_near);
sim_fpu_to32 (&res, &ans);
@@ -390,7 +390,7 @@ static SI
fixsfsi (CGEN_FPU* fpu, int how UNUSED, SF x)
{
sim_fpu op1;
- signed32 res;
+ int32_t res;
sim_fpu_32to (&op1, x);
sim_fpu_to32i (&res, &op1, sim_fpu_round_near);
@@ -401,7 +401,7 @@ static SI
fixdfsi (CGEN_FPU* fpu, int how UNUSED, DF x)
{
sim_fpu op1;
- signed32 res;
+ int32_t res;
sim_fpu_64to (&op1, x);
sim_fpu_to32i (&res, &op1, sim_fpu_round_near);
@@ -412,7 +412,7 @@ static DI
fixdfdi (CGEN_FPU* fpu, int how UNUSED, DF x)
{
sim_fpu op1;
- signed64 res;
+ int64_t res;
sim_fpu_64to (&op1, x);
sim_fpu_to64i (&res, &op1, sim_fpu_round_near);
@@ -423,7 +423,7 @@ static USI
ufixsfsi (CGEN_FPU* fpu, int how UNUSED, SF x)
{
sim_fpu op1;
- unsigned32 res;
+ uint32_t res;
sim_fpu_32to (&op1, x);
sim_fpu_to32u (&res, &op1, sim_fpu_round_near);
@@ -438,7 +438,7 @@ adddf (CGEN_FPU* fpu, DF x, DF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
@@ -457,7 +457,7 @@ subdf (CGEN_FPU* fpu, DF x, DF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
@@ -476,7 +476,7 @@ muldf (CGEN_FPU* fpu, DF x, DF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
@@ -495,7 +495,7 @@ divdf (CGEN_FPU* fpu, DF x, DF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
@@ -514,7 +514,7 @@ remdf (CGEN_FPU* fpu, DF x, DF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
@@ -532,7 +532,7 @@ negdf (CGEN_FPU* fpu, DF x)
{
sim_fpu op1;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
@@ -549,7 +549,7 @@ absdf (CGEN_FPU* fpu, DF x)
{
sim_fpu op1;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
@@ -566,7 +566,7 @@ sqrtdf (CGEN_FPU* fpu, DF x)
{
sim_fpu op1;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
@@ -583,7 +583,7 @@ invdf (CGEN_FPU* fpu, DF x)
{
sim_fpu op1;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
@@ -601,7 +601,7 @@ mindf (CGEN_FPU* fpu, DF x, DF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
@@ -620,7 +620,7 @@ maxdf (CGEN_FPU* fpu, DF x, DF y)
sim_fpu op1;
sim_fpu op2;
sim_fpu ans;
- unsigned64 res;
+ uint64_t res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
diff --git a/sim/common/cgen-par.h b/sim/common/cgen-par.h
index c06dcd53177e..46364b68a295 100644
--- a/sim/common/cgen-par.h
+++ b/sim/common/cgen-par.h
@@ -38,7 +38,7 @@ enum cgen_write_queue_kind {
typedef struct {
enum cgen_write_queue_kind kind; /* Used to select union member below. */
IADDR insn_address; /* Address of the insn performing the write. */
- unsigned32 flags; /* Target specific flags. */
+ uint32_t flags; /* Target specific flags. */
long word1; /* Target specific field. */
union {
struct {
diff --git a/sim/common/cgen-trace.c b/sim/common/cgen-trace.c
index 4fa1cda01b1e..149ea8a127cd 100644
--- a/sim/common/cgen-trace.c
+++ b/sim/common/cgen-trace.c
@@ -370,9 +370,9 @@ sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
struct disassemble_info disasm_info;
SFILE sfile;
union {
- unsigned8 bytes[CGEN_MAX_INSN_SIZE];
- unsigned16 shorts[8];
- unsigned32 words[4];
+ uint8_t bytes[CGEN_MAX_INSN_SIZE];
+ uint16_t shorts[8];
+ uint32_t words[4];
} insn_buf;
SIM_DESC sd = CPU_STATE (cpu);
CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu);
diff --git a/sim/common/cgen-types.h b/sim/common/cgen-types.h
index 414f5bb8ea44..e767c68b472b 100644
--- a/sim/common/cgen-types.h
+++ b/sim/common/cgen-types.h
@@ -61,15 +61,15 @@ extern const char * const cgen_mode_names[];
#undef VOID
typedef void VOID;
typedef unsigned char BI;
-typedef signed8 QI;
-typedef signed16 HI;
-typedef signed32 SI;
-typedef unsigned8 UQI;
-typedef unsigned16 UHI;
-typedef unsigned32 USI;
-
-typedef signed64 DI;
-typedef unsigned64 UDI;
+typedef int8_t QI;
+typedef int16_t HI;
+typedef int32_t SI;
+typedef uint8_t UQI;
+typedef uint16_t UHI;
+typedef uint32_t USI;
+
+typedef int64_t DI;
+typedef uint64_t UDI;
#define GETLODI(di) ((SI) (di))
#define GETHIDI(di) ((SI) ((UDI) (di) >> 32))
#define SETLODI(di, val) ((di) = (((di) & 0xffffffff00000000LL) | (val)))
diff --git a/sim/common/dv-pal.c b/sim/common/dv-pal.c
index 9a33de6245e5..5f42fdab75b0 100644
--- a/sim/common/dv-pal.c
+++ b/sim/common/dv-pal.c
@@ -181,8 +181,8 @@ typedef struct _hw_pal_console_buffer {
typedef struct _hw_pal_counter {
struct hw_event *handler;
- signed64 start;
- unsigned32 delta;
+ int64_t start;
+ uint32_t delta;
int periodic_p;
} hw_pal_counter;
@@ -237,10 +237,10 @@ do_counter_read (struct hw *me,
hw_pal_device *pal,
const char *reg,
hw_pal_counter *counter,
- unsigned32 *word,
+ uint32_t *word,
unsigned nr_bytes)
{
- unsigned32 val;
+ uint32_t val;
if (nr_bytes != 4)
hw_abort (me, "%s - bad read size must be 4 bytes", reg);
val = counter->delta;
@@ -253,10 +253,10 @@ do_counter_value (struct hw *me,
hw_pal_device *pal,
const char *reg,
hw_pal_counter *counter,
- unsigned32 *word,
+ uint32_t *word,
unsigned nr_bytes)
{
- unsigned32 val;
+ uint32_t val;
if (nr_bytes != 4)
hw_abort (me, "%s - bad read size must be 4 bytes", reg);
if (counter->delta != 0)
@@ -273,7 +273,7 @@ do_counter_write (struct hw *me,
hw_pal_device *pal,
const char *reg,
hw_pal_counter *counter,
- const unsigned32 *word,
+ const uint32_t *word,
unsigned nr_bytes)
{
if (nr_bytes != 4)
diff --git a/sim/common/hw-events.c b/sim/common/hw-events.c
index 62eb1c7f50ac..9bde01650244 100644
--- a/sim/common/hw-events.c
+++ b/sim/common/hw-events.c
@@ -87,7 +87,7 @@ bounce_hw_event (SIM_DESC sd,
struct hw_event *
hw_event_queue_schedule (struct hw *me,
- signed64 delta_time,
+ int64_t delta_time,
hw_event_callback *callback,
void *data)
{
@@ -96,7 +96,7 @@ hw_event_queue_schedule (struct hw *me,
struct hw_event *
hw_event_queue_schedule_tracef (struct hw *me,
- signed64 delta_time,
+ int64_t delta_time,
hw_event_callback *callback,
void *data,
const char *fmt,
@@ -112,7 +112,7 @@ hw_event_queue_schedule_tracef (struct hw *me,
struct hw_event *
hw_event_queue_schedule_vtracef (struct hw *me,
- signed64 delta_time,
+ int64_t delta_time,
hw_event_callback *callback,
void *data,
const char *fmt,
@@ -160,17 +160,17 @@ hw_event_queue_deschedule (struct hw *me,
}
-signed64
+int64_t
hw_event_queue_time (struct hw *me)
{
return sim_events_time (hw_system (me));
}
/* Returns the time that remains before the event is raised. */
-signed64
+int64_t
hw_event_remain_time (struct hw *me, struct hw_event *event)
{
- signed64 t;
+ int64_t t;
t = sim_events_remain_time (hw_system (me), event->real);
return t;
diff --git a/sim/common/hw-events.h b/sim/common/hw-events.h
index 8cc520c13632..adb285f229ef 100644
--- a/sim/common/hw-events.h
+++ b/sim/common/hw-events.h
@@ -33,13 +33,13 @@ typedef void (hw_event_callback) (struct hw *me, void *data);
struct hw_event *hw_event_queue_schedule
(struct hw *me,
- signed64 delta_time,
+ int64_t delta_time,
hw_event_callback *handler,
void *data);
struct hw_event *hw_event_queue_schedule_tracef
(struct hw *me,
- signed64 delta_time,
+ int64_t delta_time,
hw_event_callback *handler,
void *data,
const char *fmt,
@@ -47,7 +47,7 @@ struct hw_event *hw_event_queue_schedule_tracef
struct hw_event *hw_event_queue_schedule_vtracef
(struct hw *me,
- signed64 delta_time,
+ int64_t delta_time,
hw_event_callback *handler,
void *data,
const char *fmt,
@@ -58,11 +58,11 @@ void hw_event_queue_deschedule
(struct hw *me,
struct hw_event *event_to_remove);
-signed64 hw_event_queue_time
+int64_t hw_event_queue_time
(struct hw *me);
/* Returns the time that remains before the event is raised. */
-signed64 hw_event_remain_time
+int64_t hw_event_remain_time
(struct hw *me, struct hw_event *event);
#endif
diff --git a/sim/common/hw-properties.c b/sim/common/hw-properties.c
index 295cf2a3e0ac..3d2b5cdda7aa 100644
--- a/sim/common/hw-properties.c
+++ b/sim/common/hw-properties.c
@@ -368,7 +368,7 @@ hw_add_boolean_property (struct hw *me,
const char *property,
int boolean)
{
- signed32 new_boolean = (boolean ? -1 : 0);
+ int32_t new_boolean = (boolean ? -1 : 0);
hw_add_property (me, property, boolean_property,
&new_boolean, sizeof (new_boolean),
&new_boolean, sizeof (new_boolean),
diff --git a/sim/common/hw-tree.c b/sim/common/hw-tree.c
index 2e6daddfd329..56319333d76f 100644
--- a/sim/common/hw-tree.c
+++ b/sim/common/hw-tree.c
@@ -881,7 +881,7 @@ hw_tree_vparse (struct hw *current,
#endif
case '[':
{
- unsigned8 words[1024];
+ uint8_t words[1024];
char *curr = spec.value + 1;
int nr_words = 0;
while (1)
@@ -1127,7 +1127,7 @@ print_properties (struct hw *me,
}
else
{
- unsigned8 *w = (unsigned8*)property->array;
+ uint8_t *w = (uint8_t*)property->array;
p->print (p->file, " [");
while ((char*)w - (char*)property->array < property->sizeof_array)
{
diff --git a/sim/common/sim-alu.h b/sim/common/sim-alu.h
index 0fe62f159a23..a55f64845dcd 100644
--- a/sim/common/sim-alu.h
+++ b/sim/common/sim-alu.h
@@ -431,12 +431,12 @@
overflow method 2 are used. */
#define ALU8_BEGIN(VAL) \
-unsigned alu8_cr = (unsigned8) (VAL); \
-signed alu8_vr = (signed8) (alu8_cr)
+unsigned alu8_cr = (uint8_t) (VAL); \
+signed alu8_vr = (int8_t) (alu8_cr)
#define ALU8_SET(VAL) \
-alu8_cr = (unsigned8) (VAL); \
-alu8_vr = (signed8) (alu8_cr)
+alu8_cr = (uint8_t) (VAL); \
+alu8_vr = (int8_t) (alu8_cr)
#define ALU8_SET_CARRY_BORROW(CARRY) \
do { \
@@ -449,9 +449,9 @@ do { \
#define ALU8_HAD_CARRY_BORROW (alu8_cr & LSBIT32(8))
#define ALU8_HAD_OVERFLOW (((alu8_vr >> 8) ^ alu8_vr) & LSBIT32 (8-1))
-#define ALU8_RESULT ((unsigned8) alu8_cr)
-#define ALU8_CARRY_BORROW_RESULT ((unsigned8) alu8_cr)
-#define ALU8_OVERFLOW_RESULT ((unsigned8) alu8_vr)
+#define ALU8_RESULT ((uint8_t) alu8_cr)
+#define ALU8_CARRY_BORROW_RESULT ((uint8_t) alu8_cr)
+#define ALU8_OVERFLOW_RESULT ((uint8_t) alu8_vr)
/* #define ALU8_END ????? - target dependant */
@@ -463,12 +463,12 @@ do { \
overflow method 2 are used. */
#define ALU16_BEGIN(VAL) \
-signed alu16_cr = (unsigned16) (VAL); \
-unsigned alu16_vr = (signed16) (alu16_cr)
+signed alu16_cr = (uint16_t) (VAL); \
+unsigned alu16_vr = (int16_t) (alu16_cr)
#define ALU16_SET(VAL) \
-alu16_cr = (unsigned16) (VAL); \
-alu16_vr = (signed16) (alu16_cr)
+alu16_cr = (uint16_t) (VAL); \
+alu16_vr = (int16_t) (alu16_cr)
#define ALU16_SET_CARRY_BORROW(CARRY) \
do { \
@@ -481,9 +481,9 @@ do { \
#define ALU16_HAD_CARRY_BORROW (alu16_cr & LSBIT32(16))
#define ALU16_HAD_OVERFLOW (((alu16_vr >> 16) ^ alu16_vr) & LSBIT32 (16-1))
-#define ALU16_RESULT ((unsigned16) alu16_cr)
-#define ALU16_CARRY_BORROW_RESULT ((unsigned16) alu16_cr)
-#define ALU16_OVERFLOW_RESULT ((unsigned16) alu16_vr)
+#define ALU16_RESULT ((uint16_t) alu16_cr)
+#define ALU16_CARRY_BORROW_RESULT ((uint16_t) alu16_cr)
+#define ALU16_OVERFLOW_RESULT ((uint16_t) alu16_vr)
/* #define ALU16_END ????? - target dependant */
@@ -495,7 +495,7 @@ do { \
method 4 and overflow method 4 are used. */
#define ALU32_BEGIN(VAL) \
-unsigned32 alu32_r = (VAL); \
+uint32_t alu32_r = (VAL); \
int alu32_c = 0; \
int alu32_v = 0
@@ -521,7 +521,7 @@ alu32_v = 0
arithmetic, it is still used. */
#define ALU64_BEGIN(VAL) \
-unsigned64 alu64_r = (VAL); \
+uint64_t alu64_r = (VAL); \
int alu64_c = 0; \
int alu64_v = 0
@@ -560,25 +560,25 @@ alu64_v = 0
#define ALU8_ADD(VAL) \
do { \
- unsigned8 alu8add_val = (VAL); \
+ uint8_t alu8add_val = (VAL); \
ALU8_ADDC (alu8add_val); \
} while (0)
#define ALU16_ADD(VAL) \
do { \
- unsigned16 alu16add_val = (VAL); \
+ uint16_t alu16add_val = (VAL); \
ALU16_ADDC (alu8add_val); \
} while (0)
#define ALU32_ADD(VAL) \
do { \
- unsigned32 alu32add_val = (VAL); \
+ uint32_t alu32add_val = (VAL); \
ALU32_ADDC (alu32add_val); \
} while (0)
#define ALU64_ADD(VAL) \
do { \
- unsigned64 alu64add_val = (unsigned64) (VAL); \
+ uint64_t alu64add_val = (uint64_t) (VAL); \
ALU64_ADDC (alu64add_val); \
} while (0)
@@ -590,34 +590,34 @@ do { \
#define ALU8_ADDC(VAL) \
do { \
- unsigned8 alu8addc_val = (VAL); \
- alu8_cr += (unsigned8)(alu8addc_val); \
- alu8_vr += (signed8)(alu8addc_val); \
+ uint8_t alu8addc_val = (VAL); \
+ alu8_cr += (uint8_t)(alu8addc_val); \
+ alu8_vr += (int8_t)(alu8addc_val); \
} while (0)
#define ALU16_ADDC(VAL) \
do { \
- unsigned16 alu16addc_val = (VAL); \
- alu16_cr += (unsigned16)(alu16addc_val); \
- alu16_vr += (signed16)(alu16addc_val); \
+ uint16_t alu16addc_val = (VAL); \
+ alu16_cr += (uint16_t)(alu16addc_val); \
+ alu16_vr += (int16_t)(alu16addc_val); \
} while (0)
#define ALU32_ADDC(VAL) \
do { \
- unsigned32 alu32addc_val = (VAL); \
- unsigned32 alu32addc_sign = alu32addc_val ^ alu32_r; \
+ uint32_t alu32addc_val = (VAL); \
+ uint32_t alu32addc_sign = alu32addc_val ^ alu32_r; \
alu32_r += (alu32addc_val); \
alu32_c = (alu32_r < alu32addc_val); \
- alu32_v = ((alu32addc_sign ^ - (unsigned32)alu32_c) ^ alu32_r) >> 31; \
+ alu32_v = ((alu32addc_sign ^ - (uint32_t)alu32_c) ^ alu32_r) >> 31; \
} while (0)
#define ALU64_ADDC(VAL) \
do { \
- unsigned64 alu64addc_val = (unsigned64) (VAL); \
- unsigned64 alu64addc_sign = alu64addc_val ^ alu64_r; \
+ uint64_t alu64addc_val = (uint64_t) (VAL); \
+ uint64_t alu64addc_sign = alu64addc_val ^ alu64_r; \
alu64_r += (alu64addc_val); \
alu64_c = (alu64_r < alu64addc_val); \
- alu64_v = ((alu64addc_sign ^ - (unsigned64)alu64_c) ^ alu64_r) >> 63; \
+ alu64_v = ((alu64addc_sign ^ - (uint64_t)alu64_c) ^ alu64_r) >> 63; \
} while (0)
#define ALU_ADDC XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_ADDC)
@@ -628,40 +628,40 @@ do { \
#define ALU8_ADDC_C(VAL,C) \
do { \
- unsigned8 alu8addcc_val = (VAL); \
- unsigned8 alu8addcc_c = (C); \
- alu8_cr += (unsigned)(unsigned8)alu8addcc_val + alu8addcc_c; \
- alu8_vr += (signed)(signed8)(alu8addcc_val) + alu8addcc_c; \
+ uint8_t alu8addcc_val = (VAL); \
+ uint8_t alu8addcc_c = (C); \
+ alu8_cr += (unsigned)(uint8_t)alu8addcc_val + alu8addcc_c; \
+ alu8_vr += (signed)(int8_t)(alu8addcc_val) + alu8addcc_c; \
} while (0)
#define ALU16_ADDC_C(VAL,C) \
do { \
- unsigned16 alu16addcc_val = (VAL); \
- unsigned16 alu16addcc_c = (C); \
- alu16_cr += (unsigned)(unsigned16)alu16addcc_val + alu16addcc_c; \
- alu16_vr += (signed)(signed16)(alu16addcc_val) + alu16addcc_c; \
+ uint16_t alu16addcc_val = (VAL); \
+ uint16_t alu16addcc_c = (C); \
+ alu16_cr += (unsigned)(uint16_t)alu16addcc_val + alu16addcc_c; \
+ alu16_vr += (signed)(int16_t)(alu16addcc_val) + alu16addcc_c; \
} while (0)
#define ALU32_ADDC_C(VAL,C) \
do { \
- unsigned32 alu32addcc_val = (VAL); \
- unsigned32 alu32addcc_c = (C); \
- unsigned32 alu32addcc_sign = (alu32addcc_val ^ alu32_r); \
+ uint32_t alu32addcc_val = (VAL); \
+ uint32_t alu32addcc_c = (C); \
+ uint32_t alu32addcc_sign = (alu32addcc_val ^ alu32_r); \
alu32_r += (alu32addcc_val + alu32addcc_c); \
alu32_c = ((alu32_r < alu32addcc_val) \
|| (alu32addcc_c && alu32_r == alu32addcc_val)); \
- alu32_v = ((alu32addcc_sign ^ - (unsigned32)alu32_c) ^ alu32_r) >> 31;\
+ alu32_v = ((alu32addcc_sign ^ - (uint32_t)alu32_c) ^ alu32_r) >> 31;\
} while (0)
#define ALU64_ADDC_C(VAL,C) \
do { \
- unsigned64 alu64addcc_val = (VAL); \
- unsigned64 alu64addcc_c = (C); \
- unsigned64 alu64addcc_sign = (alu64addcc_val ^ alu64_r); \
+ uint64_t alu64addcc_val = (VAL); \
+ uint64_t alu64addcc_c = (C); \
+ uint64_t alu64addcc_sign = (alu64addcc_val ^ alu64_r); \
alu64_r += (alu64addcc_val + alu64addcc_c); \
alu64_c = ((alu64_r < alu64addcc_val) \
|| (alu64addcc_c && alu64_r == alu64addcc_val)); \
- alu64_v = ((alu64addcc_sign ^ - (unsigned64)alu64_c) ^ alu64_r) >> 63;\
+ alu64_v = ((alu64addcc_sign ^ - (uint64_t)alu64_c) ^ alu64_r) >> 63;\
} while (0)
#define ALU_ADDC_C XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_ADDC_C)
@@ -672,25 +672,25 @@ do { \
#define ALU8_SUB(VAL) \
do { \
- unsigned8 alu8sub_val = (VAL); \
+ uint8_t alu8sub_val = (VAL); \
ALU8_ADDC_C (~alu8sub_val, 1); \
} while (0)
#define ALU16_SUB(VAL) \
do { \
- unsigned16 alu16sub_val = (VAL); \
+ uint16_t alu16sub_val = (VAL); \
ALU16_ADDC_C (~alu16sub_val, 1); \
} while (0)
#define ALU32_SUB(VAL) \
do { \
- unsigned32 alu32sub_val = (VAL); \
+ uint32_t alu32sub_val = (VAL); \
ALU32_ADDC_C (~alu32sub_val, 1); \
} while (0)
#define ALU64_SUB(VAL) \
do { \
- unsigned64 alu64sub_val = (VAL); \
+ uint64_t alu64sub_val = (VAL); \
ALU64_ADDC_C (~alu64sub_val, 1); \
} while (0)
@@ -702,25 +702,25 @@ do { \
#define ALU8_SUBC(VAL) \
do { \
- unsigned8 alu8subc_val = (VAL); \
+ uint8_t alu8subc_val = (VAL); \
ALU8_ADDC_C (~alu8subc_val, 1); \
} while (0)
#define ALU16_SUBC(VAL) \
do { \
- unsigned16 alu16subc_val = (VAL); \
+ uint16_t alu16subc_val = (VAL); \
ALU16_ADDC_C (~alu16subc_val, 1); \
} while (0)
#define ALU32_SUBC(VAL) \
do { \
- unsigned32 alu32subc_val = (VAL); \
+ uint32_t alu32subc_val = (VAL); \
ALU32_ADDC_C (~alu32subc_val, 1); \
} while (0)
#define ALU64_SUBC(VAL) \
do { \
- unsigned64 alu64subc_val = (VAL); \
+ uint64_t alu64subc_val = (VAL); \
ALU64_ADDC_C (~alu64subc_val, 1); \
} while (0)
@@ -732,29 +732,29 @@ do { \
#define ALU8_SUBC_X(VAL,C) \
do { \
- unsigned8 alu8subcx_val = (VAL); \
- unsigned8 alu8subcx_c = (C); \
+ uint8_t alu8subcx_val = (VAL); \
+ uint8_t alu8subcx_c = (C); \
ALU8_ADDC_C (~alu8subcx_val, alu8subcx_c); \
} while (0)
#define ALU16_SUBC_X(VAL,C) \
do { \
- unsigned16 alu16subcx_val = (VAL); \
- unsigned16 alu16subcx_c = (C); \
+ uint16_t alu16subcx_val = (VAL); \
+ uint16_t alu16subcx_c = (C); \
ALU16_ADDC_C (~alu16subcx_val, alu16subcx_c); \
} while (0)
#define ALU32_SUBC_X(VAL,C) \
do { \
- unsigned32 alu32subcx_val = (VAL); \
- unsigned32 alu32subcx_c = (C); \
+ uint32_t alu32subcx_val = (VAL); \
+ uint32_t alu32subcx_c = (C); \
ALU32_ADDC_C (~alu32subcx_val, alu32subcx_c); \
} while (0)
#define ALU64_SUBC_X(VAL,C) \
do { \
- unsigned64 alu64subcx_val = (VAL); \
- unsigned64 alu64subcx_c = (C); \
+ uint64_t alu64subcx_val = (VAL); \
+ uint64_t alu64subcx_c = (C); \
ALU64_ADDC_C (~alu64subcx_val, alu64subcx_c); \
} while (0)
@@ -766,34 +766,34 @@ do { \
#define ALU8_SUBB(VAL) \
do { \
- unsigned8 alu8subb_val = (VAL); \
- alu8_cr -= (unsigned)(unsigned8)alu8subb_val; \
- alu8_vr -= (signed)(signed8)alu8subb_val; \
+ uint8_t alu8subb_val = (VAL); \
+ alu8_cr -= (unsigned)(uint8_t)alu8subb_val; \
+ alu8_vr -= (signed)(int8_t)alu8subb_val; \
} while (0)
#define ALU16_SUBB(VAL) \
do { \
- unsigned16 alu16subb_val = (VAL); \
- alu16_cr -= (unsigned)(unsigned16)alu16subb_val; \
- alu16_vr -= (signed)(signed16)alu16subb_val; \
+ uint16_t alu16subb_val = (VAL); \
+ alu16_cr -= (unsigned)(uint16_t)alu16subb_val; \
+ alu16_vr -= (signed)(int16_t)alu16subb_val; \
} while (0)
#define ALU32_SUBB(VAL) \
do { \
- unsigned32 alu32subb_val = (VAL); \
- unsigned32 alu32subb_sign = alu32subb_val ^ alu32_r; \
+ uint32_t alu32subb_val = (VAL); \
+ uint32_t alu32subb_sign = alu32subb_val ^ alu32_r; \
alu32_c = (alu32_r < alu32subb_val); \
alu32_r -= (alu32subb_val); \
- alu32_v = ((alu32subb_sign ^ - (unsigned32)alu32_c) ^ alu32_r) >> 31; \
+ alu32_v = ((alu32subb_sign ^ - (uint32_t)alu32_c) ^ alu32_r) >> 31; \
} while (0)
#define ALU64_SUBB(VAL) \
do { \
- unsigned64 alu64subb_val = (VAL); \
- unsigned64 alu64subb_sign = alu64subb_val ^ alu64_r; \
+ uint64_t alu64subb_val = (VAL); \
+ uint64_t alu64subb_sign = alu64subb_val ^ alu64_r; \
alu64_c = (alu64_r < alu64subb_val); \
alu64_r -= (alu64subb_val); \
- alu64_v = ((alu64subb_sign ^ - (unsigned64)alu64_c) ^ alu64_r) >> 31; \
+ alu64_v = ((alu64subb_sign ^ - (uint64_t)alu64_c) ^ alu64_r) >> 31; \
} while (0)
#define ALU_SUBB XCONCAT3(ALU,WITH_TARGET_WORD_BITSIZE,_SUBB)
@@ -804,34 +804,34 @@ do { \
#define ALU8_SUBB_B(VAL,B) \
do { \
- unsigned8 alu8subbb_val = (VAL); \
- unsigned8 alu8subbb_b = (B); \
- alu8_cr -= (unsigned)(unsigned8)alu8subbb_val; \
- alu8_cr -= (unsigned)(unsigned8)alu8subbb_b; \
- alu8_vr -= (signed)(signed8)alu8subbb_val + alu8subbb_b; \
+ uint8_t alu8subbb_val = (VAL); \
+ uint8_t alu8subbb_b = (B); \
+ alu8_cr -= (unsigned)(uint8_t)alu8subbb_val; \
+ alu8_cr -= (unsigned)(uint8_t)alu8subbb_b; \
+ alu8_vr -= (signed)(int8_t)alu8subbb_val + alu8subbb_b; \
} while (0)
#define ALU16_SUBB_B(VAL,B) \
do { \
- unsigned16 alu16subbb_val = (VAL); \
- unsigned16 alu16subbb_b = (B); \
- alu16_cr -= (unsigned)(unsigned16)alu16subbb_val; \
- alu16_cr -= (unsigned)(unsigned16)alu16subbb_b; \
- alu16_vr -= (signed)(signed16)alu16subbb_val + alu16subbb_b; \
+ uint16_t alu16subbb_val = (VAL); \
+ uint16_t alu16subbb_b = (B); \
+ alu16_cr -= (unsigned)(uint16_t)alu16subbb_val; \
+ alu16_cr -= (unsigned)(uint16_t)alu16subbb_b; \
+ alu16_vr -= (signed)(int16_t)alu16subbb_val + alu16subbb_b; \
} while (0)
#define ALU32_SUBB_B(VAL,B) \
do { \
- unsigned32 alu32subbb_val = (VAL); \
- unsigned32 alu32subbb_b = (B); \
+ uint32_t alu32subbb_val = (VAL); \
+ uint32_t alu32subbb_b = (B); \
ALU32_ADDC_C (~alu32subbb_val, !alu32subbb_b); \
alu32_c = !alu32_c; \
} while (0)
#define ALU64_SUBB_B(VAL,B) \
do { \
- unsigned64 alu64subbb_val = (VAL); \
- unsigned64 alu64subbb_b = (B); \
+ uint64_t alu64subbb_val = (VAL); \
+ uint64_t alu64subbb_b = (B); \
ALU64_ADDC_C (~alu64subbb_val, !alu64subbb_b); \
alu64_c = !alu64_c; \
} while (0)
@@ -858,14 +858,14 @@ do { \
#define ALU32_NEG() \
do { \
- unsigned32 alu32neg_val = (ALU32_RESULT); \
+ uint32_t alu32neg_val = (ALU32_RESULT); \
ALU32_SET (1); \
ALU32_ADDC (~alu32neg_val); \
} while(0)
#define ALU64_NEG() \
do { \
- unsigned64 alu64neg_val = (ALU64_RESULT); \
+ uint64_t alu64neg_val = (ALU64_RESULT); \
ALU64_SET (1); \
ALU64_ADDC (~alu64neg_val); \
} while (0)
@@ -893,14 +893,14 @@ do { \
#define ALU32_NEGC() \
do { \
- unsigned32 alu32negc_val = (ALU32_RESULT); \
+ uint32_t alu32negc_val = (ALU32_RESULT); \
ALU32_SET (1); \
ALU32_ADDC (~alu32negc_val); \
} while(0)
#define ALU64_NEGC() \
do { \
- unsigned64 alu64negc_val = (ALU64_RESULT); \
+ uint64_t alu64negc_val = (ALU64_RESULT); \
ALU64_SET (1); \
ALU64_ADDC (~alu64negc_val); \
} while (0)
@@ -928,14 +928,14 @@ do { \
#define ALU32_NEGB() \
do { \
- unsigned32 alu32negb_val = (ALU32_RESULT); \
+ uint32_t alu32negb_val = (ALU32_RESULT); \
ALU32_SET (0); \
ALU32_SUBB (alu32negb_val); \
} while(0)
#define ALU64_NEGB() \
do { \
- unsigned64 alu64negb_val = (ALU64_RESULT); \
+ uint64_t alu64negb_val = (ALU64_RESULT); \
ALU64_SET (0); \
ALU64_SUBB (alu64negb_val); \
} while (0)
diff --git a/sim/common/sim-bits.h b/sim/common/sim-bits.h
index c1aeafc3db1b..b1352d5a3053 100644
--- a/sim/common/sim-bits.h
+++ b/sim/common/sim-bits.h
@@ -206,41 +206,41 @@
/* LS/MS Bit operations */
-#define LSBIT8(POS) ((unsigned8) 1 << (POS))
-#define LSBIT16(POS) ((unsigned16)1 << (POS))
-#define LSBIT32(POS) ((unsigned32)1 << (POS))
-#define LSBIT64(POS) ((unsigned64)1 << (POS))
+#define LSBIT8(POS) ((uint8_t) 1 << (POS))
+#define LSBIT16(POS) ((uint16_t)1 << (POS))
+#define LSBIT32(POS) ((uint32_t)1 << (POS))
+#define LSBIT64(POS) ((uint64_t)1 << (POS))
#if (WITH_TARGET_WORD_BITSIZE == 64)
#define LSBIT(POS) LSBIT64 (POS)
#endif
#if (WITH_TARGET_WORD_BITSIZE == 32)
-#define LSBIT(POS) ((unsigned32)((POS) >= 32 \
+#define LSBIT(POS) ((uint32_t)((POS) >= 32 \
? 0 \
: (1 << ((POS) >= 32 ? 0 : (POS)))))
#endif
#if (WITH_TARGET_WORD_BITSIZE == 16)
-#define LSBIT(POS) ((unsigned16)((POS) >= 16 \
+#define LSBIT(POS) ((uint16_t)((POS) >= 16 \
? 0 \
: (1 << ((POS) >= 16 ? 0 : (POS)))))
#endif
-#define MSBIT8(POS) ((unsigned8) 1 << ( 8 - 1 - (POS)))
-#define MSBIT16(POS) ((unsigned16)1 << (16 - 1 - (POS)))
-#define MSBIT32(POS) ((unsigned32)1 << (32 - 1 - (POS)))
-#define MSBIT64(POS) ((unsigned64)1 << (64 - 1 - (POS)))
+#define MSBIT8(POS) ((uint8_t) 1 << ( 8 - 1 - (POS)))
+#define MSBIT16(POS) ((uint16_t)1 << (16 - 1 - (POS)))
+#define MSBIT32(POS) ((uint32_t)1 << (32 - 1 - (POS)))
+#define MSBIT64(POS) ((uint64_t)1 << (64 - 1 - (POS)))
#if (WITH_TARGET_WORD_BITSIZE == 64)
#define MSBIT(POS) MSBIT64 (POS)
#endif
#if (WITH_TARGET_WORD_BITSIZE == 32)
-#define MSBIT(POS) ((unsigned32)((POS) < 32 \
+#define MSBIT(POS) ((uint32_t)((POS) < 32 \
? 0 \
: (1 << ((POS) < 32 ? 0 : (64 - 1) - (POS)))))
#endif
#if (WITH_TARGET_WORD_BITSIZE == 16)
-#define MSBIT(POS) ((unsigned16)((POS) < 48 \
+#define MSBIT(POS) ((uint16_t)((POS) < 48 \
? 0 \
: (1 << ((POS) < 48 ? 0 : (64 - 1) - (POS)))))
#endif
@@ -271,7 +271,7 @@
/* multi bit mask */
/* 111111 -> mmll11 -> mm11ll */
-#define _MASKn(WIDTH, START, STOP) (((unsigned##WIDTH)(-1) \
+#define _MASKn(WIDTH, START, STOP) (((uint##WIDTH##_t)(-1) \
>> (_MSB_SHIFT (WIDTH, START) \
+ _LSB_SHIFT (WIDTH, STOP))) \
<< _LSB_SHIFT (WIDTH, STOP))
@@ -375,17 +375,17 @@
/* mask the required bits, leaving them in place */
-INLINE_SIM_BITS(unsigned8) LSMASKED8 (unsigned8 word, int first, int last);
-INLINE_SIM_BITS(unsigned16) LSMASKED16 (unsigned16 word, int first, int last);
-INLINE_SIM_BITS(unsigned32) LSMASKED32 (unsigned32 word, int first, int last);
-INLINE_SIM_BITS(unsigned64) LSMASKED64 (unsigned64 word, int first, int last);
+INLINE_SIM_BITS(uint8_t) LSMASKED8 (uint8_t word, int first, int last);
+INLINE_SIM_BITS(uint16_t) LSMASKED16 (uint16_t word, int first, int last);
+INLINE_SIM_BITS(uint32_t) LSMASKED32 (uint32_t word, int first, int last);
+INLINE_SIM_BITS(uint64_t) LSMASKED64 (uint64_t word, int first, int last);
INLINE_SIM_BITS(unsigned_word) LSMASKED (unsigned_word word, int first, int last);
-INLINE_SIM_BITS(unsigned8) MSMASKED8 (unsigned8 word, int first, int last);
-INLINE_SIM_BITS(unsigned16) MSMASKED16 (unsigned16 word, int first, int last);
-INLINE_SIM_BITS(unsigned32) MSMASKED32 (unsigned32 word, int first, int last);
-INLINE_SIM_BITS(unsigned64) MSMASKED64 (unsigned64 word, int first, int last);
+INLINE_SIM_BITS(uint8_t) MSMASKED8 (uint8_t word, int first, int last);
+INLINE_SIM_BITS(uint16_t) MSMASKED16 (uint16_t word, int first, int last);
+INLINE_SIM_BITS(uint32_t) MSMASKED32 (uint32_t word, int first, int last);
+INLINE_SIM_BITS(uint64_t) MSMASKED64 (uint64_t word, int first, int last);
INLINE_SIM_BITS(unsigned_word) MSMASKED (unsigned_word word, int first, int last);
@@ -407,17 +407,17 @@ INLINE_SIM_BITS(unsigned_word) MSMASKED (unsigned_word word, int first, int last
/* extract the required bits aligning them with the lsb */
-INLINE_SIM_BITS(unsigned8) LSEXTRACTED8 (unsigned8 val, int start, int stop);
-INLINE_SIM_BITS(unsigned16) LSEXTRACTED16 (unsigned16 val, int start, int stop);
-INLINE_SIM_BITS(unsigned32) LSEXTRACTED32 (unsigned32 val, int start, int stop);
-INLINE_SIM_BITS(unsigned64) LSEXTRACTED64 (unsigned64 val, int start, int stop);
+INLINE_SIM_BITS(uint8_t) LSEXTRACTED8 (uint8_t val, int start, int stop);
+INLINE_SIM_BITS(uint16_t) LSEXTRACTED16 (uint16_t val, int start, int stop);
+INLINE_SIM_BITS(uint32_t) LSEXTRACTED32 (uint32_t val, int start, int stop);
+INLINE_SIM_BITS(uint64_t) LSEXTRACTED64 (uint64_t val, int start, int stop);
INLINE_SIM_BITS(unsigned_word) LSEXTRACTED (unsigned_word val, int start, int stop);
-INLINE_SIM_BITS(unsigned8) MSEXTRACTED8 (unsigned8 val, int start, int stop);
-INLINE_SIM_BITS(unsigned16) MSEXTRACTED16 (unsigned16 val, int start, int stop);
-INLINE_SIM_BITS(unsigned32) MSEXTRACTED32 (unsigned32 val, int start, int stop);
-INLINE_SIM_BITS(unsigned64) MSEXTRACTED64 (unsigned64 val, int start, int stop);
+INLINE_SIM_BITS(uint8_t) MSEXTRACTED8 (uint8_t val, int start, int stop);
+INLINE_SIM_BITS(uint16_t) MSEXTRACTED16 (uint16_t val, int start, int stop);
+INLINE_SIM_BITS(uint32_t) MSEXTRACTED32 (uint32_t val, int start, int stop);
+INLINE_SIM_BITS(uint64_t) MSEXTRACTED64 (uint64_t val, int start, int stop);
INLINE_SIM_BITS(unsigned_word) MSEXTRACTED (unsigned_word val, int start, int stop);
@@ -441,10 +441,10 @@ INLINE_SIM_BITS(unsigned_word) MSEXTRACTED (unsigned_word val, int start, int st
/* NB: the wierdness (N>O?N-O:0) is to stop a warning from GCC */
#define _SHUFFLEDn(N, WORD, OLD, NEW) \
((OLD) < (NEW) \
- ? (((unsigned##N)(WORD) \
+ ? (((uint##N##_t)(WORD) \
>> (((NEW) > (OLD)) ? ((NEW) - (OLD)) : 0)) \
& MASK32((NEW), (NEW))) \
- : (((unsigned##N)(WORD) \
+ : (((uint##N##_t)(WORD) \
<< (((OLD) > (NEW)) ? ((OLD) - (NEW)) : 0)) \
& MASK32((NEW), (NEW))))
@@ -456,16 +456,16 @@ INLINE_SIM_BITS(unsigned_word) MSEXTRACTED (unsigned_word val, int start, int st
/* Insert a group of bits into a bit position */
-INLINE_SIM_BITS(unsigned8) LSINSERTED8 (unsigned8 val, int start, int stop);
-INLINE_SIM_BITS(unsigned16) LSINSERTED16 (unsigned16 val, int start, int stop);
-INLINE_SIM_BITS(unsigned32) LSINSERTED32 (unsigned32 val, int start, int stop);
-INLINE_SIM_BITS(unsigned64) LSINSERTED64 (unsigned64 val, int start, int stop);
+INLINE_SIM_BITS(uint8_t) LSINSERTED8 (uint8_t val, int start, int stop);
+INLINE_SIM_BITS(uint16_t) LSINSERTED16 (uint16_t val, int start, int stop);
+INLINE_SIM_BITS(uint32_t) LSINSERTED32 (uint32_t val, int start, int stop);
+INLINE_SIM_BITS(uint64_t) LSINSERTED64 (uint64_t val, int start, int stop);
INLINE_SIM_BITS(unsigned_word) LSINSERTED (unsigned_word val, int start, int stop);
-INLINE_SIM_BITS(unsigned8) MSINSERTED8 (unsigned8 val, int start, int stop);
-INLINE_SIM_BITS(unsigned16) MSINSERTED16 (unsigned16 val, int start, int stop);
-INLINE_SIM_BITS(unsigned32) MSINSERTED32 (unsigned32 val, int start, int stop);
-INLINE_SIM_BITS(unsigned64) MSINSERTED64 (unsigned64 val, int start, int stop);
+INLINE_SIM_BITS(uint8_t) MSINSERTED8 (uint8_t val, int start, int stop);
+INLINE_SIM_BITS(uint16_t) MSINSERTED16 (uint16_t val, int start, int stop);
+INLINE_SIM_BITS(uint32_t) MSINSERTED32 (uint32_t val, int start, int stop);
+INLINE_SIM_BITS(uint64_t) MSINSERTED64 (uint64_t val, int start, int stop);
INLINE_SIM_BITS(unsigned_word) MSINSERTED (unsigned_word val, int start, int stop);
#if (WITH_TARGET_WORD_MSB == 0)
@@ -499,19 +499,19 @@ INLINE_SIM_BITS(unsigned_word) MSINSERTED (unsigned_word val, int start, int sto
#define EXTEND4(X) (LSSEXT ((X), 3))
#define EXTEND5(X) (LSSEXT ((X), 4))
#define EXTEND6(X) (LSSEXT ((X), 5))
-#define EXTEND8(X) ((signed_word)(signed8)(X))
+#define EXTEND8(X) ((signed_word)(int8_t)(X))
#define EXTEND11(X) (LSSEXT ((X), 10))
#define EXTEND12(X) (LSSEXT ((X), 11))
#define EXTEND15(X) (LSSEXT ((X), 14))
-#define EXTEND16(X) ((signed_word)(signed16)(X))
+#define EXTEND16(X) ((signed_word)(int16_t)(X))
#define EXTEND24(X) (LSSEXT ((X), 23))
#define EXTEND25(X) (LSSEXT ((X), 24))
-#define EXTEND32(X) ((signed_word)(signed32)(X))
-#define EXTEND64(X) ((signed_word)(signed64)(X))
+#define EXTEND32(X) ((signed_word)(int32_t)(X))
+#define EXTEND64(X) ((signed_word)(int64_t)(X))
/* depending on MODE return a 64bit or 32bit (sign extended) value */
#if (WITH_TARGET_WORD_BITSIZE == 64)
-#define EXTENDED(X) ((signed64)(signed32)(X))
+#define EXTENDED(X) ((int64_t)(int32_t)(X))
#endif
#if (WITH_TARGET_WORD_BITSIZE == 32)
#define EXTENDED(X) (X)
@@ -546,37 +546,37 @@ do { \
intentionally omited. */
-INLINE_SIM_BITS(unsigned8) ROT8 (unsigned8 val, int shift);
-INLINE_SIM_BITS(unsigned16) ROT16 (unsigned16 val, int shift);
-INLINE_SIM_BITS(unsigned32) ROT32 (unsigned32 val, int shift);
-INLINE_SIM_BITS(unsigned64) ROT64 (unsigned64 val, int shift);
+INLINE_SIM_BITS(uint8_t) ROT8 (uint8_t val, int shift);
+INLINE_SIM_BITS(uint16_t) ROT16 (uint16_t val, int shift);
+INLINE_SIM_BITS(uint32_t) ROT32 (uint32_t val, int shift);
+INLINE_SIM_BITS(uint64_t) ROT64 (uint64_t val, int shift);
-INLINE_SIM_BITS(unsigned8) ROTL8 (unsigned8 val, int shift);
-INLINE_SIM_BITS(unsigned16) ROTL16 (unsigned16 val, int shift);
-INLINE_SIM_BITS(unsigned32) ROTL32 (unsigned32 val, int shift);
-INLINE_SIM_BITS(unsigned64) ROTL64 (unsigned64 val, int shift);
+INLINE_SIM_BITS(uint8_t) ROTL8 (uint8_t val, int shift);
+INLINE_SIM_BITS(uint16_t) ROTL16 (uint16_t val, int shift);
+INLINE_SIM_BITS(uint32_t) ROTL32 (uint32_t val, int shift);
+INLINE_SIM_BITS(uint64_t) ROTL64 (uint64_t val, int shift);
-INLINE_SIM_BITS(unsigned8) ROTR8 (unsigned8 val, int shift);
-INLINE_SIM_BITS(unsigned16) ROTR16 (unsigned16 val, int shift);
-INLINE_SIM_BITS(unsigned32) ROTR32 (unsigned32 val, int shift);
-INLINE_SIM_BITS(unsigned64) ROTR64 (unsigned64 val, int shift);
+INLINE_SIM_BITS(uint8_t) ROTR8 (uint8_t val, int shift);
+INLINE_SIM_BITS(uint16_t) ROTR16 (uint16_t val, int shift);
+INLINE_SIM_BITS(uint32_t) ROTR32 (uint32_t val, int shift);
+INLINE_SIM_BITS(uint64_t) ROTR64 (uint64_t val, int shift);
/* Sign extension operations */
-INLINE_SIM_BITS(unsigned8) LSSEXT8 (signed8 val, int sign_bit);
-INLINE_SIM_BITS(unsigned16) LSSEXT16 (signed16 val, int sign_bit);
-INLINE_SIM_BITS(unsigned32) LSSEXT32 (signed32 val, int sign_bit);
-INLINE_SIM_BITS(unsigned64) LSSEXT64 (signed64 val, int sign_bit);
+INLINE_SIM_BITS(uint8_t) LSSEXT8 (int8_t val, int sign_bit);
+INLINE_SIM_BITS(uint16_t) LSSEXT16 (int16_t val, int sign_bit);
+INLINE_SIM_BITS(uint32_t) LSSEXT32 (int32_t val, int sign_bit);
+INLINE_SIM_BITS(uint64_t) LSSEXT64 (int64_t val, int sign_bit);
INLINE_SIM_BITS(unsigned_word) LSSEXT (signed_word val, int sign_bit);
-INLINE_SIM_BITS(unsigned8) MSSEXT8 (signed8 val, int sign_bit);
-INLINE_SIM_BITS(unsigned16) MSSEXT16 (signed16 val, int sign_bit);
-INLINE_SIM_BITS(unsigned32) MSSEXT32 (signed32 val, int sign_bit);
-INLINE_SIM_BITS(unsigned64) MSSEXT64 (signed64 val, int sign_bit);
+INLINE_SIM_BITS(uint8_t) MSSEXT8 (int8_t val, int sign_bit);
+INLINE_SIM_BITS(uint16_t) MSSEXT16 (int16_t val, int sign_bit);
+INLINE_SIM_BITS(uint32_t) MSSEXT32 (int32_t val, int sign_bit);
+INLINE_SIM_BITS(uint64_t) MSSEXT64 (int64_t val, int sign_bit);
INLINE_SIM_BITS(unsigned_word) MSSEXT (signed_word val, int sign_bit);
#if (WITH_TARGET_WORD_MSB == 0)
diff --git a/sim/common/sim-core.c b/sim/common/sim-core.c
index f07109e0b2ec..fab8f1015958 100644
--- a/sim/common/sim-core.c
+++ b/sim/common/sim-core.c
@@ -285,14 +285,14 @@ sim_core_attach (SIM_DESC sd,
{
unsigned mask = modulo - 1;
/* any zero bits */
- while (mask >= sizeof (unsigned64)) /* minimum modulo */
+ while (mask >= sizeof (uint64_t)) /* minimum modulo */
{
if ((mask & 1) == 0)
mask = 0;
else
mask >>= 1;
}
- if (mask != sizeof (unsigned64) - 1)
+ if (mask != sizeof (uint64_t) - 1)
{
#if (WITH_HW)
sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
@@ -313,7 +313,7 @@ sim_core_attach (SIM_DESC sd,
{
if (optional_buffer == NULL)
{
- int padding = (addr % sizeof (unsigned64));
+ int padding = (addr % sizeof (uint64_t));
unsigned long bytes = (modulo == 0 ? nr_bytes : modulo) + padding;
free_buffer = zalloc (bytes);
buffer = (char*) free_buffer + padding;
@@ -453,7 +453,7 @@ STATIC_INLINE_SIM_CORE\
sim_core_translate (sim_core_mapping *mapping,
address_word addr)
{
- return (void *)((unsigned8 *) mapping->buffer
+ return (void *)((uint8_t *) mapping->buffer
+ ((addr - mapping->base) & mapping->mask));
}
diff --git a/sim/common/sim-events.c b/sim/common/sim-events.c
index b42459ade55c..78668e63a408 100644
--- a/sim/common/sim-events.c
+++ b/sim/common/sim-events.c
@@ -88,7 +88,7 @@ struct _sim_event {
void *data;
sim_event_handler *handler;
/* timer event */
- signed64 time_of_event;
+ int64_t time_of_event;
/* watch wallclock event */
unsigned wallclock;
/* watch core address */
@@ -100,8 +100,8 @@ struct _sim_event {
int is_within; /* 0/1 */
unsigned ub;
unsigned lb;
- unsigned64 ub64;
- unsigned64 lb64;
+ uint64_t ub64;
+ uint64_t lb64;
/* trace info (if any) */
char *trace;
/* list */
@@ -350,7 +350,7 @@ sim_events_init (SIM_DESC sd)
INLINE_SIM_EVENTS\
-(signed64)
+(int64_t)
sim_events_time (SIM_DESC sd)
{
sim_events *events = STATE_EVENTS (sd);
@@ -375,7 +375,7 @@ sim_events_elapsed_time (SIM_DESC sd)
/* Returns the time that remains before the event is raised. */
INLINE_SIM_EVENTS\
-(signed64)
+(int64_t)
sim_events_remain_time (SIM_DESC sd, sim_event *event)
{
if (event == 0)
@@ -391,7 +391,7 @@ STATIC_INLINE_SIM_EVENTS\
update_time_from_event (SIM_DESC sd)
{
sim_events *events = STATE_EVENTS (sd);
- signed64 current_time = sim_events_time (sd);
+ int64_t current_time = sim_events_time (sd);
if (events->queue != NULL)
{
events->time_of_event = events->queue->time_of_event;
@@ -434,12 +434,12 @@ update_time_from_event (SIM_DESC sd)
static void
insert_sim_event (SIM_DESC sd,
sim_event *new_event,
- signed64 delta)
+ int64_t delta)
{
sim_events *events = STATE_EVENTS (sd);
sim_event *curr;
sim_event **prev;
- signed64 time_of_event;
+ int64_t time_of_event;
if (delta < 0)
sim_io_error (sd, "what is past is past!\n");
@@ -473,7 +473,7 @@ insert_sim_event (SIM_DESC sd,
#if EXTERN_SIM_EVENTS_P
sim_event *
sim_events_schedule (SIM_DESC sd,
- signed64 delta_time,
+ int64_t delta_time,
sim_event_handler *handler,
void *data)
{
@@ -485,7 +485,7 @@ sim_events_schedule (SIM_DESC sd,
#if EXTERN_SIM_EVENTS_P
sim_event *
sim_events_schedule_tracef (SIM_DESC sd,
- signed64 delta_time,
+ int64_t delta_time,
sim_event_handler *handler,
void *data,
const char *fmt,
@@ -504,7 +504,7 @@ sim_events_schedule_tracef (SIM_DESC sd,
#if EXTERN_SIM_EVENTS_P
sim_event *
sim_events_schedule_vtracef (SIM_DESC sd,
- signed64 delta_time,
+ int64_t delta_time,
sim_event_handler *handler,
void *data,
const char *fmt,
@@ -535,7 +535,7 @@ sim_events_schedule_vtracef (SIM_DESC sd,
#if EXTERN_SIM_EVENTS_P
void
sim_events_schedule_after_signal (SIM_DESC sd,
- signed64 delta_time,
+ int64_t delta_time,
sim_event_handler *handler,
void *data)
{
@@ -624,8 +624,8 @@ sim_events_watch_clock (SIM_DESC sd,
sim_event *
sim_events_watch_pc (SIM_DESC sd,
int is_within,
- unsigned64 lb,
- unsigned64 ub,
+ uint64_t lb,
+ uint64_t ub,
sim_event_handler *handler,
void *data)
{
@@ -667,8 +667,8 @@ sim_events_watch_sim (SIM_DESC sd,
int nr_bytes,
enum bfd_endian byte_order,
int is_within,
- unsigned64 lb,
- unsigned64 ub,
+ uint64_t lb,
+ uint64_t ub,
sim_event_handler *handler,
void *data)
{
@@ -747,8 +747,8 @@ sim_events_watch_core (SIM_DESC sd,
int nr_bytes,
enum bfd_endian byte_order,
int is_within,
- unsigned64 lb,
- unsigned64 ub,
+ uint64_t lb,
+ uint64_t ub,
sim_event_handler *handler,
void *data)
{
@@ -1147,7 +1147,7 @@ INLINE_SIM_EVENTS\
sim_events_process (SIM_DESC sd)
{
sim_events *events = STATE_EVENTS (sd);
- signed64 event_time = sim_events_time (sd);
+ int64_t event_time = sim_events_time (sd);
/* Clear work_pending before checking nr_held. Clearing
work_pending after nr_held (with out a lock could loose an
diff --git a/sim/common/sim-events.h b/sim/common/sim-events.h
index 153117190edb..b50a427f3af2 100644
--- a/sim/common/sim-events.h
+++ b/sim/common/sim-events.h
@@ -95,8 +95,8 @@ struct _sim_events {
/* timekeeping */
unsigned long elapsed_wallclock;
SIM_ELAPSED_TIME resume_wallclock;
- signed64 time_of_event;
- signed64 time_from_event;
+ int64_t time_of_event;
+ int64_t time_from_event;
};
@@ -110,13 +110,13 @@ extern SIM_RC sim_events_install (SIM_DESC sd);
extern sim_event *sim_events_schedule
(SIM_DESC sd,
- signed64 delta_time,
+ int64_t delta_time,
sim_event_handler *handler,
void *data);
extern sim_event *sim_events_schedule_tracef
(SIM_DESC sd,
- signed64 delta_time,
+ int64_t delta_time,
sim_event_handler *handler,
void *data,
const char *fmt,
@@ -124,7 +124,7 @@ extern sim_event *sim_events_schedule_tracef
extern sim_event *sim_events_schedule_vtracef
(SIM_DESC sd,
- signed64 delta_time,
+ int64_t delta_time,
sim_event_handler *handler,
void *data,
const char *fmt,
@@ -133,7 +133,7 @@ extern sim_event *sim_events_schedule_vtracef
extern void sim_events_schedule_after_signal
(SIM_DESC sd,
- signed64 delta_time,
+ int64_t delta_time,
sim_event_handler *handler,
void *data);
@@ -157,8 +157,8 @@ extern sim_event *sim_events_watch_clock
extern sim_event *sim_events_watch_pc
(SIM_DESC sd,
int is_within,
- unsigned64 lb,
- unsigned64 ub,
+ uint64_t lb,
+ uint64_t ub,
sim_event_handler *handler,
void *data);
@@ -177,8 +177,8 @@ extern sim_event *sim_events_watch_sim
int nr_bytes,
enum bfd_endian byte_order,
int is_within,
- unsigned64 lb,
- unsigned64 ub,
+ uint64_t lb,
+ uint64_t ub,
sim_event_handler *handler,
void *data);
@@ -198,8 +198,8 @@ extern sim_event *sim_events_watch_core
int nr_bytes,
enum bfd_endian byte_order,
int is_within,
- unsigned64 lb,
- unsigned64 ub,
+ uint64_t lb,
+ uint64_t ub,
sim_event_handler *handler,
void *data);
@@ -274,7 +274,7 @@ INLINE_SIM_EVENTS\
/* local concept of elapsed target time */
INLINE_SIM_EVENTS\
-(signed64) sim_events_time
+(int64_t) sim_events_time
(SIM_DESC sd);
@@ -286,7 +286,7 @@ INLINE_SIM_EVENTS\
/* Returns the time that remains before the event is raised. */
INLINE_SIM_EVENTS\
-(signed64) sim_events_remain_time
+(int64_t) sim_events_remain_time
(SIM_DESC sd, sim_event *event);
diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c
index c36096422624..a05c57897ffa 100644
--- a/sim/common/sim-fpu.c
+++ b/sim/common/sim-fpu.c
@@ -50,13 +50,13 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
If digits is -1, then print all digits. */
static void
-print_bits (unsigned64 x,
+print_bits (uint64_t x,
int msbit,
int digits,
sim_fpu_print_func print,
void *arg)
{
- unsigned64 bit = LSBIT64 (msbit);
+ uint64_t bit = LSBIT64 (msbit);
int i = 4;
while (bit && digits)
{
@@ -82,7 +82,7 @@ print_bits (unsigned64 x,
typedef union
{
double d;
- unsigned64 i;
+ uint64_t i;
} sim_fpu_map;
@@ -166,13 +166,13 @@ typedef union
/* Integer constants */
-#define MAX_INT32 ((signed64) LSMASK64 (30, 0))
+#define MAX_INT32 ((int64_t) LSMASK64 (30, 0))
#define MAX_UINT32 LSMASK64 (31, 0)
-#define MIN_INT32 ((signed64) LSMASK64 (63, 31))
+#define MIN_INT32 ((int64_t) LSMASK64 (63, 31))
-#define MAX_INT64 ((signed64) LSMASK64 (62, 0))
+#define MAX_INT64 ((int64_t) LSMASK64 (62, 0))
#define MAX_UINT64 LSMASK64 (63, 0)
-#define MIN_INT64 ((signed64) LSMASK64 (63, 63))
+#define MIN_INT64 ((int64_t) LSMASK64 (63, 63))
#define MAX_INT (is_64bit ? MAX_INT64 : MAX_INT32)
#define MIN_INT (is_64bit ? MIN_INT64 : MIN_INT32)
@@ -180,14 +180,14 @@ typedef union
#define NR_INTBITS (is_64bit ? 64 : 32)
/* Squeeze an unpacked sim_fpu struct into a 32/64 bit integer. */
-STATIC_INLINE_SIM_FPU (unsigned64)
+STATIC_INLINE_SIM_FPU (uint64_t)
pack_fpu (const sim_fpu *src,
int is_double)
{
int sign;
- unsigned64 exp;
- unsigned64 fraction;
- unsigned64 packed;
+ uint64_t exp;
+ uint64_t fraction;
+ uint64_t packed;
switch (src->class)
{
@@ -321,9 +321,9 @@ pack_fpu (const sim_fpu *src,
/* Unpack a 32/64 bit integer into a sim_fpu structure. */
STATIC_INLINE_SIM_FPU (void)
-unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
+unpack_fpu (sim_fpu *dst, uint64_t packed, int is_double)
{
- unsigned64 fraction = LSMASKED64 (packed, NR_FRACBITS - 1, 0);
+ uint64_t fraction = LSMASKED64 (packed, NR_FRACBITS - 1, 0);
unsigned exp = LSEXTRACTED64 (packed, NR_EXPBITS + NR_FRACBITS - 1, NR_FRACBITS);
int sign = (packed & SIGNBIT) != 0;
@@ -416,8 +416,8 @@ unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
}
else
{
- unsigned32 val = pack_fpu (dst, 0);
- unsigned32 org = packed;
+ uint32_t val = pack_fpu (dst, 0);
+ uint32_t org = packed;
ASSERT (val == org);
}
}
@@ -426,12 +426,12 @@ unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
/* Convert a floating point into an integer. */
STATIC_INLINE_SIM_FPU (int)
-fpu2i (signed64 *i,
+fpu2i (int64_t *i,
const sim_fpu *s,
int is_64bit,
sim_fpu_round round)
{
- unsigned64 tmp;
+ uint64_t tmp;
int shift;
int status = 0;
if (sim_fpu_is_zero (s))
@@ -526,7 +526,7 @@ fpu2i (signed64 *i,
/* Convert an integer into a floating point. */
STATIC_INLINE_SIM_FPU (int)
-i2fpu (sim_fpu *f, signed64 i, int is_64bit)
+i2fpu (sim_fpu *f, int64_t i, int is_64bit)
{
int status = 0;
if (i == 0)
@@ -585,7 +585,7 @@ i2fpu (sim_fpu *f, signed64 i, int is_64bit)
/* sanity check */
{
- signed64 val;
+ int64_t val;
fpu2i (&val, f, is_64bit, sim_fpu_round_zero);
if (i >= MIN_INT32 && i <= MAX_INT32)
{
@@ -599,10 +599,10 @@ i2fpu (sim_fpu *f, signed64 i, int is_64bit)
/* Convert a floating point into an integer. */
STATIC_INLINE_SIM_FPU (int)
-fpu2u (unsigned64 *u, const sim_fpu *s, int is_64bit)
+fpu2u (uint64_t *u, const sim_fpu *s, int is_64bit)
{
const int is_double = 1;
- unsigned64 tmp;
+ uint64_t tmp;
int shift;
if (sim_fpu_is_zero (s))
{
@@ -656,7 +656,7 @@ fpu2u (unsigned64 *u, const sim_fpu *s, int is_64bit)
/* Convert an unsigned integer into a floating point. */
STATIC_INLINE_SIM_FPU (int)
-u2fpu (sim_fpu *f, unsigned64 u, int is_64bit)
+u2fpu (sim_fpu *f, uint64_t u, int is_64bit)
{
if (u == 0)
{
@@ -684,30 +684,30 @@ u2fpu (sim_fpu *f, unsigned64 u, int is_64bit)
/* register <-> sim_fpu */
INLINE_SIM_FPU (void)
-sim_fpu_32to (sim_fpu *f, unsigned32 s)
+sim_fpu_32to (sim_fpu *f, uint32_t s)
{
unpack_fpu (f, s, 0);
}
INLINE_SIM_FPU (void)
-sim_fpu_232to (sim_fpu *f, unsigned32 h, unsigned32 l)
+sim_fpu_232to (sim_fpu *f, uint32_t h, uint32_t l)
{
- unsigned64 s = h;
+ uint64_t s = h;
s = (s << 32) | l;
unpack_fpu (f, s, 1);
}
INLINE_SIM_FPU (void)
-sim_fpu_64to (sim_fpu *f, unsigned64 s)
+sim_fpu_64to (sim_fpu *f, uint64_t s)
{
unpack_fpu (f, s, 1);
}
INLINE_SIM_FPU (void)
-sim_fpu_to32 (unsigned32 *s,
+sim_fpu_to32 (uint32_t *s,
const sim_fpu *f)
{
*s = pack_fpu (f, 0);
@@ -715,17 +715,17 @@ sim_fpu_to32 (unsigned32 *s,
INLINE_SIM_FPU (void)
-sim_fpu_to232 (unsigned32 *h, unsigned32 *l,
+sim_fpu_to232 (uint32_t *h, uint32_t *l,
const sim_fpu *f)
{
- unsigned64 s = pack_fpu (f, 1);
+ uint64_t s = pack_fpu (f, 1);
*l = s;
*h = (s >> 32);
}
INLINE_SIM_FPU (void)
-sim_fpu_to64 (unsigned64 *u,
+sim_fpu_to64 (uint64_t *u,
const sim_fpu *f)
{
*u = pack_fpu (f, 1);
@@ -736,7 +736,7 @@ INLINE_SIM_FPU (void)
sim_fpu_fractionto (sim_fpu *f,
int sign,
int normal_exp,
- unsigned64 fraction,
+ uint64_t fraction,
int precision)
{
int shift = (NR_FRAC_GUARD - precision);
@@ -752,13 +752,13 @@ sim_fpu_fractionto (sim_fpu *f,
}
-INLINE_SIM_FPU (unsigned64)
+INLINE_SIM_FPU (uint64_t)
sim_fpu_tofraction (const sim_fpu *d,
int precision)
{
/* We have NR_FRAC_GUARD bits, we want only PRECISION bits. */
int shift = (NR_FRAC_GUARD - precision);
- unsigned64 fraction = (d->fraction & ~IMPLICIT_1);
+ uint64_t fraction = (d->fraction & ~IMPLICIT_1);
if (shift >= 0)
return fraction >> shift;
else
@@ -835,9 +835,9 @@ do_normal_round (sim_fpu *f,
int nr_guards,
sim_fpu_round round)
{
- unsigned64 guardmask = LSMASK64 (nr_guards - 1, 0);
- unsigned64 guardmsb = LSBIT64 (nr_guards - 1);
- unsigned64 fraclsb = guardmsb << 1;
+ uint64_t guardmask = LSMASK64 (nr_guards - 1, 0);
+ uint64_t guardmsb = LSBIT64 (nr_guards - 1);
+ uint64_t fraclsb = guardmsb << 1;
if ((f->fraction & guardmask))
{
int status = sim_fpu_status_inexact;
@@ -1055,8 +1055,8 @@ sim_fpu_add (sim_fpu *f,
{
int status = 0;
int shift = l->normal_exp - r->normal_exp;
- unsigned64 lfraction;
- unsigned64 rfraction;
+ uint64_t lfraction;
+ uint64_t rfraction;
/* use exp of larger */
if (shift >= NR_FRAC_GUARD)
{
@@ -1113,7 +1113,7 @@ sim_fpu_add (sim_fpu *f,
/* sign? */
f->class = sim_fpu_class_number;
- if (((signed64) f->fraction) >= 0)
+ if (((int64_t) f->fraction) >= 0)
f->sign = 0;
else
{
@@ -1208,8 +1208,8 @@ sim_fpu_sub (sim_fpu *f,
{
int status = 0;
int shift = l->normal_exp - r->normal_exp;
- unsigned64 lfraction;
- unsigned64 rfraction;
+ uint64_t lfraction;
+ uint64_t rfraction;
/* use exp of larger */
if (shift >= NR_FRAC_GUARD)
{
@@ -1267,7 +1267,7 @@ sim_fpu_sub (sim_fpu *f,
/* sign? */
f->class = sim_fpu_class_number;
- if (((signed64) f->fraction) >= 0)
+ if (((int64_t) f->fraction) >= 0)
f->sign = 0;
else
{
@@ -1354,19 +1354,19 @@ sim_fpu_mul (sim_fpu *f,
/* Calculate the mantissa by multiplying both 64bit numbers to get a
128 bit number. */
{
- unsigned64 low;
- unsigned64 high;
- unsigned64 nl = l->fraction & 0xffffffff;
- unsigned64 nh = l->fraction >> 32;
- unsigned64 ml = r->fraction & 0xffffffff;
- unsigned64 mh = r->fraction >>32;
- unsigned64 pp_ll = ml * nl;
- unsigned64 pp_hl = mh * nl;
- unsigned64 pp_lh = ml * nh;
- unsigned64 pp_hh = mh * nh;
- unsigned64 res2 = 0;
- unsigned64 res0 = 0;
- unsigned64 ps_hh__ = pp_hl + pp_lh;
+ uint64_t low;
+ uint64_t high;
+ uint64_t nl = l->fraction & 0xffffffff;
+ uint64_t nh = l->fraction >> 32;
+ uint64_t ml = r->fraction & 0xffffffff;
+ uint64_t mh = r->fraction >>32;
+ uint64_t pp_ll = ml * nl;
+ uint64_t pp_hl = mh * nl;
+ uint64_t pp_lh = ml * nh;
+ uint64_t pp_hh = mh * nh;
+ uint64_t res2 = 0;
+ uint64_t res0 = 0;
+ uint64_t ps_hh__ = pp_hl + pp_lh;
if (ps_hh__ < pp_hl)
res2 += UNSIGNED64 (0x100000000);
pp_hl = (ps_hh__ << 32) & UNSIGNED64 (0xffffffff00000000);
@@ -1497,10 +1497,10 @@ sim_fpu_div (sim_fpu *f,
/* quotient = ( ( numerator / denominator)
x 2^(numerator exponent - denominator exponent)
*/
- unsigned64 numerator;
- unsigned64 denominator;
- unsigned64 quotient;
- unsigned64 bit;
+ uint64_t numerator;
+ uint64_t denominator;
+ uint64_t quotient;
+ uint64_t bit;
f->class = sim_fpu_class_number;
f->sign = l->sign ^ r->sign;
@@ -1993,10 +1993,10 @@ sim_fpu_sqrt (sim_fpu *f,
{
/* Generate sqrt(x) bit by bit. */
- unsigned64 y;
- unsigned64 q;
- unsigned64 s;
- unsigned64 b;
+ uint64_t y;
+ uint64_t q;
+ uint64_t s;
+ uint64_t b;
f->class = sim_fpu_class_number;
f->sign = 0;
@@ -2018,7 +2018,7 @@ sim_fpu_sqrt (sim_fpu *f,
while (b)
{
- unsigned64 t = s + b;
+ uint64_t t = s + b;
if (t <= y)
{
s |= (b << 1);
@@ -2046,7 +2046,7 @@ sim_fpu_sqrt (sim_fpu *f,
INLINE_SIM_FPU (int)
sim_fpu_i32to (sim_fpu *f,
- signed32 i,
+ int32_t i,
sim_fpu_round round)
{
i2fpu (f, i, 0);
@@ -2055,7 +2055,7 @@ sim_fpu_i32to (sim_fpu *f,
INLINE_SIM_FPU (int)
sim_fpu_u32to (sim_fpu *f,
- unsigned32 u,
+ uint32_t u,
sim_fpu_round round)
{
u2fpu (f, u, 0);
@@ -2064,7 +2064,7 @@ sim_fpu_u32to (sim_fpu *f,
INLINE_SIM_FPU (int)
sim_fpu_i64to (sim_fpu *f,
- signed64 i,
+ int64_t i,
sim_fpu_round round)
{
i2fpu (f, i, 1);
@@ -2073,7 +2073,7 @@ sim_fpu_i64to (sim_fpu *f,
INLINE_SIM_FPU (int)
sim_fpu_u64to (sim_fpu *f,
- unsigned64 u,
+ uint64_t u,
sim_fpu_round round)
{
u2fpu (f, u, 1);
@@ -2082,29 +2082,29 @@ sim_fpu_u64to (sim_fpu *f,
INLINE_SIM_FPU (int)
-sim_fpu_to32i (signed32 *i,
+sim_fpu_to32i (int32_t *i,
const sim_fpu *f,
sim_fpu_round round)
{
- signed64 i64;
+ int64_t i64;
int status = fpu2i (&i64, f, 0, round);
*i = i64;
return status;
}
INLINE_SIM_FPU (int)
-sim_fpu_to32u (unsigned32 *u,
+sim_fpu_to32u (uint32_t *u,
const sim_fpu *f,
sim_fpu_round round)
{
- unsigned64 u64;
+ uint64_t u64;
int status = fpu2u (&u64, f, 0);
*u = u64;
return status;
}
INLINE_SIM_FPU (int)
-sim_fpu_to64i (signed64 *i,
+sim_fpu_to64i (int64_t *i,
const sim_fpu *f,
sim_fpu_round round)
{
@@ -2113,7 +2113,7 @@ sim_fpu_to64i (signed64 *i,
INLINE_SIM_FPU (int)
-sim_fpu_to64u (unsigned64 *u,
+sim_fpu_to64u (uint64_t *u,
const sim_fpu *f,
sim_fpu_round round)
{
@@ -2277,18 +2277,18 @@ sim_fpu_exp (const sim_fpu *d)
}
-INLINE_SIM_FPU (unsigned64)
+INLINE_SIM_FPU (uint64_t)
sim_fpu_fraction (const sim_fpu *d)
{
return d->fraction;
}
-INLINE_SIM_FPU (unsigned64)
+INLINE_SIM_FPU (uint64_t)
sim_fpu_guard (const sim_fpu *d, int is_double)
{
- unsigned64 rv;
- unsigned64 guardmask = LSMASK64 (NR_GUARDS - 1, 0);
+ uint64_t rv;
+ uint64_t guardmask = LSMASK64 (NR_GUARDS - 1, 0);
rv = (d->fraction & guardmask) >> NR_PAD;
return rv;
}
diff --git a/sim/common/sim-fpu.h b/sim/common/sim-fpu.h
index 1f47528954a9..447621b5d731 100644
--- a/sim/common/sim-fpu.h
+++ b/sim/common/sim-fpu.h
@@ -91,7 +91,7 @@ typedef enum
typedef struct _sim_fpu {
sim_fpu_class class;
int sign;
- unsigned64 fraction;
+ uint64_t fraction;
int normal_exp;
} sim_fpu;
@@ -171,13 +171,13 @@ typedef enum
emulating exact FPU behavior, sim_fpu_round_{32,64} should be
called before packing the sim_fpu value. */
-INLINE_SIM_FPU (void) sim_fpu_32to (sim_fpu *f, unsigned32 s);
-INLINE_SIM_FPU (void) sim_fpu_232to (sim_fpu *f, unsigned32 h, unsigned32 l);
-INLINE_SIM_FPU (void) sim_fpu_64to (sim_fpu *f, unsigned64 d);
+INLINE_SIM_FPU (void) sim_fpu_32to (sim_fpu *f, uint32_t s);
+INLINE_SIM_FPU (void) sim_fpu_232to (sim_fpu *f, uint32_t h, uint32_t l);
+INLINE_SIM_FPU (void) sim_fpu_64to (sim_fpu *f, uint64_t d);
-INLINE_SIM_FPU (void) sim_fpu_to32 (unsigned32 *s, const sim_fpu *f);
-INLINE_SIM_FPU (void) sim_fpu_to232 (unsigned32 *h, unsigned32 *l, const sim_fpu *f);
-INLINE_SIM_FPU (void) sim_fpu_to64 (unsigned64 *d, const sim_fpu *f);
+INLINE_SIM_FPU (void) sim_fpu_to32 (uint32_t *s, const sim_fpu *f);
+INLINE_SIM_FPU (void) sim_fpu_to232 (uint32_t *h, uint32_t *l, const sim_fpu *f);
+INLINE_SIM_FPU (void) sim_fpu_to64 (uint64_t *d, const sim_fpu *f);
/* Create a sim_fpu struct using raw information. (FRACTION & LSMASK
@@ -189,12 +189,12 @@ INLINE_SIM_FPU (void) sim_fpu_to64 (unsigned64 *d, const sim_fpu *f);
You can not specify zero using this function. */
-INLINE_SIM_FPU (void) sim_fpu_fractionto (sim_fpu *f, int sign, int normal_exp, unsigned64 fraction, int precision);
+INLINE_SIM_FPU (void) sim_fpu_fractionto (sim_fpu *f, int sign, int normal_exp, uint64_t fraction, int precision);
/* Reverse operation. If S is a non-zero number, discards the implied
leading one and returns PRECISION fraction bits. No rounding is
performed. */
-INLINE_SIM_FPU (unsigned64) sim_fpu_tofraction (const sim_fpu *s, int precision);
+INLINE_SIM_FPU (uint64_t) sim_fpu_tofraction (const sim_fpu *s, int precision);
@@ -250,37 +250,37 @@ INLINE_SIM_FPU (int) sim_fpu_sqrt (sim_fpu *f,
/* Conversion of integer <-> floating point. */
-INLINE_SIM_FPU (int) sim_fpu_i32to (sim_fpu *f, signed32 i,
+INLINE_SIM_FPU (int) sim_fpu_i32to (sim_fpu *f, int32_t i,
sim_fpu_round round);
-INLINE_SIM_FPU (int) sim_fpu_u32to (sim_fpu *f, unsigned32 u,
+INLINE_SIM_FPU (int) sim_fpu_u32to (sim_fpu *f, uint32_t u,
sim_fpu_round round);
-INLINE_SIM_FPU (int) sim_fpu_i64to (sim_fpu *f, signed64 i,
+INLINE_SIM_FPU (int) sim_fpu_i64to (sim_fpu *f, int64_t i,
sim_fpu_round round);
-INLINE_SIM_FPU (int) sim_fpu_u64to (sim_fpu *f, unsigned64 u,
+INLINE_SIM_FPU (int) sim_fpu_u64to (sim_fpu *f, uint64_t u,
sim_fpu_round round);
#if 0
-INLINE_SIM_FPU (int) sim_fpu_i232to (sim_fpu *f, signed32 h, signed32 l,
+INLINE_SIM_FPU (int) sim_fpu_i232to (sim_fpu *f, int32_t h, int32_t l,
sim_fpu_round round);
#endif
#if 0
-INLINE_SIM_FPU (int) sim_fpu_u232to (sim_fpu *f, unsigned32 h, unsigned32 l,
+INLINE_SIM_FPU (int) sim_fpu_u232to (sim_fpu *f, uint32_t h, uint32_t l,
sim_fpu_round round);
#endif
-INLINE_SIM_FPU (int) sim_fpu_to32i (signed32 *i, const sim_fpu *f,
+INLINE_SIM_FPU (int) sim_fpu_to32i (int32_t *i, const sim_fpu *f,
sim_fpu_round round);
-INLINE_SIM_FPU (int) sim_fpu_to32u (unsigned32 *u, const sim_fpu *f,
+INLINE_SIM_FPU (int) sim_fpu_to32u (uint32_t *u, const sim_fpu *f,
sim_fpu_round round);
-INLINE_SIM_FPU (int) sim_fpu_to64i (signed64 *i, const sim_fpu *f,
+INLINE_SIM_FPU (int) sim_fpu_to64i (int64_t *i, const sim_fpu *f,
sim_fpu_round round);
-INLINE_SIM_FPU (int) sim_fpu_to64u (unsigned64 *u, const sim_fpu *f,
+INLINE_SIM_FPU (int) sim_fpu_to64u (uint64_t *u, const sim_fpu *f,
sim_fpu_round round);
#if 0
-INLINE_SIM_FPU (int) sim_fpu_to232i (signed64 *h, signed64 *l, const sim_fpu *f,
+INLINE_SIM_FPU (int) sim_fpu_to232i (int64_t *h, int64_t *l, const sim_fpu *f,
sim_fpu_round round);
#endif
#if 0
-INLINE_SIM_FPU (int) sim_fpu_to232u (unsigned64 *h, unsigned64 *l, const sim_fpu *f,
+INLINE_SIM_FPU (int) sim_fpu_to232u (uint64_t *h, uint64_t *l, const sim_fpu *f,
sim_fpu_round round);
#endif
@@ -320,8 +320,8 @@ INLINE_SIM_FPU (int) sim_fpu_is_denorm (const sim_fpu *s); /* !zero */
INLINE_SIM_FPU (int) sim_fpu_sign (const sim_fpu *s);
INLINE_SIM_FPU (int) sim_fpu_exp (const sim_fpu *s);
-INLINE_SIM_FPU (unsigned64) sim_fpu_fraction (const sim_fpu *s);
-INLINE_SIM_FPU (unsigned64) sim_fpu_guard (const sim_fpu *s, int is_double);
+INLINE_SIM_FPU (uint64_t) sim_fpu_fraction (const sim_fpu *s);
+INLINE_SIM_FPU (uint64_t) sim_fpu_guard (const sim_fpu *s, int is_double);
diff --git a/sim/common/sim-memopt.c b/sim/common/sim-memopt.c
index eb1bf0671655..342188391d73 100644
--- a/sim/common/sim-memopt.c
+++ b/sim/common/sim-memopt.c
@@ -41,7 +41,7 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-options.h"
/* Memory fill byte. */
-static unsigned8 fill_byte_value;
+static uint8_t fill_byte_value;
static int fill_byte_flag = 0;
/* Memory mapping; see OPTION_MEMORY_MAPFILE. */
@@ -143,7 +143,7 @@ do_memopt_add (SIM_DESC sd,
{
/* Allocate new well-aligned buffer, just as sim_core_attach(). */
void *aligned_buffer;
- int padding = (addr % sizeof (unsigned64));
+ int padding = (addr % sizeof (uint64_t));
unsigned long bytes;
#ifdef HAVE_MMAP
@@ -457,7 +457,7 @@ memory_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
case OPTION_MEMORY_CLEAR:
{
- fill_byte_value = (unsigned8) 0;
+ fill_byte_value = (uint8_t) 0;
fill_byte_flag = 1;
return SIM_RC_OK;
break;
@@ -472,7 +472,7 @@ memory_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
sim_io_eprintf (sd, "Missing fill value between 0 and 255\n");
return SIM_RC_FAIL;
}
- fill_byte_value = (unsigned8) fill_value;
+ fill_byte_value = (uint8_t) fill_value;
fill_byte_flag = 1;
return SIM_RC_OK;
break;
diff --git a/sim/common/sim-n-bits.h b/sim/common/sim-n-bits.h
index b15bb95cfdbe..bcb00436ce0e 100644
--- a/sim/common/sim-n-bits.h
+++ b/sim/common/sim-n-bits.h
@@ -34,8 +34,8 @@
#endif
/* NOTE: See end of file for #undef */
-#define unsignedN XCONCAT2(unsigned,N)
-#define signedN XCONCAT2(signed,N)
+#define unsignedN XCONCAT3(uint,N,_t)
+#define signedN XCONCAT3(int,N,_t)
#define LSMASKn XCONCAT2(LSMASK,N)
#define MSMASKn XCONCAT2(MSMASK,N)
#define LSMASKEDn XCONCAT2(LSMASKED,N)
diff --git a/sim/common/sim-profile.c b/sim/common/sim-profile.c
index 93956ab64f08..7d229822b1ba 100644
--- a/sim/common/sim-profile.c
+++ b/sim/common/sim-profile.c
@@ -693,7 +693,7 @@ profile_print_pc (sim_cpu *cpu, int verbose)
{
int ok;
/* FIXME: what if the target has a 64 bit PC? */
- unsigned32 header[3];
+ uint32_t header[3];
unsigned loop;
if (PROFILE_PC_END (profile) != 0)
{
@@ -718,7 +718,7 @@ profile_print_pc (sim_cpu *cpu, int verbose)
ok && (loop < PROFILE_PC_NR_BUCKETS (profile));
loop++)
{
- signed16 sample;
+ int16_t sample;
if (PROFILE_PC_COUNT (profile) [loop] >= 0xffff)
sample = 0xffff;
else
diff --git a/sim/common/sim-trace.c b/sim/common/sim-trace.c
index a2ddf74b8b0c..0b63bdb07b65 100644
--- a/sim/common/sim-trace.c
+++ b/sim/common/sim-trace.c
@@ -558,13 +558,13 @@ print_data (SIM_DESC sd,
{
switch (size)
{
- case sizeof (unsigned32):
- trace_printf (sd, cpu, " 0x%08lx", (long) * (unsigned32*) data);
+ case sizeof (uint32_t):
+ trace_printf (sd, cpu, " 0x%08lx", (long) * (uint32_t*) data);
break;
- case sizeof (unsigned64):
+ case sizeof (uint64_t):
trace_printf (sd, cpu, " 0x%08lx%08lx",
- (long) ((* (unsigned64*) data) >> 32),
- (long) * (unsigned64*) data);
+ (long) ((* (uint64_t*) data) >> 32),
+ (long) * (uint64_t*) data);
break;
default:
abort ();
@@ -585,10 +585,10 @@ print_data (SIM_DESC sd,
{
/* FIXME: Assumes sizeof float == 4; sizeof double == 8 */
case 4:
- sim_fpu_32to (&fp, *(unsigned32*)data);
+ sim_fpu_32to (&fp, *(uint32_t*)data);
break;
case 8:
- sim_fpu_64to (&fp, *(unsigned64*)data);
+ sim_fpu_64to (&fp, *(uint64_t*)data);
break;
default:
abort ();
@@ -598,12 +598,12 @@ print_data (SIM_DESC sd,
{
case 4:
trace_printf (sd, cpu, " (0x%08lx)",
- (long) *(unsigned32*)data);
+ (long) *(uint32_t*)data);
break;
case 8:
trace_printf (sd, cpu, " (0x%08lx%08lx)",
- (long) (*(unsigned64*)data >> 32),
- (long) (*(unsigned64*)data));
+ (long) (*(uint64_t*)data >> 32),
+ (long) (*(uint64_t*)data));
break;
default:
abort ();
diff --git a/sim/common/sim-trace.h b/sim/common/sim-trace.h
index c68a5eeedb7b..d08810d9fccd 100644
--- a/sim/common/sim-trace.h
+++ b/sim/common/sim-trace.h
@@ -179,13 +179,13 @@ typedef struct _trace_data {
/* Buffer to save the inputs for the current instruction. Use a
union to force the buffer into correct alignment */
union {
- unsigned8 i8;
- unsigned16 i16;
- unsigned32 i32;
- unsigned64 i64;
+ uint8_t i8;
+ uint16_t i16;
+ uint32_t i32;
+ uint64_t i64;
} trace_input_data[16];
- unsigned8 trace_input_fmt[16];
- unsigned8 trace_input_size[16];
+ uint8_t trace_input_fmt[16];
+ uint8_t trace_input_size[16];
int trace_input_idx;
#define TRACE_INPUT_DATA(t) ((t)->trace_input_data)
#define TRACE_INPUT_FMT(t) ((t)->trace_input_fmt)
diff --git a/sim/common/sim-types.h b/sim/common/sim-types.h
index fd06e8e37802..b4dad0d957a5 100644
--- a/sim/common/sim-types.h
+++ b/sim/common/sim-types.h
@@ -33,8 +33,11 @@
TYPES:
- signed* signed type of the given size
- unsigned* The corresponding insigned type
+ intNN_t Signed type of the given bit size
+ uintNN_t The corresponding unsigned type
+
+ signed128 Non-standard type for 128-bit integers.
+ unsigned128 Likewise, but unsigned.
SIZES
@@ -56,38 +59,28 @@
# define SIGNED32(X) (X##i32)
# define SIGNED64(X) (X##i64)
#else
-# define UNSIGNED32(X) ((unsigned32) X##UL)
-# define UNSIGNED64(X) ((unsigned64) X##ULL)
-# define SIGNED32(X) ((signed32) X##L)
-# define SIGNED64(X) ((signed64) X##LL)
+# define UNSIGNED32(X) ((uint32_t) X##UL)
+# define UNSIGNED64(X) ((uint64_t) X##ULL)
+# define SIGNED32(X) ((int32_t) X##L)
+# define SIGNED64(X) ((int64_t) X##LL)
#endif
-typedef int8_t signed8;
-typedef int16_t signed16;
-typedef int32_t signed32;
-typedef int64_t signed64;
-
-typedef uint8_t unsigned8;
-typedef uint16_t unsigned16;
-typedef uint32_t unsigned32;
-typedef uint64_t unsigned64;
-
-typedef struct { unsigned64 a[2]; } unsigned128;
-typedef struct { signed64 a[2]; } signed128;
+typedef struct { uint64_t a[2]; } unsigned128;
+typedef struct { int64_t a[2]; } signed128;
/* byte based */
-typedef signed8 signed_1;
-typedef signed16 signed_2;
-typedef signed32 signed_4;
-typedef signed64 signed_8;
+typedef int8_t signed_1;
+typedef int16_t signed_2;
+typedef int32_t signed_4;
+typedef int64_t signed_8;
typedef signed128 signed_16;
-typedef unsigned8 unsigned_1;
-typedef unsigned16 unsigned_2;
-typedef unsigned32 unsigned_4;
-typedef unsigned64 unsigned_8;
+typedef uint8_t unsigned_1;
+typedef uint16_t unsigned_2;
+typedef uint32_t unsigned_4;
+typedef uint64_t unsigned_8;
typedef unsigned128 unsigned_16;
@@ -103,16 +96,16 @@ typedef unsigned128 unsigned_16;
/* target architecture based */
#if (WITH_TARGET_WORD_BITSIZE == 64)
-typedef unsigned64 unsigned_word;
-typedef signed64 signed_word;
+typedef uint64_t unsigned_word;
+typedef int64_t signed_word;
#endif
#if (WITH_TARGET_WORD_BITSIZE == 32)
-typedef unsigned32 unsigned_word;
-typedef signed32 signed_word;
+typedef uint32_t unsigned_word;
+typedef int32_t signed_word;
#endif
#if (WITH_TARGET_WORD_BITSIZE == 16)
-typedef unsigned16 unsigned_word;
-typedef signed16 signed_word;
+typedef uint16_t unsigned_word;
+typedef int16_t signed_word;
#endif
#define PRI_TW(t) SIM_PRI_TB (t, WITH_TARGET_WORD_BITSIZE)
@@ -122,16 +115,16 @@ typedef signed16 signed_word;
/* Other instructions */
#if (WITH_TARGET_ADDRESS_BITSIZE == 64)
-typedef unsigned64 unsigned_address;
-typedef signed64 signed_address;
+typedef uint64_t unsigned_address;
+typedef int64_t signed_address;
#endif
#if (WITH_TARGET_ADDRESS_BITSIZE == 32)
-typedef unsigned32 unsigned_address;
-typedef signed32 signed_address;
+typedef uint32_t unsigned_address;
+typedef int32_t signed_address;
#endif
#if (WITH_TARGET_ADDRESS_BITSIZE == 16)
-typedef unsigned16 unsigned_address;
-typedef signed16 signed_address;
+typedef uint16_t unsigned_address;
+typedef int16_t signed_address;
#endif
typedef unsigned_address address_word;
@@ -142,12 +135,12 @@ typedef unsigned_address address_word;
/* IEEE 1275 cell size */
#if (WITH_TARGET_CELL_BITSIZE == 64)
-typedef unsigned64 unsigned_cell;
-typedef signed64 signed_cell;
+typedef uint64_t unsigned_cell;
+typedef int64_t signed_cell;
#endif
#if (WITH_TARGET_CELL_BITSIZE == 32)
-typedef unsigned32 unsigned_cell;
-typedef signed32 signed_cell;
+typedef uint32_t unsigned_cell;
+typedef int32_t signed_cell;
#endif
typedef signed_cell cell_word; /* cells are normally signed */
@@ -158,10 +151,10 @@ typedef signed_cell cell_word; /* cells are normally signed */
/* Floating point registers */
#if (WITH_TARGET_FLOATING_POINT_BITSIZE == 64)
-typedef unsigned64 fp_word;
+typedef uint64_t fp_word;
#endif
#if (WITH_TARGET_FLOATING_POINT_BITSIZE == 32)
-typedef unsigned32 fp_word;
+typedef uint32_t fp_word;
#endif
#define PRI_TF(t) SIM_PRI_TB (t, WITH_TARGET_FLOATING_POINT_BITSIZE)
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 17/17] sim: ppc: migrate to standard uintXX_t types
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
` (14 preceding siblings ...)
2022-01-01 20:55 ` [PATCH 16/17] sim: common: " Mike Frysinger
@ 2022-01-01 20:55 ` Mike Frysinger
15 siblings, 0 replies; 17+ messages in thread
From: Mike Frysinger @ 2022-01-01 20:55 UTC (permalink / raw)
To: gdb-patches
Drop the sim-specific unsignedXX types and move to the standard uintXX_t
types that C11 provides.
---
sim/ppc/altivec.igen | 404 +++++------
sim/ppc/altivec_registers.h | 8 +-
sim/ppc/bits.c | 24 +-
sim/ppc/bits.h | 32 +-
sim/ppc/corefile.c | 2 +-
sim/ppc/cpu.c | 14 +-
sim/ppc/cpu.h | 8 +-
sim/ppc/device.c | 6 +-
sim/ppc/device.h | 4 +-
sim/ppc/double.c | 16 +-
sim/ppc/e500.igen | 1274 +++++++++++++++++-----------------
sim/ppc/e500_expression.h | 24 +-
sim/ppc/e500_registers.h | 4 +-
sim/ppc/emul_chirp.c | 32 +-
sim/ppc/emul_generic.c | 12 +-
sim/ppc/emul_generic.h | 4 +-
sim/ppc/emul_unix.c | 154 ++--
sim/ppc/events.c | 22 +-
sim/ppc/events.h | 6 +-
sim/ppc/hw_disk.c | 12 +-
sim/ppc/hw_eeprom.c | 44 +-
sim/ppc/hw_htab.c | 66 +-
sim/ppc/hw_ide.c | 20 +-
sim/ppc/hw_nvram.c | 12 +-
sim/ppc/hw_opic.c | 4 +-
sim/ppc/hw_register.c | 2 +-
sim/ppc/hw_sem.c | 2 +-
sim/ppc/hw_trace.c | 2 +-
sim/ppc/idecode_expression.h | 44 +-
sim/ppc/pk_disklabel.c | 38 +-
sim/ppc/ppc-instructions | 308 ++++----
sim/ppc/psim.c | 6 +-
sim/ppc/registers.c | 4 +-
sim/ppc/registers.h | 10 +-
sim/ppc/sim-main.h | 2 +-
sim/ppc/tree.c | 4 +-
sim/ppc/words.h | 45 +-
37 files changed, 1332 insertions(+), 1343 deletions(-)
diff --git a/sim/ppc/altivec.igen b/sim/ppc/altivec.igen
index c6b7f8164c32..63fe95a53d51 100644
--- a/sim/ppc/altivec.igen
+++ b/sim/ppc/altivec.igen
@@ -27,16 +27,16 @@
:cache:av:::VS:VS:
:cache:av::vreg *:vS:VS:(cpu_registers(processor)->altivec.vr + VS)
-:cache:av::unsigned32:VS_BITMASK:VS:(1 << VS)
+:cache:av::uint32_t:VS_BITMASK:VS:(1 << VS)
:cache:av:::VA:VA:
:cache:av::vreg *:vA:VA:(cpu_registers(processor)->altivec.vr + VA)
-:cache:av::unsigned32:VA_BITMASK:VA:(1 << VA)
+:cache:av::uint32_t:VA_BITMASK:VA:(1 << VA)
:cache:av:::VB:VB:
:cache:av::vreg *:vB:VB:(cpu_registers(processor)->altivec.vr + VB)
-:cache:av::unsigned32:VB_BITMASK:VB:(1 << VB)
+:cache:av::uint32_t:VB_BITMASK:VB:(1 << VB)
:cache:av:::VC:VC:
:cache:av::vreg *:vC:VC:(cpu_registers(processor)->altivec.vr + VC)
-:cache:av::unsigned32:VC_BITMASK:VC:(1 << VC)
+:cache:av::uint32_t:VC_BITMASK:VC:(1 << VC)
# Flags for model.h
::model-macro:::
@@ -77,7 +77,7 @@
} while (0)
# Trace waiting for AltiVec registers to become available
-void::model-static::model_trace_altivec_busy_p:model_data *model_ptr, unsigned32 vr_busy
+void::model-static::model_trace_altivec_busy_p:model_data *model_ptr, uint32_t vr_busy
int i;
if (vr_busy) {
vr_busy &= model_ptr->vr_busy;
@@ -91,7 +91,7 @@ void::model-static::model_trace_altivec_busy_p:model_data *model_ptr, unsigned32
TRACE(trace_model, ("Waiting for VSCR\n"));
# Trace making AltiVec registers busy
-void::model-static::model_trace_altivec_make_busy:model_data *model_ptr, unsigned32 vr_mask, unsigned32 cr_mask
+void::model-static::model_trace_altivec_make_busy:model_data *model_ptr, uint32_t vr_mask, uint32_t cr_mask
int i;
if (vr_mask) {
for(i = 0; i < 32; i++) {
@@ -109,9 +109,9 @@ void::model-static::model_trace_altivec_make_busy:model_data *model_ptr, unsigne
}
# Schedule an AltiVec instruction that takes integer input registers and produces output registers
-void::model-function::ppc_insn_int_vr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned32 out_vmask, const unsigned32 in_vmask
- const unsigned32 int_mask = out_mask | in_mask;
- const unsigned32 vr_mask = out_vmask | in_vmask;
+void::model-function::ppc_insn_int_vr:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask, const uint32_t out_vmask, const uint32_t in_vmask
+ const uint32_t int_mask = out_mask | in_mask;
+ const uint32_t vr_mask = out_vmask | in_vmask;
model_busy *busy_ptr;
if ((model_ptr->int_busy & int_mask) != 0 || (model_ptr->vr_busy & vr_mask)) {
@@ -146,8 +146,8 @@ void::model-function::ppc_insn_int_vr:itable_index index, model_data *model_ptr,
}
# Schedule an AltiVec instruction that takes vector input registers and produces vector output registers
-void::model-function::ppc_insn_vr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask
- const unsigned32 vr_mask = out_vmask | in_vmask;
+void::model-function::ppc_insn_vr:itable_index index, model_data *model_ptr, const uint32_t out_vmask, const uint32_t in_vmask
+ const uint32_t vr_mask = out_vmask | in_vmask;
model_busy *busy_ptr;
if (model_ptr->vr_busy & vr_mask) {
@@ -174,8 +174,8 @@ void::model-function::ppc_insn_vr:itable_index index, model_data *model_ptr, con
}
# Schedule an AltiVec instruction that takes vector input registers and produces vector output registers, touches CR
-void::model-function::ppc_insn_vr_cr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask, const unsigned32 cr_mask
- const unsigned32 vr_mask = out_vmask | in_vmask;
+void::model-function::ppc_insn_vr_cr:itable_index index, model_data *model_ptr, const uint32_t out_vmask, const uint32_t in_vmask, const uint32_t cr_mask
+ const uint32_t vr_mask = out_vmask | in_vmask;
model_busy *busy_ptr;
if ((model_ptr->vr_busy & vr_mask) || (model_ptr->cr_fpscr_busy & cr_mask)) {
@@ -208,8 +208,8 @@ void::model-function::ppc_insn_vr_cr:itable_index index, model_data *model_ptr,
model_trace_altivec_make_busy(model_ptr, vr_mask, cr_mask);
# Schedule an AltiVec instruction that takes vector input registers and produces vector output registers, touches VSCR
-void::model-function::ppc_insn_vr_vscr:itable_index index, model_data *model_ptr, const unsigned32 out_vmask, const unsigned32 in_vmask
- const unsigned32 vr_mask = out_vmask | in_vmask;
+void::model-function::ppc_insn_vr_vscr:itable_index index, model_data *model_ptr, const uint32_t out_vmask, const uint32_t in_vmask
+ const uint32_t vr_mask = out_vmask | in_vmask;
model_busy *busy_ptr;
if ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) {
@@ -237,7 +237,7 @@ void::model-function::ppc_insn_vr_vscr:itable_index index, model_data *model_ptr
model_trace_altivec_make_busy(model_ptr, vr_mask, 0);
# Schedule an MFVSCR instruction that VSCR input register and produces an AltiVec output register
-void::model-function::ppc_insn_from_vscr:itable_index index, model_data *model_ptr, const unsigned32 vr_mask
+void::model-function::ppc_insn_from_vscr:itable_index index, model_data *model_ptr, const uint32_t vr_mask
model_busy *busy_ptr;
while ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) {
@@ -259,7 +259,7 @@ void::model-function::ppc_insn_from_vscr:itable_index index, model_data *model_p
model_trace_altivec_make_busy(model_ptr, vr_mask, 0);
# Schedule an MTVSCR instruction that one AltiVec input register and produces a vscr output register
-void::model-function::ppc_insn_to_vscr:itable_index index, model_data *model_ptr, const unsigned32 vr_mask
+void::model-function::ppc_insn_to_vscr:itable_index index, model_data *model_ptr, const uint32_t vr_mask
model_busy *busy_ptr;
while ((model_ptr->vr_busy & vr_mask) != 0 || model_ptr->vscr_busy != 0) {
@@ -278,8 +278,8 @@ void::model-function::ppc_insn_to_vscr:itable_index index, model_data *model_ptr
# The follow are AltiVec saturate operations
-signed8::model-function::altivec_signed_saturate_8:signed16 val, int *sat
- signed8 rv;
+int8_t::model-function::altivec_signed_saturate_8:int16_t val, int *sat
+ int8_t rv;
if (val > 127) {
rv = 127;
*sat = 1;
@@ -292,8 +292,8 @@ signed8::model-function::altivec_signed_saturate_8:signed16 val, int *sat
}
return rv;
-signed16::model-function::altivec_signed_saturate_16:signed32 val, int *sat
- signed16 rv;
+int16_t::model-function::altivec_signed_saturate_16:int32_t val, int *sat
+ int16_t rv;
if (val > 32767) {
rv = 32767;
*sat = 1;
@@ -306,8 +306,8 @@ signed16::model-function::altivec_signed_saturate_16:signed32 val, int *sat
}
return rv;
-signed32::model-function::altivec_signed_saturate_32:signed64 val, int *sat
- signed32 rv;
+int32_t::model-function::altivec_signed_saturate_32:int64_t val, int *sat
+ int32_t rv;
if (val > 2147483647) {
rv = 2147483647;
*sat = 1;
@@ -320,8 +320,8 @@ signed32::model-function::altivec_signed_saturate_32:signed64 val, int *sat
}
return rv;
-unsigned8::model-function::altivec_unsigned_saturate_8:signed16 val, int *sat
- unsigned8 rv;
+uint8_t::model-function::altivec_unsigned_saturate_8:int16_t val, int *sat
+ uint8_t rv;
if (val > 255) {
rv = 255;
*sat = 1;
@@ -334,8 +334,8 @@ unsigned8::model-function::altivec_unsigned_saturate_8:signed16 val, int *sat
}
return rv;
-unsigned16::model-function::altivec_unsigned_saturate_16:signed32 val, int *sat
- unsigned16 rv;
+uint16_t::model-function::altivec_unsigned_saturate_16:int32_t val, int *sat
+ uint16_t rv;
if (val > 65535) {
rv = 65535;
*sat = 1;
@@ -348,8 +348,8 @@ unsigned16::model-function::altivec_unsigned_saturate_16:signed32 val, int *sat
}
return rv;
-unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
- unsigned32 rv;
+uint32_t::model-function::altivec_unsigned_saturate_32:int64_t val, int *sat
+ uint32_t rv;
if (val > 4294967295LL) {
rv = 4294967295LL;
*sat = 1;
@@ -573,17 +573,17 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
#
0.4,6.VS,11.VA,16.VB,21.384:VX:av:vaddcuw %VD, %VA, %VB:Vector Add Carryout Unsigned Word
- unsigned64 temp;
+ uint64_t temp;
int i;
for (i = 0; i < 4; i++) {
- temp = (unsigned64)(*vA).w[i] + (unsigned64)(*vB).w[i];
+ temp = (uint64_t)(*vA).w[i] + (uint64_t)(*vB).w[i];
(*vS).w[i] = temp >> 32;
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
0.4,6.VS,11.VA,16.VB,21.10:VX:av:vaddfp %VD, %VA, %VB:Vector Add Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -596,9 +596,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.768:VX:av:vaddsbs %VD, %VA, %VB:Vector Add Signed Byte Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
for (i = 0; i < 16; i++) {
- temp = (signed16)(signed8)(*vA).b[i] + (signed16)(signed8)(*vB).b[i];
+ temp = (int16_t)(int8_t)(*vA).b[i] + (int16_t)(int8_t)(*vB).b[i];
(*vS).b[i] = altivec_signed_saturate_8(temp, &tempsat);
sat |= tempsat;
}
@@ -607,10 +607,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.832:VX:av:vaddshs %VD, %VA, %VB:Vector Add Signed Half Word Saturate
int i, sat, tempsat;
- signed32 temp, a, b;
+ int32_t temp, a, b;
for (i = 0; i < 8; i++) {
- a = (signed32)(signed16)(*vA).h[i];
- b = (signed32)(signed16)(*vB).h[i];
+ a = (int32_t)(int16_t)(*vA).h[i];
+ b = (int32_t)(int16_t)(*vB).h[i];
temp = a + b;
(*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
sat |= tempsat;
@@ -620,9 +620,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.896:VX:av:vaddsws %VD, %VA, %VB:Vector Add Signed Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (i = 0; i < 4; i++) {
- temp = (signed64)(signed32)(*vA).w[i] + (signed64)(signed32)(*vB).w[i];
+ temp = (int64_t)(int32_t)(*vA).w[i] + (int64_t)(int32_t)(*vB).w[i];
(*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -637,10 +637,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.512:VX:av:vaddubs %VD, %VA, %VB:Vector Add Unsigned Byte Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
- temp = (signed16)(unsigned8)(*vA).b[i] + (signed16)(unsigned8)(*vB).b[i];
+ temp = (int16_t)(uint8_t)(*vA).b[i] + (int16_t)(uint8_t)(*vB).b[i];
(*vS).b[i] = altivec_unsigned_saturate_8(temp, &tempsat);
sat |= tempsat;
}
@@ -655,9 +655,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.576:VX:av:vadduhs %VD, %VA, %VB:Vector Add Unsigned Half Word Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
for (i = 0; i < 8; i++) {
- temp = (signed32)(unsigned16)(*vA).h[i] + (signed32)(unsigned16)(*vB).h[i];
+ temp = (int32_t)(uint16_t)(*vA).h[i] + (int32_t)(uint16_t)(*vB).h[i];
(*vS).h[i] = altivec_unsigned_saturate_16(temp, &tempsat);
sat |= tempsat;
}
@@ -672,9 +672,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.640:VX:av:vadduws %VD, %VA, %VB:Vector Add Unsigned Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (i = 0; i < 4; i++) {
- temp = (signed64)(unsigned32)(*vA).w[i] + (signed64)(unsigned32)(*vB).w[i];
+ temp = (int64_t)(uint32_t)(*vA).w[i] + (int64_t)(uint32_t)(*vB).w[i];
(*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -704,10 +704,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1282:VX:av:vavgsb %VD, %VA, %VB:Vector Average Signed Byte
int i;
- signed16 temp, a, b;
+ int16_t temp, a, b;
for (i = 0; i < 16; i++) {
- a = (signed16)(signed8)(*vA).b[i];
- b = (signed16)(signed8)(*vB).b[i];
+ a = (int16_t)(int8_t)(*vA).b[i];
+ b = (int16_t)(int8_t)(*vB).b[i];
temp = a + b + 1;
(*vS).b[i] = (temp >> 1) & 0xff;
}
@@ -715,10 +715,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1346:VX:av:vavgsh %VD, %VA, %VB:Vector Average Signed Half Word
int i;
- signed32 temp, a, b;
+ int32_t temp, a, b;
for (i = 0; i < 8; i++) {
- a = (signed32)(signed16)(*vA).h[i];
- b = (signed32)(signed16)(*vB).h[i];
+ a = (int32_t)(int16_t)(*vA).h[i];
+ b = (int32_t)(int16_t)(*vB).h[i];
temp = a + b + 1;
(*vS).h[i] = (temp >> 1) & 0xffff;
}
@@ -726,10 +726,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1410:VX:av:vavgsw %VD, %VA, %VB:Vector Average Signed Word
int i;
- signed64 temp, a, b;
+ int64_t temp, a, b;
for (i = 0; i < 4; i++) {
- a = (signed64)(signed32)(*vA).w[i];
- b = (signed64)(signed32)(*vB).w[i];
+ a = (int64_t)(int32_t)(*vA).w[i];
+ b = (int64_t)(int32_t)(*vB).w[i];
temp = a + b + 1;
(*vS).w[i] = (temp >> 1) & 0xffffffff;
}
@@ -737,7 +737,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1026:VX:av:vavgub %VD, %VA, %VB:Vector Average Unsigned Byte
int i;
- unsigned16 temp, a, b;
+ uint16_t temp, a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -748,7 +748,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1090:VX:av:vavguh %VD, %VA, %VB:Vector Average Unsigned Half Word
int i;
- unsigned32 temp, a, b;
+ uint32_t temp, a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -759,7 +759,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1154:VX:av:vavguw %VD, %VA, %VB:Vector Average Unsigned Word
int i;
- unsigned64 temp, a, b;
+ uint64_t temp, a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -774,7 +774,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.842:VX:av:vcfsx %VD, %VB, %UIMM:Vector Convert From Signed Fixed-Point Word
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu b, div, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&b, (*vB).w[i]);
@@ -787,7 +787,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.778:VX:av:vcfux %VD, %VA, %UIMM:Vector Convert From Unsigned Fixed-Point Word
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu b, d, div;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&b, (*vB).w[i]);
@@ -896,7 +896,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.774:VXR:av:vcmpgtsbx %VD, %VA, %VB:Vector Compare Greater-Than Signed Byte
int i;
- signed8 a, b;
+ int8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -911,7 +911,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.838:VXR:av:vcmpgtshx %VD, %VA, %VB:Vector Compare Greater-Than Signed Half Word
int i;
- signed16 a, b;
+ int16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -926,7 +926,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.902:VXR:av:vcmpgtswx %VD, %VA, %VB:Vector Compare Greater-Than Signed Word
int i;
- signed32 a, b;
+ int32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -941,7 +941,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.518:VXR:av:vcmpgtubx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Byte
int i;
- unsigned8 a, b;
+ uint8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -956,7 +956,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.582:VXR:av:vcmpgtuhx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Half Word
int i;
- unsigned16 a, b;
+ uint16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -971,7 +971,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.RC,22.646:VXR:av:vcmpgtuwx %VD, %VA, %VB:Vector Compare Greater-Than Unsigned Word
int i;
- unsigned32 a, b;
+ uint32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -990,7 +990,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.970:VX:av:vctsxs %VD, %VB, %UIMM:Vector Convert to Signed Fixed-Point Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
sim_fpu a, b, m;
sat = 0;
for (i = 0; i < 4; i++) {
@@ -1006,7 +1006,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.906:VX:av:vctuxs %VD, %VB, %UIMM:Vector Convert to Unsigned Fixed-Point Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
sim_fpu a, b, m;
sat = 0;
for (i = 0; i < 4; i++) {
@@ -1026,8 +1026,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.394:VX:av:vexptefp %VD, %VB:Vector 2 Raised to the Exponent Estimate Floating Point
int i;
- unsigned32 f;
- signed32 bi;
+ uint32_t f;
+ int32_t bi;
sim_fpu b, d;
for (i = 0; i < 4; i++) {
/*HACK!*/
@@ -1042,7 +1042,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.458:VX:av:vlogefp %VD, %VB:Vector Log2 Estimate Floating Point
int i;
- unsigned32 c, u, f;
+ uint32_t c, u, f;
sim_fpu b, cfpu, d;
for (i = 0; i < 4; i++) {
/*HACK!*/
@@ -1063,7 +1063,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.46:VAX:av:vmaddfp %VD, %VA, %VB, %VC:Vector Multiply Add Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, c, d, e;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -1083,7 +1083,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1034:VX:av:vmaxfp %VD, %VA, %VB:Vector Maximum Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -1096,7 +1096,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.258:VX:av:vmaxsb %VD, %VA, %VB:Vector Maximum Signed Byte
int i;
- signed8 a, b;
+ int8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -1109,7 +1109,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.322:VX:av:vmaxsh %VD, %VA, %VB:Vector Maximum Signed Half Word
int i;
- signed16 a, b;
+ int16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -1122,7 +1122,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.386:VX:av:vmaxsw %VD, %VA, %VB:Vector Maximum Signed Word
int i;
- signed32 a, b;
+ int32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -1135,7 +1135,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.2:VX:av:vmaxub %VD, %VA, %VB:Vector Maximum Unsigned Byte
int i;
- unsigned8 a, b;
+ uint8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -1148,7 +1148,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.66:VX:av:vmaxus %VD, %VA, %VB:Vector Maximum Unsigned Half Word
int i;
- unsigned16 a, b;
+ uint16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -1161,7 +1161,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.130:VX:av:vmaxuw %VD, %VA, %VB:Vector Maximum Unsigned Word
int i;
- unsigned32 a, b;
+ uint32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -1179,13 +1179,13 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.32:VAX:av:vmhaddshs %VD, %VA, %VB, %VC:Vector Multiple High and Add Signed Half Word Saturate
int i, sat, tempsat;
- signed16 a, b;
- signed32 prod, temp, c;
+ int16_t a, b;
+ int32_t prod, temp, c;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
- c = (signed32)(signed16)(*vC).h[i];
- prod = (signed32)a * (signed32)b;
+ c = (int32_t)(int16_t)(*vC).h[i];
+ prod = (int32_t)a * (int32_t)b;
temp = (prod >> 15) + c;
(*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
sat |= tempsat;
@@ -1195,13 +1195,13 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.33:VAX:av:vmhraddshs %VD, %VA, %VB, %VC:Vector Multiple High Round and Add Signed Half Word Saturate
int i, sat, tempsat;
- signed16 a, b;
- signed32 prod, temp, c;
+ int16_t a, b;
+ int32_t prod, temp, c;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
- c = (signed32)(signed16)(*vC).h[i];
- prod = (signed32)a * (signed32)b;
+ c = (int32_t)(int16_t)(*vC).h[i];
+ prod = (int32_t)a * (int32_t)b;
prod += 0x4000;
temp = (prod >> 15) + c;
(*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
@@ -1217,7 +1217,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1098:VX:av:vminfp %VD, %VA, %VB:Vector Minimum Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -1230,7 +1230,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.770:VX:av:vminsb %VD, %VA, %VB:Vector Minimum Signed Byte
int i;
- signed8 a, b;
+ int8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -1243,7 +1243,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.834:VX:av:vminsh %VD, %VA, %VB:Vector Minimum Signed Half Word
int i;
- signed16 a, b;
+ int16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -1256,7 +1256,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.898:VX:av:vminsw %VD, %VA, %VB:Vector Minimum Signed Word
int i;
- signed32 a, b;
+ int32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -1269,7 +1269,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.514:VX:av:vminub %VD, %VA, %VB:Vector Minimum Unsigned Byte
int i;
- unsigned8 a, b;
+ uint8_t a, b;
for (i = 0; i < 16; i++) {
a = (*vA).b[i];
b = (*vB).b[i];
@@ -1282,7 +1282,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.578:VX:av:vminuh %VD, %VA, %VB:Vector Minimum Unsigned Half Word
int i;
- unsigned16 a, b;
+ uint16_t a, b;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
@@ -1295,7 +1295,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.642:VX:av:vminuw %VD, %VA, %VB:Vector Minimum Unsigned Word
int i;
- unsigned32 a, b;
+ uint32_t a, b;
for (i = 0; i < 4; i++) {
a = (*vA).w[i];
b = (*vB).w[i];
@@ -1313,13 +1313,13 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.34:VAX:av:vmladduhm %VD, %VA, %VB, %VC:Vector Multiply Low and Add Unsigned Half Word Modulo
int i;
- unsigned16 a, b, c;
- unsigned32 prod;
+ uint16_t a, b, c;
+ uint32_t prod;
for (i = 0; i < 8; i++) {
a = (*vA).h[i];
b = (*vB).h[i];
c = (*vC).h[i];
- prod = (unsigned32)a * (unsigned32)b;
+ prod = (uint32_t)a * (uint32_t)b;
(*vS).h[i] = (prod + c) & 0xffff;
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK);
@@ -1384,16 +1384,16 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.37:VAX:av:vmsummbm %VD, %VA, %VB, %VC:Vector Multiply Sum Mixed-Sign Byte Modulo
int i, j;
- signed32 temp;
- signed16 prod, a;
- unsigned16 b;
+ int32_t temp;
+ int16_t prod, a;
+ uint16_t b;
for (i = 0; i < 4; i++) {
temp = (*vC).w[i];
for (j = 0; j < 4; j++) {
- a = (signed16)(signed8)(*vA).b[i*4+j];
+ a = (int16_t)(int8_t)(*vA).b[i*4+j];
b = (*vB).b[i*4+j];
prod = a * b;
- temp += (signed32)prod;
+ temp += (int32_t)prod;
}
(*vS).w[i] = temp;
}
@@ -1401,12 +1401,12 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.40:VAX:av:vmsumshm %VD, %VA, %VB, %VC:Vector Multiply Sum Signed Half Word Modulo
int i, j;
- signed32 temp, prod, a, b;
+ int32_t temp, prod, a, b;
for (i = 0; i < 4; i++) {
temp = (*vC).w[i];
for (j = 0; j < 2; j++) {
- a = (signed32)(signed16)(*vA).h[i*2+j];
- b = (signed32)(signed16)(*vB).h[i*2+j];
+ a = (int32_t)(int16_t)(*vA).h[i*2+j];
+ b = (int32_t)(int16_t)(*vB).h[i*2+j];
prod = a * b;
temp += prod;
}
@@ -1416,16 +1416,16 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.41:VAX:av:vmsumshs %VD, %VA, %VB, %VC:Vector Multiply Sum Signed Half Word Saturate
int i, j, sat, tempsat;
- signed64 temp;
- signed32 prod, a, b;
+ int64_t temp;
+ int32_t prod, a, b;
sat = 0;
for (i = 0; i < 4; i++) {
- temp = (signed64)(signed32)(*vC).w[i];
+ temp = (int64_t)(int32_t)(*vC).w[i];
for (j = 0; j < 2; j++) {
- a = (signed32)(signed16)(*vA).h[i*2+j];
- b = (signed32)(signed16)(*vB).h[i*2+j];
+ a = (int32_t)(int16_t)(*vA).h[i*2+j];
+ b = (int32_t)(int16_t)(*vB).h[i*2+j];
prod = a * b;
- temp += (signed64)prod;
+ temp += (int64_t)prod;
}
(*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
@@ -1435,8 +1435,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.36:VAX:av:vmsumubm %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Byte Modulo
int i, j;
- unsigned32 temp;
- unsigned16 prod, a, b;
+ uint32_t temp;
+ uint16_t prod, a, b;
for (i = 0; i < 4; i++) {
temp = (*vC).w[i];
for (j = 0; j < 4; j++) {
@@ -1451,7 +1451,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.38:VAX:av:vmsumuhm %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Half Word Modulo
int i, j;
- unsigned32 temp, prod, a, b;
+ uint32_t temp, prod, a, b;
for (i = 0; i < 4; i++) {
temp = (*vC).w[i];
for (j = 0; j < 2; j++) {
@@ -1466,7 +1466,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.39:VAX:av:vmsumuhs %VD, %VA, %VB, %VC:Vector Multiply Sum Unsigned Half Word Saturate
int i, j, sat, tempsat;
- unsigned32 temp, prod, a, b;
+ uint32_t temp, prod, a, b;
sat = 0;
for (i = 0; i < 4; i++) {
temp = (*vC).w[i];
@@ -1489,8 +1489,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.776:VX:av:vmulesb %VD, %VA, %VB:Vector Multiply Even Signed Byte
int i;
- signed8 a, b;
- signed16 prod;
+ int8_t a, b;
+ int16_t prod;
for (i = 0; i < 8; i++) {
a = (*vA).b[AV_BINDEX(i*2)];
b = (*vB).b[AV_BINDEX(i*2)];
@@ -1501,8 +1501,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.840:VX:av:vmulesh %VD, %VA, %VB:Vector Multiply Even Signed Half Word
int i;
- signed16 a, b;
- signed32 prod;
+ int16_t a, b;
+ int32_t prod;
for (i = 0; i < 4; i++) {
a = (*vA).h[AV_HINDEX(i*2)];
b = (*vB).h[AV_HINDEX(i*2)];
@@ -1513,8 +1513,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.520:VX:av:vmuleub %VD, %VA, %VB:Vector Multiply Even Unsigned Byte
int i;
- unsigned8 a, b;
- unsigned16 prod;
+ uint8_t a, b;
+ uint16_t prod;
for (i = 0; i < 8; i++) {
a = (*vA).b[AV_BINDEX(i*2)];
b = (*vB).b[AV_BINDEX(i*2)];
@@ -1525,8 +1525,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.584:VX:av:vmuleuh %VD, %VA, %VB:Vector Multiply Even Unsigned Half Word
int i;
- unsigned16 a, b;
- unsigned32 prod;
+ uint16_t a, b;
+ uint32_t prod;
for (i = 0; i < 4; i++) {
a = (*vA).h[AV_HINDEX(i*2)];
b = (*vB).h[AV_HINDEX(i*2)];
@@ -1537,8 +1537,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.264:VX:av:vmulosb %VD, %VA, %VB:Vector Multiply Odd Signed Byte
int i;
- signed8 a, b;
- signed16 prod;
+ int8_t a, b;
+ int16_t prod;
for (i = 0; i < 8; i++) {
a = (*vA).b[AV_BINDEX((i*2)+1)];
b = (*vB).b[AV_BINDEX((i*2)+1)];
@@ -1549,8 +1549,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.328:VX:av:vmulosh %VD, %VA, %VB:Vector Multiply Odd Signed Half Word
int i;
- signed16 a, b;
- signed32 prod;
+ int16_t a, b;
+ int32_t prod;
for (i = 0; i < 4; i++) {
a = (*vA).h[AV_HINDEX((i*2)+1)];
b = (*vB).h[AV_HINDEX((i*2)+1)];
@@ -1561,8 +1561,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.8:VX:av:vmuloub %VD, %VA, %VB:Vector Multiply Odd Unsigned Byte
int i;
- unsigned8 a, b;
- unsigned16 prod;
+ uint8_t a, b;
+ uint16_t prod;
for (i = 0; i < 8; i++) {
a = (*vA).b[AV_BINDEX((i*2)+1)];
b = (*vB).b[AV_BINDEX((i*2)+1)];
@@ -1573,8 +1573,8 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.72:VX:av:vmulouh %VD, %VA, %VB:Vector Multiply Odd Unsigned Half Word
int i;
- unsigned16 a, b;
- unsigned32 prod;
+ uint16_t a, b;
+ uint32_t prod;
for (i = 0; i < 4; i++) {
a = (*vA).h[AV_HINDEX((i*2)+1)];
b = (*vB).h[AV_HINDEX((i*2)+1)];
@@ -1590,7 +1590,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.47:VX:av:vnmsubfp %VD, %VA, %VB, %VC:Vector Negative Multiply-Subtract Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, c, d, i1, i2;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -1667,7 +1667,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.398:VX:av:vpkshss %VD, %VA, %VB:Vector Pack Signed Half Word Signed Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
if (i < 8)
@@ -1682,7 +1682,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.270:VX:av:vpkshus %VD, %VA, %VB:Vector Pack Signed Half Word Unsigned Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
if (i < 8)
@@ -1697,7 +1697,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.462:VX:av:vpkswss %VD, %VA, %VB:Vector Pack Signed Word Signed Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
sat = 0;
for (i = 0; i < 8; i++) {
if (i < 4)
@@ -1712,7 +1712,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.334:VX:av:vpkswus %VD, %VA, %VB:Vector Pack Signed Word Unsigned Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
sat = 0;
for (i = 0; i < 8; i++) {
if (i < 4)
@@ -1736,14 +1736,14 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.142:VX:av:vpkuhus %VD, %VA, %VB:Vector Pack Unsigned Half Word Unsigned Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
if (i < 8)
temp = (*vA).h[AV_HINDEX(i)];
else
temp = (*vB).h[AV_HINDEX(i-8)];
- /* force positive in signed16, ok as we'll toss the bit away anyway */
+ /* force positive in int16_t, ok as we'll toss the bit away anyway */
temp &= ~0x8000;
(*vS).b[AV_BINDEX(i)] = altivec_unsigned_saturate_8(temp, &tempsat);
sat |= tempsat;
@@ -1762,14 +1762,14 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.206:VX:av:vpkuwus %VD, %VA, %VB:Vector Pack Unsigned Word Unsigned Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
sat = 0;
for (i = 0; i < 8; i++) {
if (i < 4)
temp = (*vA).w[i];
else
temp = (*vB).w[i-4];
- /* force positive in signed32, ok as we'll toss the bit away anyway */
+ /* force positive in int32_t, ok as we'll toss the bit away anyway */
temp &= ~0x80000000;
(*vS).h[AV_HINDEX(i)] = altivec_unsigned_saturate_16(temp, &tempsat);
sat |= tempsat;
@@ -1784,7 +1784,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.266:VX:av:vrefp %VD, %VB:Vector Reciprocal Estimate Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1796,7 +1796,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.330:VX:av:vrsqrtefp %VD, %VB:Vector Reciprocal Square Root Estimate Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op, i1, one, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1814,7 +1814,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.714:VX:av:vrfim %VD, %VB:Vector Round to Floating-Point Integer towards Minus Infinity
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1826,7 +1826,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.522:VX:av:vrfin %VD, %VB:Vector Round to Floating-Point Integer Nearest
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1838,7 +1838,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.650:VX:av:vrfip %VD, %VB:Vector Round to Floating-Point Integer towards Plus Infinity
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1850,7 +1850,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.586:VX:av:vrfiz %VD, %VB:Vector Round to Floating-Point Integer towards Zero
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu op;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&op, (*vB).w[i]);
@@ -1867,27 +1867,27 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.4:VX:av:vrlb %VD, %VA, %VB:Vector Rotate Left Integer Byte
int i;
- unsigned16 temp;
+ uint16_t temp;
for (i = 0; i < 16; i++) {
- temp = (unsigned16)(*vA).b[i] << (((*vB).b[i]) & 7);
+ temp = (uint16_t)(*vA).b[i] << (((*vB).b[i]) & 7);
(*vS).b[i] = (temp & 0xff) | ((temp >> 8) & 0xff);
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
0.4,6.VS,11.VA,16.VB,21.68:VX:av:vrlh %VD, %VA, %VB:Vector Rotate Left Integer Half Word
int i;
- unsigned32 temp;
+ uint32_t temp;
for (i = 0; i < 8; i++) {
- temp = (unsigned32)(*vA).h[i] << (((*vB).h[i]) & 0xf);
+ temp = (uint32_t)(*vA).h[i] << (((*vB).h[i]) & 0xf);
(*vS).h[i] = (temp & 0xffff) | ((temp >> 16) & 0xffff);
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
0.4,6.VS,11.VA,16.VB,21.132:VX:av:vrlw %VD, %VA, %VB:Vector Rotate Left Integer Word
int i;
- unsigned64 temp;
+ uint64_t temp;
for (i = 0; i < 4; i++) {
- temp = (unsigned64)(*vA).w[i] << (((*vB).w[i]) & 0x1f);
+ temp = (uint64_t)(*vA).w[i] << (((*vB).w[i]) & 0x1f);
(*vS).w[i] = (temp & 0xffffffff) | ((temp >> 32) & 0xffffffff);
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
@@ -1899,7 +1899,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.VC,26.42:VAX:av:vsel %VD, %VA, %VB, %VC:Vector Conditional Select
int i;
- unsigned32 c;
+ uint32_t c;
for (i = 0; i < 4; i++) {
c = (*vC).w[i];
(*vS).w[i] = ((*vB).w[i] & c) | ((*vA).w[i] & ~c);
@@ -1978,7 +1978,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.524:VX:av:vspltb %VD, %VB, %UIMM:Vector Splat Byte
int i;
- unsigned8 b;
+ uint8_t b;
b = (*vB).b[AV_BINDEX(UIMM & 0xf)];
for (i = 0; i < 16; i++)
(*vS).b[i] = b;
@@ -1986,7 +1986,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.588:VX:av:vsplth %VD, %VB, %UIMM:Vector Splat Half Word
int i;
- unsigned16 h;
+ uint16_t h;
h = (*vB).h[AV_HINDEX(UIMM & 0x7)];
for (i = 0; i < 8; i++)
(*vS).h[i] = h;
@@ -1994,7 +1994,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.SIMM,16.0,21.780:VX:av:vspltisb %VD, %SIMM:Vector Splat Immediate Signed Byte
int i;
- signed8 b = SIMM;
+ int8_t b = SIMM;
/* manual 5-bit signed extension */
if (b & 0x10)
b -= 0x20;
@@ -2004,7 +2004,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.SIMM,16.0,21.844:VX:av:vspltish %VD, %SIMM:Vector Splat Immediate Signed Half Word
int i;
- signed16 h = SIMM;
+ int16_t h = SIMM;
/* manual 5-bit signed extension */
if (h & 0x10)
h -= 0x20;
@@ -2014,7 +2014,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.SIMM,16.0,21.908:VX:av:vspltisw %VD, %SIMM:Vector Splat Immediate Signed Word
int i;
- signed32 w = SIMM;
+ int32_t w = SIMM;
/* manual 5-bit signed extension */
if (w & 0x10)
w -= 0x20;
@@ -2024,7 +2024,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.UIMM,16.VB,21.652:VX:av:vspltw %VD, %VB, %UIMM:Vector Splat Word
int i;
- unsigned32 w;
+ uint32_t w;
w = (*vB).w[UIMM & 0x3];
for (i = 0; i < 4; i++)
(*vS).w[i] = w;
@@ -2052,30 +2052,30 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.772:VX:av:vsrab %VD, %VA, %VB:Vector Shift Right Algebraic Byte
int i, sh;
- signed16 a;
+ int16_t a;
for (i = 0; i < 16; i++) {
sh = ((*vB).b[i]) & 7;
- a = (signed16)(signed8)(*vA).b[i];
+ a = (int16_t)(int8_t)(*vA).b[i];
(*vS).b[i] = (a >> sh) & 0xff;
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
0.4,6.VS,11.VA,16.VB,21.836:VX:av:vsrah %VD, %VA, %VB:Vector Shift Right Algebraic Half Word
int i, sh;
- signed32 a;
+ int32_t a;
for (i = 0; i < 8; i++) {
sh = ((*vB).h[i]) & 0xf;
- a = (signed32)(signed16)(*vA).h[i];
+ a = (int32_t)(int16_t)(*vA).h[i];
(*vS).h[i] = (a >> sh) & 0xffff;
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
0.4,6.VS,11.VA,16.VB,21.900:VX:av:vsraw %VD, %VA, %VB:Vector Shift Right Algebraic Word
int i, sh;
- signed64 a;
+ int64_t a;
for (i = 0; i < 4; i++) {
sh = ((*vB).w[i]) & 0xf;
- a = (signed64)(signed32)(*vA).w[i];
+ a = (int64_t)(int32_t)(*vA).w[i];
(*vS).w[i] = (a >> sh) & 0xffffffff;
}
PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK);
@@ -2125,10 +2125,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1408:VX:av:vsubcuw %VD, %VA, %VB:Vector Subtract Carryout Unsigned Word
int i;
- signed64 temp, a, b;
+ int64_t temp, a, b;
for (i = 0; i < 4; i++) {
- a = (signed64)(unsigned32)(*vA).w[i];
- b = (signed64)(unsigned32)(*vB).w[i];
+ a = (int64_t)(uint32_t)(*vA).w[i];
+ b = (int64_t)(uint32_t)(*vB).w[i];
temp = a - b;
(*vS).w[i] = ~(temp >> 32) & 1;
}
@@ -2136,7 +2136,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.74:VX:av:vsubfp %VD, %VA, %VB:Vector Subtract Floating Point
int i;
- unsigned32 f;
+ uint32_t f;
sim_fpu a, b, d;
for (i = 0; i < 4; i++) {
sim_fpu_32to (&a, (*vA).w[i]);
@@ -2149,10 +2149,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1792:VX:av:vsubsbs %VD, %VA, %VB:Vector Subtract Signed Byte Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
- temp = (signed16)(signed8)(*vA).b[i] - (signed16)(signed8)(*vB).b[i];
+ temp = (int16_t)(int8_t)(*vA).b[i] - (int16_t)(int8_t)(*vB).b[i];
(*vS).b[i] = altivec_signed_saturate_8(temp, &tempsat);
sat |= tempsat;
}
@@ -2161,10 +2161,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1856:VX:av:vsubshs %VD, %VA, %VB:Vector Subtract Signed Half Word Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
sat = 0;
for (i = 0; i < 8; i++) {
- temp = (signed32)(signed16)(*vA).h[i] - (signed32)(signed16)(*vB).h[i];
+ temp = (int32_t)(int16_t)(*vA).h[i] - (int32_t)(int16_t)(*vB).h[i];
(*vS).h[i] = altivec_signed_saturate_16(temp, &tempsat);
sat |= tempsat;
}
@@ -2173,10 +2173,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1920:VX:av:vsubsws %VD, %VA, %VB:Vector Subtract Signed Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
sat = 0;
for (i = 0; i < 4; i++) {
- temp = (signed64)(signed32)(*vA).w[i] - (signed64)(signed32)(*vB).w[i];
+ temp = (int64_t)(int32_t)(*vA).w[i] - (int64_t)(int32_t)(*vB).w[i];
(*vS).w[i] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -2191,10 +2191,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1536:VX:av:vsububs %VD, %VA, %VB:Vector Subtract Unsigned Byte Saturate
int i, sat, tempsat;
- signed16 temp;
+ int16_t temp;
sat = 0;
for (i = 0; i < 16; i++) {
- temp = (signed16)(unsigned8)(*vA).b[i] - (signed16)(unsigned8)(*vB).b[i];
+ temp = (int16_t)(uint8_t)(*vA).b[i] - (int16_t)(uint8_t)(*vB).b[i];
(*vS).b[i] = altivec_unsigned_saturate_8(temp, &tempsat);
sat |= tempsat;
}
@@ -2209,9 +2209,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1600:VX:av:vsubuhs %VD, %VA, %VB:Vector Subtract Unsigned Half Word Saturate
int i, sat, tempsat;
- signed32 temp;
+ int32_t temp;
for (i = 0; i < 8; i++) {
- temp = (signed32)(unsigned16)(*vA).h[i] - (signed32)(unsigned16)(*vB).h[i];
+ temp = (int32_t)(uint16_t)(*vA).h[i] - (int32_t)(uint16_t)(*vB).h[i];
(*vS).h[i] = altivec_unsigned_saturate_16(temp, &tempsat);
sat |= tempsat;
}
@@ -2226,9 +2226,9 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1664:VX:av:vsubuws %VD, %VA, %VB:Vector Subtract Unsigned Word Saturate
int i, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (i = 0; i < 4; i++) {
- temp = (signed64)(unsigned32)(*vA).w[i] - (signed64)(unsigned32)(*vB).w[i];
+ temp = (int64_t)(uint32_t)(*vA).w[i] - (int64_t)(uint32_t)(*vB).w[i];
(*vS).w[i] = altivec_unsigned_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -2242,10 +2242,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1928:VX:av:vsumsws %VD, %VA, %VB:Vector Sum Across Signed Word Saturate
int i, sat;
- signed64 temp;
- temp = (signed64)(signed32)(*vB).w[3];
+ int64_t temp;
+ temp = (int64_t)(int32_t)(*vB).w[3];
for (i = 0; i < 4; i++)
- temp += (signed64)(signed32)(*vA).w[i];
+ temp += (int64_t)(int32_t)(*vA).w[i];
(*vS).w[3] = altivec_signed_saturate_32(temp, &sat);
(*vS).w[0] = (*vS).w[1] = (*vS).w[2] = 0;
ALTIVEC_SET_SAT(sat);
@@ -2253,10 +2253,10 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1672:VX:av:vsum2sws %VD, %VA, %VB:Vector Sum Across Partial (1/2) Signed Word Saturate
int i, j, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (j = 0; j < 4; j += 2) {
- temp = (signed64)(signed32)(*vB).w[j+1];
- temp += (signed64)(signed32)(*vA).w[j] + (signed64)(signed32)(*vA).w[j+1];
+ temp = (int64_t)(int32_t)(*vB).w[j+1];
+ temp += (int64_t)(int32_t)(*vA).w[j] + (int64_t)(int32_t)(*vA).w[j+1];
(*vS).w[j+1] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -2266,11 +2266,11 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1800:VX:av:vsum4sbs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Signed Byte Saturate
int i, j, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (j = 0; j < 4; j++) {
- temp = (signed64)(signed32)(*vB).w[j];
+ temp = (int64_t)(int32_t)(*vB).w[j];
for (i = 0; i < 4; i++)
- temp += (signed64)(signed8)(*vA).b[i+(j*4)];
+ temp += (int64_t)(int8_t)(*vA).b[i+(j*4)];
(*vS).w[j] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -2279,11 +2279,11 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1608:VX:av:vsum4shs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Signed Half Word Saturate
int i, j, sat, tempsat;
- signed64 temp;
+ int64_t temp;
for (j = 0; j < 4; j++) {
- temp = (signed64)(signed32)(*vB).w[j];
+ temp = (int64_t)(int32_t)(*vB).w[j];
for (i = 0; i < 2; i++)
- temp += (signed64)(signed16)(*vA).h[i+(j*2)];
+ temp += (int64_t)(int16_t)(*vA).h[i+(j*2)];
(*vS).w[j] = altivec_signed_saturate_32(temp, &tempsat);
sat |= tempsat;
}
@@ -2292,12 +2292,12 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.VA,16.VB,21.1544:VX:av:vsum4ubs %VD, %VA, %VB:Vector Sum Across Partial (1/4) Unsigned Byte Saturate
int i, j, sat, tempsat;
- signed64 utemp;
- signed64 temp;
+ int64_t utemp;
+ int64_t temp;
for (j = 0; j < 4; j++) {
- utemp = (signed64)(unsigned32)(*vB).w[j];
+ utemp = (int64_t)(uint32_t)(*vB).w[j];
for (i = 0; i < 4; i++)
- utemp += (signed64)(unsigned16)(*vA).b[i+(j*4)];
+ utemp += (int64_t)(uint16_t)(*vA).b[i+(j*4)];
temp = utemp;
(*vS).w[j] = altivec_unsigned_saturate_32(temp, &tempsat);
sat |= tempsat;
@@ -2312,7 +2312,7 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.846:VX:av:vupkhpx %VD, %VB:Vector Unpack High Pixel16
int i;
- unsigned16 h;
+ uint16_t h;
for (i = 0; i < 4; i++) {
h = (*vB).h[AV_HINDEX(i)];
(*vS).w[i] = ((h & 0x8000) ? 0xff000000 : 0)
@@ -2325,18 +2325,18 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.526:VX:av:vupkhsb %VD, %VB:Vector Unpack High Signed Byte
int i;
for (i = 0; i < 8; i++)
- (*vS).h[AV_HINDEX(i)] = (signed16)(signed8)(*vB).b[AV_BINDEX(i)];
+ (*vS).h[AV_HINDEX(i)] = (int16_t)(int8_t)(*vB).b[AV_BINDEX(i)];
PPC_INSN_VR(VS_BITMASK, VB_BITMASK);
0.4,6.VS,11.0,16.VB,21.590:VX:av:vupkhsh %VD, %VB:Vector Unpack High Signed Half Word
int i;
for (i = 0; i < 4; i++)
- (*vS).w[i] = (signed32)(signed16)(*vB).h[AV_HINDEX(i)];
+ (*vS).w[i] = (int32_t)(int16_t)(*vB).h[AV_HINDEX(i)];
PPC_INSN_VR(VS_BITMASK, VB_BITMASK);
0.4,6.VS,11.0,16.VB,21.974:VX:av:vupklpx %VD, %VB:Vector Unpack Low Pixel16
int i;
- unsigned16 h;
+ uint16_t h;
for (i = 0; i < 4; i++) {
h = (*vB).h[AV_HINDEX(i + 4)];
(*vS).w[i] = ((h & 0x8000) ? 0xff000000 : 0)
@@ -2349,11 +2349,11 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat
0.4,6.VS,11.0,16.VB,21.654:VX:av:vupklsb %VD, %VB:Vector Unpack Low Signed Byte
int i;
for (i = 0; i < 8; i++)
- (*vS).h[AV_HINDEX(i)] = (signed16)(signed8)(*vB).b[AV_BINDEX(i + 8)];
+ (*vS).h[AV_HINDEX(i)] = (int16_t)(int8_t)(*vB).b[AV_BINDEX(i + 8)];
PPC_INSN_VR(VS_BITMASK, VB_BITMASK);
0.4,6.VS,11.0,16.VB,21.718:VX:av:vupklsh %VD, %VB:Vector Unpack Low Signed Half Word
int i;
for (i = 0; i < 4; i++)
- (*vS).w[i] = (signed32)(signed16)(*vB).h[AV_HINDEX(i + 4)];
+ (*vS).w[i] = (int32_t)(int16_t)(*vB).h[AV_HINDEX(i + 4)];
PPC_INSN_VR(VS_BITMASK, VB_BITMASK);
diff --git a/sim/ppc/altivec_registers.h b/sim/ppc/altivec_registers.h
index 33480ed4fa4b..8e6a2db8ecc8 100644
--- a/sim/ppc/altivec_registers.h
+++ b/sim/ppc/altivec_registers.h
@@ -24,12 +24,12 @@
entities. */
typedef union
{
- unsigned8 b[16];
- unsigned16 h[8];
- unsigned32 w[4];
+ uint8_t b[16];
+ uint16_t h[8];
+ uint32_t w[4];
} vreg;
-typedef unsigned32 vscreg;
+typedef uint32_t vscreg;
struct altivec_regs {
/* AltiVec Registers */
diff --git a/sim/ppc/bits.c b/sim/ppc/bits.c
index 767f196fad58..bf2f8f0d6e90 100644
--- a/sim/ppc/bits.c
+++ b/sim/ppc/bits.c
@@ -24,8 +24,8 @@
#include "basics.h"
INLINE_BITS\
-(unsigned64)
-LSMASKED64 (unsigned64 word,
+(uint64_t)
+LSMASKED64 (uint64_t word,
int start,
int stop)
{
@@ -34,8 +34,8 @@ LSMASKED64 (unsigned64 word,
}
INLINE_BITS\
-(unsigned64)
-LSEXTRACTED64 (unsigned64 val,
+(uint64_t)
+LSEXTRACTED64 (uint64_t val,
int start,
int stop)
{
@@ -45,8 +45,8 @@ LSEXTRACTED64 (unsigned64 val,
}
INLINE_BITS\
-(unsigned32)
-MASKED32(unsigned32 word,
+(uint32_t)
+MASKED32(uint32_t word,
unsigned start,
unsigned stop)
{
@@ -54,8 +54,8 @@ MASKED32(unsigned32 word,
}
INLINE_BITS\
-(unsigned64)
-MASKED64(unsigned64 word,
+(uint64_t)
+MASKED64(uint64_t word,
unsigned start,
unsigned stop)
{
@@ -112,8 +112,8 @@ INSERTED(unsigned_word word,
INLINE_BITS\
-(unsigned32)
-ROTL32(unsigned32 val,
+(uint32_t)
+ROTL32(uint32_t val,
long shift)
{
ASSERT(shift >= 0 && shift <= 32);
@@ -122,8 +122,8 @@ ROTL32(unsigned32 val,
INLINE_BITS\
-(unsigned64)
-ROTL64(unsigned64 val,
+(uint64_t)
+ROTL64(uint64_t val,
long shift)
{
ASSERT(shift >= 0 && shift <= 64);
diff --git a/sim/ppc/bits.h b/sim/ppc/bits.h
index d3b765addb50..d08f8d59e646 100644
--- a/sim/ppc/bits.h
+++ b/sim/ppc/bits.h
@@ -108,7 +108,7 @@
/* multi bit mask */
#define _MASKn(WIDTH, START, STOP) \
-(((((unsigned##WIDTH)0) - 1) \
+(((((uint##WIDTH##_t)0) - 1) \
>> (WIDTH - ((STOP) - (START) + 1))) \
<< (WIDTH - 1 - (STOP)))
@@ -151,14 +151,14 @@
/* mask the required bits, leaving them in place */
INLINE_BITS\
-(unsigned32) MASKED32
-(unsigned32 word,
+(uint32_t) MASKED32
+(uint32_t word,
unsigned start,
unsigned stop);
INLINE_BITS\
-(unsigned64) MASKED64
-(unsigned64 word,
+(uint64_t) MASKED64
+(uint64_t word,
unsigned start,
unsigned stop);
@@ -169,8 +169,8 @@ INLINE_BITS\
unsigned stop);
INLINE_BITS\
-(unsigned64) LSMASKED64
-(unsigned64 word,
+(uint64_t) LSMASKED64
+(uint64_t word,
int first,
int last);
@@ -191,8 +191,8 @@ INLINE_BITS\
unsigned stop);
INLINE_BITS\
-(unsigned64) LSEXTRACTED64
-(unsigned64 val,
+(uint64_t) LSEXTRACTED64
+(uint64_t val,
int start,
int stop);
@@ -200,10 +200,10 @@ INLINE_BITS\
/* NB: the wierdness (N>O?N-O:0) is to stop a warning from GCC */
#define _SHUFFLEDn(N, WORD, OLD, NEW) \
((OLD) < (NEW) \
- ? (((unsigned##N)(WORD) \
+ ? (((uint##N##_t)(WORD) \
>> (((NEW) > (OLD)) ? ((NEW) - (OLD)) : 0)) \
& MASK32((NEW), (NEW))) \
- : (((unsigned##N)(WORD) \
+ : (((uint##N##_t)(WORD) \
<< (((OLD) > (NEW)) ? ((OLD) - (NEW)) : 0)) \
& MASK32((NEW), (NEW))))
@@ -229,7 +229,7 @@ INLINE_BITS\
/* depending on MODE return a 64bit or 32bit (sign extended) value */
#if (WITH_TARGET_WORD_BITSIZE == 64)
-#define EXTENDED(X) ((signed64)(signed32)(X))
+#define EXTENDED(X) ((int64_t)(int32_t)(X))
#else
#define EXTENDED(X) (X)
#endif
@@ -270,13 +270,13 @@ do { \
(((VAL) << (SHIFT)) | ((VAL) >> ((N)-(SHIFT))))
INLINE_BITS\
-(unsigned32) ROTL32
-(unsigned32 val,
+(uint32_t) ROTL32
+(uint32_t val,
long shift);
INLINE_BITS\
-(unsigned64) ROTL64
-(unsigned64 val,
+(uint64_t) ROTL64
+(uint64_t val,
long shift);
diff --git a/sim/ppc/corefile.c b/sim/ppc/corefile.c
index ac8aa5d7e22f..1b3eeef8b53c 100644
--- a/sim/ppc/corefile.c
+++ b/sim/ppc/corefile.c
@@ -227,7 +227,7 @@ core_attach(core *memory,
if (attach == attach_raw_memory) {
/* Padd out the raw buffer to ensure that ADDR starts on a
correctly aligned boundary */
- int padding = (addr % sizeof (unsigned64));
+ int padding = (addr % sizeof (uint64_t));
free_buffer = zalloc(nr_bytes + padding);
buffer = (char*)free_buffer + padding;
}
diff --git a/sim/ppc/cpu.c b/sim/ppc/cpu.c
index 1462766e5fe4..b89be03648b9 100644
--- a/sim/ppc/cpu.c
+++ b/sim/ppc/cpu.c
@@ -68,8 +68,8 @@ struct _cpu {
memory_reservation reservation;
/* offset from event time to this cpu's idea of the local time */
- signed64 time_base_local_time;
- signed64 decrementer_local_time;
+ int64_t time_base_local_time;
+ int64_t decrementer_local_time;
event_entry_tag decrementer_event;
};
@@ -229,7 +229,7 @@ cpu_error(cpu *processor,
/* The processors local concept of time */
INLINE_CPU\
-(signed64)
+(int64_t)
cpu_get_time_base(cpu *processor)
{
return (event_queue_time(processor->events)
@@ -239,14 +239,14 @@ cpu_get_time_base(cpu *processor)
INLINE_CPU\
(void)
cpu_set_time_base(cpu *processor,
- signed64 time_base)
+ int64_t time_base)
{
processor->time_base_local_time = (event_queue_time(processor->events)
- time_base);
}
INLINE_CPU\
-(signed32)
+(int32_t)
cpu_get_decrementer(cpu *processor)
{
return (processor->decrementer_local_time
@@ -265,9 +265,9 @@ cpu_decrement_event(void *data)
INLINE_CPU\
(void)
cpu_set_decrementer(cpu *processor,
- signed32 decrementer)
+ int32_t decrementer)
{
- signed64 old_decrementer = cpu_get_decrementer(processor);
+ int64_t old_decrementer = cpu_get_decrementer(processor);
event_queue_deschedule(processor->events, processor->decrementer_event);
processor->decrementer_event = NULL;
processor->decrementer_local_time = (event_queue_time(processor->events)
diff --git a/sim/ppc/cpu.h b/sim/ppc/cpu.h
index 7dc6074b9c6c..c7a087112710 100644
--- a/sim/ppc/cpu.h
+++ b/sim/ppc/cpu.h
@@ -120,22 +120,22 @@ EXTERN_CPU\
/* The processors local concept of time */
INLINE_CPU\
-(signed64) cpu_get_time_base
+(int64_t) cpu_get_time_base
(cpu *processor);
INLINE_CPU\
(void) cpu_set_time_base
(cpu *processor,
- signed64 time_base);
+ int64_t time_base);
INLINE_CPU\
-(signed32) cpu_get_decrementer
+(int32_t) cpu_get_decrementer
(cpu *processor);
INLINE_CPU\
(void) cpu_set_decrementer
(cpu *processor,
- signed32 decrementer);
+ int32_t decrementer);
#if WITH_IDECODE_CACHE_SIZE
diff --git a/sim/ppc/device.c b/sim/ppc/device.c
index 47fa7518f7e8..4537e89b38dc 100644
--- a/sim/ppc/device.c
+++ b/sim/ppc/device.c
@@ -989,7 +989,7 @@ device_add_boolean_property(device *me,
const char *property,
int boolean)
{
- signed32 new_boolean = (boolean ? -1 : 0);
+ int32_t new_boolean = (boolean ? -1 : 0);
device_add_property(me, property, boolean_property,
&new_boolean, sizeof(new_boolean),
&new_boolean, sizeof(new_boolean),
@@ -1879,7 +1879,7 @@ device_instance_to_external(device_instance *instance)
INLINE_DEVICE\
(event_entry_tag)
device_event_queue_schedule(device *me,
- signed64 delta_time,
+ int64_t delta_time,
device_event_handler *handler,
void *data)
{
@@ -1899,7 +1899,7 @@ device_event_queue_deschedule(device *me,
}
INLINE_DEVICE\
-(signed64)
+(int64_t)
device_event_queue_time(device *me)
{
return event_queue_time(psim_event_queue(me->system));
diff --git a/sim/ppc/device.h b/sim/ppc/device.h
index 68a2d24dd8df..bd5390951608 100644
--- a/sim/ppc/device.h
+++ b/sim/ppc/device.h
@@ -780,7 +780,7 @@ typedef void device_event_handler(void *data);
INLINE_DEVICE\
(event_entry_tag) device_event_queue_schedule
(device *me,
- signed64 delta_time,
+ int64_t delta_time,
device_event_handler *handler,
void *data);
@@ -790,7 +790,7 @@ INLINE_DEVICE\
event_entry_tag event_to_remove);
INLINE_DEVICE\
-(signed64) device_event_queue_time
+(int64_t) device_event_queue_time
(device *me);
#endif /* _DEVICE_H_ */
diff --git a/sim/ppc/double.c b/sim/ppc/double.c
index 615797fc45eb..d52c4d27fc04 100644
--- a/sim/ppc/double.c
+++ b/sim/ppc/double.c
@@ -24,16 +24,16 @@
#include "basics.h"
#include "ansidecls.h"
-#define SFtype unsigned32
-#define DFtype unsigned64
+#define SFtype uint32_t
+#define DFtype uint64_t
-#define HItype signed16
-#define SItype signed32
-#define DItype signed64
+#define HItype int16_t
+#define SItype int32_t
+#define DItype int64_t
-#define UHItype unsigned16
-#define USItype unsigned32
-#define UDItype unsigned64
+#define UHItype uint16_t
+#define USItype uint32_t
+#define UDItype uint64_t
#define US_SOFTWARE_GOFAST
diff --git a/sim/ppc/e500.igen b/sim/ppc/e500.igen
index 5b9c5538ab54..dce18655a8e2 100644
--- a/sim/ppc/e500.igen
+++ b/sim/ppc/e500.igen
@@ -37,8 +37,8 @@
} while (0)
# Schedule an instruction that takes 2 integer register and produces a special purpose output register plus an integer output register
-void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned nSPR
- const unsigned32 int_mask = out_mask | in_mask;
+void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask, const unsigned nSPR
+ const uint32_t int_mask = out_mask | in_mask;
model_busy *busy_ptr;
while ((model_ptr->int_busy & int_mask) != 0 || model_ptr->spr_busy[nSPR] != 0) {
@@ -60,23 +60,23 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
#
# SPE Modulo Fractional Multiplication handling support
#
-:function:e500::unsigned64:ev_multiply16_smf:signed16 a, signed16 b, int *sat
- signed32 a32 = a, b32 = b, rv32;
+:function:e500::uint64_t:ev_multiply16_smf:int16_t a, int16_t b, int *sat
+ int32_t a32 = a, b32 = b, rv32;
rv32 = a * b;
*sat = (rv32 & (3<<30)) == (3<<30);
- return (signed64)rv32 << 1;
+ return (int64_t)rv32 << 1;
-:function:e500::unsigned64:ev_multiply32_smf:signed32 a, signed32 b, int *sat
- signed64 rv64, a64 = a, b64 = b;
+:function:e500::uint64_t:ev_multiply32_smf:int32_t a, int32_t b, int *sat
+ int64_t rv64, a64 = a, b64 = b;
rv64 = a64 * b64;
- *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62);
+ *sat = (rv64 & ((int64_t)3<<62)) == ((int64_t)3<<62);
/* Loses top sign bit. */
return rv64 << 1;
#
# SPE Saturation handling support
#
-:function:e500::signed32:ev_multiply16_ssf:signed16 a, signed16 b, int *sat
- signed32 rv32;
+:function:e500::int32_t:ev_multiply16_ssf:int16_t a, int16_t b, int *sat
+ int32_t rv32;
if (a == 0xffff8000 && b == 0xffff8000)
{
rv32 = 0x7fffffffL;
@@ -85,15 +85,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
}
else
{
- signed32 a32 = a, b32 = b;
+ int32_t a32 = a, b32 = b;
rv32 = a * b;
* sat = (rv32 & (3<<30)) == (3<<30);
- return (signed64)rv32 << 1;
+ return (int64_t)rv32 << 1;
}
-:function:e500::signed64:ev_multiply32_ssf:signed32 a, signed32 b, int *sat
- signed64 rv64;
+:function:e500::int64_t:ev_multiply32_ssf:int32_t a, int32_t b, int *sat
+ int64_t rv64;
if (a == 0x80000000 && b == 0x80000000)
{
rv64 = 0x7fffffffffffffffLL;
@@ -102,9 +102,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
}
else
{
- signed64 a64 = a, b64 = b;
+ int64_t a64 = a, b64 = b;
rv64 = a64 * b64;
- *sat = (rv64 & ((signed64)3<<62)) == ((signed64)3<<62);
+ *sat = (rv64 & ((int64_t)3<<62)) == ((int64_t)3<<62);
/* Loses top sign bit. */
return rv64 << 1;
}
@@ -114,21 +114,21 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
#
:function:e500::void:ev_check_guard:sim_fpu *a, int fg, int fx, cpu *processor
- unsigned64 guard;
+ uint64_t guard;
guard = sim_fpu_guard(a, 0);
if (guard & 1)
EV_SET_SPEFSCR_BITS(fg);
if (guard & ~1)
EV_SET_SPEFSCR_BITS(fx);
-:function:e500::void:booke_sim_fpu_32to:sim_fpu *dst, unsigned32 packed
+:function:e500::void:booke_sim_fpu_32to:sim_fpu *dst, uint32_t packed
sim_fpu_32to (dst, packed);
/* Set normally unused fields to allow booke arithmetic. */
if (dst->class == sim_fpu_class_infinity)
{
dst->normal_exp = 128;
- dst->fraction = ((unsigned64)1 << 60);
+ dst->fraction = ((uint64_t)1 << 60);
}
else if (dst->class == sim_fpu_class_qnan
|| dst->class == sim_fpu_class_snan)
@@ -136,7 +136,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
dst->normal_exp = 128;
/* This is set, but without the implicit bit, so we have to or
in the implicit bit. */
- dst->fraction |= ((unsigned64)1 << 60);
+ dst->fraction |= ((uint64_t)1 << 60);
}
:function:e500::int:booke_sim_fpu_add:sim_fpu *d, sim_fpu *a, sim_fpu *b, int inv, int over, int under, cpu *processor
@@ -207,9 +207,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
return invalid_operand || overflow_result || underflow_result;
-:function:e500::unsigned32:ev_fs_add:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor
+:function:e500::uint32_t:ev_fs_add:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor
sim_fpu a, b, d;
- unsigned32 w;
+ uint32_t w;
int exception;
booke_sim_fpu_32to (&a, aa);
@@ -223,9 +223,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
ev_check_guard(&d, fg, fx, processor);
return w;
-:function:e500::unsigned32:ev_fs_sub:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor
+:function:e500::uint32_t:ev_fs_sub:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor
sim_fpu a, b, d;
- unsigned32 w;
+ uint32_t w;
int exception;
booke_sim_fpu_32to (&a, aa);
@@ -244,7 +244,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
# sim_fpu_exp leaves the normal_exp field undefined for Inf and NaN.
# The booke algorithms require exp values, so we fake them here.
# fixme: It also apparently does the same for zero, but should not.
-:function:e500::unsigned32:booke_sim_fpu_exp:sim_fpu *x
+:function:e500::uint32_t:booke_sim_fpu_exp:sim_fpu *x
int y = sim_fpu_is (x);
if (y == SIM_FPU_IS_PZERO || y == SIM_FPU_IS_NZERO)
return 0;
@@ -254,9 +254,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
else
return sim_fpu_exp (x);
-:function:e500::unsigned32:ev_fs_mul:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int fg, int fx, cpu *processor
+:function:e500::uint32_t:ev_fs_mul:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor
sim_fpu a, b, d;
- unsigned32 w;
+ uint32_t w;
int sa, sb, ea, eb, ei;
sim_fpu_32to (&a, aa);
sim_fpu_32to (&b, bb);
@@ -296,9 +296,9 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
}
return w;
-:function:e500::unsigned32:ev_fs_div:unsigned32 aa, unsigned32 bb, int inv, int over, int under, int dbz, int fg, int fx, cpu *processor
+:function:e500::uint32_t:ev_fs_div:uint32_t aa, uint32_t bb, int inv, int over, int under, int dbz, int fg, int fx, cpu *processor
sim_fpu a, b, d;
- unsigned32 w;
+ uint32_t w;
int sa, sb, ea, eb, ei;
sim_fpu_32to (&a, aa);
@@ -381,7 +381,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
#
0.4,6.RS,11.RA,16.RB,21.512:X:e500:evaddw %RS,%RA,%RB:Vector Add Word
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh + *rAh;
w2 = *rB + *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -389,7 +389,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.IMM,16.RB,21.514:X:e500:evaddiw %RS,%RB,%IMM:Vector Add Immediate Word
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh + IMM;
w2 = *rB + IMM;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -397,7 +397,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.516:X:e500:evsubfw %RS,%RA,%RB:Vector Subtract from Word
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh - *rAh;
w2 = *rB - *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -405,7 +405,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.IMM,16.RB,21.518:X:e500:evsubifw %RS,%RB,%IMM:Vector Subtract Immediate from Word
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh - IMM;
w2 = *rB - IMM;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -413,7 +413,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.520:X:e500:evabs %RS,%RA:Vector Absolute Value
- signed32 w1, w2;
+ int32_t w1, w2;
w1 = *rAh;
if (w1 < 0 && w1 != 0x80000000)
w1 = -w1;
@@ -424,7 +424,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.521:X:e500:evneg %RS,%RA:Vector Negate
- signed32 w1, w2;
+ int32_t w1, w2;
w1 = *rAh;
/* the negative most negative number is the most negative number */
if (w1 != 0x80000000)
@@ -436,7 +436,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.522:X:e500:evextsb %RS,%RA:Vector Extend Signed Byte
- unsigned64 w1, w2;
+ uint64_t w1, w2;
w1 = *rAh & 0xff;
if (w1 & 0x80)
w1 |= 0xffffff00;
@@ -447,7 +447,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK , 0);
0.4,6.RS,11.RA,16.0,21.523:X:e500:evextsb %RS,%RA:Vector Extend Signed Half Word
- unsigned64 w1, w2;
+ uint64_t w1, w2;
w1 = *rAh & 0xffff;
if (w1 & 0x8000)
w1 |= 0xffff0000;
@@ -458,49 +458,49 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.529:X:e500:evand %RS,%RA,%RB:Vector AND
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh & *rAh;
w2 = *rB & *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.535:X:e500:evor %RS,%RA,%RB:Vector OR
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh | *rAh;
w2 = *rB | *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.534:X:e500:evxor %RS,%RA,%RB:Vector XOR
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rBh ^ *rAh;
w2 = *rB ^ *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.542:X:e500:evnand %RS,%RA,%RB:Vector NAND
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = ~(*rBh & *rAh);
w2 = ~(*rB & *rA);
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.536:X:e500:evnor %RS,%RA,%RB:Vector NOR
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = ~(*rBh | *rAh);
w2 = ~(*rB | *rA);
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.537:X:e500:eveqv %RS,%RA,%RB:Vector Equivalent
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = (~*rBh) ^ *rAh;
w2 = (~*rB) ^ *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.530:X:e500:evandc %RS,%RA,%RB:Vector AND with Compliment
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = (~*rBh) & *rAh;
w2 = (~*rB) & *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -508,7 +508,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.539:X:e500:evorc %RS,%RA,%RB:Vector OR with Compliment
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = (~*rBh) | *rAh;
w2 = (~*rB) | *rA;
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -516,76 +516,76 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.552:X:e500:evrlw %RS,%RA,%RB:Vector Rotate Left Word
- unsigned32 nh, nl, w1, w2;
+ uint32_t nh, nl, w1, w2;
nh = *rBh & 0x1f;
nl = *rB & 0x1f;
- w1 = ((unsigned32)*rAh) << nh | ((unsigned32)*rAh) >> (32 - nh);
- w2 = ((unsigned32)*rA) << nl | ((unsigned32)*rA) >> (32 - nl);
+ w1 = ((uint32_t)*rAh) << nh | ((uint32_t)*rAh) >> (32 - nh);
+ w2 = ((uint32_t)*rA) << nl | ((uint32_t)*rA) >> (32 - nl);
EV_SET_REG2(*rSh, *rS, w1, w2);
//printf("evrlw: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.UIMM,21.554:X:e500:evrlwi %RS,%RA,%UIMM:Vector Rotate Left Word Immediate
- unsigned32 w1, w2, imm;
- imm = (unsigned32)UIMM;
- w1 = ((unsigned32)*rAh) << imm | ((unsigned32)*rAh) >> (32 - imm);
- w2 = ((unsigned32)*rA) << imm | ((unsigned32)*rA) >> (32 - imm);
+ uint32_t w1, w2, imm;
+ imm = (uint32_t)UIMM;
+ w1 = ((uint32_t)*rAh) << imm | ((uint32_t)*rAh) >> (32 - imm);
+ w2 = ((uint32_t)*rA) << imm | ((uint32_t)*rA) >> (32 - imm);
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.548:X:e500:evslw %RS,%RA,%RB:Vector Shift Left Word
- unsigned32 nh, nl, w1, w2;
+ uint32_t nh, nl, w1, w2;
nh = *rBh & 0x1f;
nl = *rB & 0x1f;
- w1 = ((unsigned32)*rAh) << nh;
- w2 = ((unsigned32)*rA) << nl;
+ w1 = ((uint32_t)*rAh) << nh;
+ w2 = ((uint32_t)*rA) << nl;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.UIMM,21.550:X:e500:evslwi %RS,%RA,%UIMM:Vector Shift Left Word Immediate
- unsigned32 w1, w2, imm = UIMM;
- w1 = ((unsigned32)*rAh) << imm;
- w2 = ((unsigned32)*rA) << imm;
+ uint32_t w1, w2, imm = UIMM;
+ w1 = ((uint32_t)*rAh) << imm;
+ w2 = ((uint32_t)*rA) << imm;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.545:X:e500:evsrws %RS,%RA,%RB:Vector Shift Right Word Signed
- signed32 w1, w2;
- unsigned32 nh, nl;
+ int32_t w1, w2;
+ uint32_t nh, nl;
nh = *rBh & 0x1f;
nl = *rB & 0x1f;
- w1 = ((signed32)*rAh) >> nh;
- w2 = ((signed32)*rA) >> nl;
+ w1 = ((int32_t)*rAh) >> nh;
+ w2 = ((int32_t)*rA) >> nl;
EV_SET_REG2(*rSh, *rS, w1, w2);
//printf("evsrws: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.544:X:e500:evsrwu %RS,%RA,%RB:Vector Shift Right Word Unsigned
- unsigned32 w1, w2, nh, nl;
+ uint32_t w1, w2, nh, nl;
nh = *rBh & 0x1f;
nl = *rB & 0x1f;
- w1 = ((unsigned32)*rAh) >> nh;
- w2 = ((unsigned32)*rA) >> nl;
+ w1 = ((uint32_t)*rAh) >> nh;
+ w2 = ((uint32_t)*rA) >> nl;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.UIMM,21.547:X:e500:evsrwis %RS,%RA,%UIMM:Vector Shift Right Word Immediate Signed
- signed32 w1, w2;
- unsigned32 imm = UIMM;
- w1 = ((signed32)*rAh) >> imm;
- w2 = ((signed32)*rA) >> imm;
+ int32_t w1, w2;
+ uint32_t imm = UIMM;
+ w1 = ((int32_t)*rAh) >> imm;
+ w2 = ((int32_t)*rA) >> imm;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.UIMM,21.546:X:e500:evsrwiu %RS,%RA,%UIMM:Vector Shift Right Word Immediate Unsigned
- unsigned32 w1, w2, imm = UIMM;
- w1 = ((unsigned32)*rAh) >> imm;
- w2 = ((unsigned32)*rA) >> imm;
+ uint32_t w1, w2, imm = UIMM;
+ w1 = ((uint32_t)*rAh) >> imm;
+ w2 = ((uint32_t)*rA) >> imm;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.525:X:e500:evcntlzw %RS,%RA:Vector Count Leading Zeros Word
- unsigned32 w1, w2, mask, c1, c2;
+ uint32_t w1, w2, mask, c1, c2;
for (c1 = 0, mask = 0x80000000, w1 = *rAh;
!(w1 & mask) && mask != 0; mask >>= 1)
c1++;
@@ -596,7 +596,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.526:X:e500:evcntlsw %RS,%RA:Vector Count Leading Sign Bits Word
- unsigned32 w1, w2, mask, sign_bit, c1, c2;
+ uint32_t w1, w2, mask, sign_bit, c1, c2;
for (c1 = 0, mask = 0x80000000, w1 = *rAh, sign_bit = w1 & mask;
((w1 & mask) == sign_bit) && mask != 0;
mask >>= 1, sign_bit >>= 1)
@@ -609,43 +609,43 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.524:X:e500:evrndw %RS,%RA:Vector Round Word
- unsigned32 w1, w2;
- w1 = ((unsigned32)*rAh + 0x8000) & 0xffff0000;
- w2 = ((unsigned32)*rA + 0x8000) & 0xffff0000;
+ uint32_t w1, w2;
+ w1 = ((uint32_t)*rAh + 0x8000) & 0xffff0000;
+ w2 = ((uint32_t)*rA + 0x8000) & 0xffff0000;
EV_SET_REG2(*rSh, *rS, w1, w2);
//printf("evrndw: *rSh = %08x; *rS = %08x\n", *rSh, *rS);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.556:X:e500:evmergehi %RS,%RA,%RB:Vector Merge Hi
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rAh;
w2 = *rBh;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.557:X:e500:evmergelo %RS,%RA,%RB:Vector Merge Low
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rA;
w2 = *rB;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.559:X:e500:evmergelohi %RS,%RA,%RB:Vector Merge Low Hi
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rA;
w2 = *rBh;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.558:X:e500:evmergehilo %RS,%RA,%RB:Vector Merge Hi Low
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rAh;
w2 = *rB;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.SIMM,16.0,21.553:X:e500:evsplati %RS,%SIMM:Vector Splat Immediate
- unsigned32 w;
+ uint32_t w;
w = SIMM & 0x1f;
if (w & 0x10)
w |= 0xffffffe0;
@@ -653,13 +653,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, 0, 0);
0.4,6.RS,11.SIMM,16.0,21.555:X:e500:evsplatfi %RS,%SIMM:Vector Splat Fractional Immediate
- unsigned32 w;
+ uint32_t w;
w = SIMM << 27;
EV_SET_REG2(*rSh, *rS, w, w);
PPC_INSN_INT(RS_BITMASK, 0, 0);
0.4,6.BF,9.0,11.RA,16.RB,21.561:X:e500:evcmpgts %BF,%RA,%RB:Vector Compare Greater Than Signed
- signed32 ah, al, bh, bl;
+ int32_t ah, al, bh, bl;
int w, ch, cl;
ah = *rAh;
al = *rA;
@@ -678,7 +678,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.BF,9.0,11.RA,16.RB,21.560:X:e500:evcmpgtu %BF,%RA,%RB:Vector Compare Greater Than Unsigned
- unsigned32 ah, al, bh, bl;
+ uint32_t ah, al, bh, bl;
int w, ch, cl;
ah = *rAh;
al = *rA;
@@ -697,7 +697,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.BF,9.0,11.RA,16.RB,21.563:X:e500:evcmplts %BF,%RA,%RB:Vector Compare Less Than Signed
- signed32 ah, al, bh, bl;
+ int32_t ah, al, bh, bl;
int w, ch, cl;
ah = *rAh;
al = *rA;
@@ -716,7 +716,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.BF,9.0,11.RA,16.RB,21.562:X:e500:evcmpltu %BF,%RA,%RB:Vector Compare Less Than Unsigned
- unsigned32 ah, al, bh, bl;
+ uint32_t ah, al, bh, bl;
int w, ch, cl;
ah = *rAh;
al = *rA;
@@ -735,7 +735,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.BF,9.0,11.RA,16.RB,21.564:X:e500:evcmpeq %BF,%RA,%RB:Vector Compare Equal
- unsigned32 ah, al, bh, bl;
+ uint32_t ah, al, bh, bl;
int w, ch, cl;
ah = *rAh;
al = *rA;
@@ -755,7 +755,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.RS,11.RA,16.RB,21.79,29.CRFS:X:e500:evsel %RS,%RA,%RB,%CRFS:Vector Select
- unsigned32 w1, w2;
+ uint32_t w1, w2;
int cr;
cr = CR_FIELD(CRFS);
if (cr & 8)
@@ -770,7 +770,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.527:X:e500:brinc %RS,%RA,%RB:Bit Reversed Increment
- unsigned32 w1, w2, a, d, mask;
+ uint32_t w1, w2, a, d, mask;
mask = (*rB) & 0xffff;
a = (*rA) & 0xffff;
d = EV_BITREVERSE16(1 + EV_BITREVERSE16(a | ~mask));
@@ -783,14 +783,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
#
0.4,6.RS,11.RA,16.RB,21.1031:EVX:e500:evmhossf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int movl, movh;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
tl = ev_multiply16_ssf (al, bl, &movl);
th = ev_multiply16_ssf (ah, bh, &movh);
EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
@@ -799,14 +799,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1063:EVX:e500:evmhossfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional Accumulate
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int movl, movh;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
tl = ev_multiply16_ssf (al, bl, &movl);
th = ev_multiply16_ssf (ah, bh, &movh);
EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
@@ -815,39 +815,39 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1039:EVX:e500:evmhosmf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int dummy;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
tl = ev_multiply16_smf (al, bl, & dummy);
th = ev_multiply16_smf (ah, bh, & dummy);
EV_SET_REG2 (*rSh, *rS, th, tl);
PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1071:EVX:e500:evmhosmfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional Accumulate
- signed32 al, ah, bl, bh;
- signed32 tl, th;
+ int32_t al, ah, bl, bh;
+ int32_t tl, th;
int dummy;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
tl = ev_multiply16_smf (al, bl, & dummy);
th = ev_multiply16_smf (ah, bh, & dummy);
EV_SET_REG2_ACC (*rSh, *rS, th, tl);
PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1037:EVX:e500:evmhosmi %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer
- signed32 al, ah, bl, bh, tl, th;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
+ int32_t al, ah, bl, bh, tl, th;
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2(*rSh, *rS, th, tl);
@@ -855,11 +855,11 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1069:EVX:e500:evmhosmia %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer Accumulate
- signed32 al, ah, bl, bh, tl, th;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
+ int32_t al, ah, bl, bh, tl, th;
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2_ACC(*rSh, *rS, th, tl);
@@ -867,36 +867,36 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1036:EVX:e500:evmhoumi %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer
- unsigned32 al, ah, bl, bh, tl, th;
- al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
+ uint32_t al, ah, bl, bh, tl, th;
+ al = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2(*rSh, *rS, th, tl);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1068:EVX:e500:evmhoumia %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer Accumulate
- unsigned32 al, ah, bl, bh, tl, th;
- al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
+ uint32_t al, ah, bl, bh, tl, th;
+ al = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2_ACC(*rSh, *rS, th, tl);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1027:EVX:e500:evmhessf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int movl, movh;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
tl = ev_multiply16_ssf (al, bl, &movl);
th = ev_multiply16_ssf (ah, bh, &movh);
EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
@@ -905,14 +905,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1059:EVX:e500:evmhessfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional Accumulate
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int movl, movh;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
tl = ev_multiply16_ssf (al, bl, &movl);
th = ev_multiply16_ssf (ah, bh, &movh);
EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th),
@@ -921,14 +921,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1035:EVX:e500:evmhesmf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional
- signed16 al, ah, bl, bh;
- signed64 tl, th;
+ int16_t al, ah, bl, bh;
+ int64_t tl, th;
int movl, movh;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
tl = ev_multiply16_smf (al, bl, &movl);
th = ev_multiply16_smf (ah, bh, &movh);
EV_SET_REG2 (*rSh, *rS, th, tl);
@@ -936,75 +936,75 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1067:EVX:e500:evmhesmfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional Accumulate
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
int dummy;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
tl = ev_multiply16_smf (al, bl, & dummy);
th = ev_multiply16_smf (ah, bh, & dummy);
EV_SET_REG2_ACC (*rSh, *rS, th, tl);
PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1033:EVX:e500:evmhesmi %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer
- signed16 al, ah, bl, bh;
- signed32 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t tl, th;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2 (*rSh, *rS, th, tl);
PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1065:EVX:e500:evmhesmia %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer Accumulate
- signed32 al, ah, bl, bh, tl, th;
- al = (signed32)(signed16)EV_HIHALF(*rA);
- ah = (signed32)(signed16)EV_HIHALF(*rAh);
- bl = (signed32)(signed16)EV_HIHALF(*rB);
- bh = (signed32)(signed16)EV_HIHALF(*rBh);
+ int32_t al, ah, bl, bh, tl, th;
+ al = (int32_t)(int16_t)EV_HIHALF(*rA);
+ ah = (int32_t)(int16_t)EV_HIHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_HIHALF(*rB);
+ bh = (int32_t)(int16_t)EV_HIHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2_ACC(*rSh, *rS, th, tl);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1032:EVX:e500:evmheumi %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer
- unsigned32 al, ah, bl, bh, tl, th;
- al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
+ uint32_t al, ah, bl, bh, tl, th;
+ al = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_HIHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2(*rSh, *rS, th, tl);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1064:EVX:e500:evmheumia %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer Accumulate
- unsigned32 al, ah, bl, bh, tl, th;
- al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
+ uint32_t al, ah, bl, bh, tl, th;
+ al = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_HIHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh);
tl = al * bl;
th = ah * bh;
EV_SET_REG2_ACC(*rSh, *rS, th, tl);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1287:EVX:e500:evmhossfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate into Words
- signed16 al, ah, bl, bh;
- signed32 t1, t2;
- signed64 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t t1, t2;
+ int64_t tl, th;
int movl, movh, ovl, ovh;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
t1 = ev_multiply16_ssf (ah, bh, &movh);
t2 = ev_multiply16_ssf (al, bl, &movl);
th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1);
@@ -1017,13 +1017,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1285:EVX:e500:evmhossiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
int ovl, ovh;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH + t1;
@@ -1038,26 +1038,26 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1295:EVX:e500:evmhosmfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
- t1 = ((signed64)ah * bh) << 1;
- t2 = ((signed64)al * bl) << 1;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
+ t1 = ((int64_t)ah * bh) << 1;
+ t2 = ((int64_t)al * bl) << 1;
th = EV_ACCHIGH + (t1 & 0xffffffff);
tl = EV_ACCLOW + (t2 & 0xffffffff);
EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1293:EVX:e500:evmhosmiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH + t1;
@@ -1068,18 +1068,18 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1284:EVX:e500:evmhousiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate into Words
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
- signed64 tl, th;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
+ int64_t tl, th;
int ovl, ovh;
- al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
+ al = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
- th = (signed64)EV_ACCHIGH + (signed64)t1;
- tl = (signed64)EV_ACCLOW + (signed64)t2;
+ th = (int64_t)EV_ACCHIGH + (int64_t)t1;
+ tl = (int64_t)EV_ACCLOW + (int64_t)t2;
ovh = EV_SAT_P_U32(th);
ovl = EV_SAT_P_U32(tl);
EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th),
@@ -1090,13 +1090,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1292:EVX:e500:evmhoumiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate into Words
- unsigned32 al, ah, bl, bh;
- unsigned32 t1, t2;
- signed64 tl, th;
- al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
+ uint32_t al, ah, bl, bh;
+ uint32_t t1, t2;
+ int64_t tl, th;
+ al = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH + t1;
@@ -1107,15 +1107,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1283:EVX:e500:evmhessfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate into Words
- signed16 al, ah, bl, bh;
- signed32 t1, t2;
- signed64 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t t1, t2;
+ int64_t tl, th;
int movl, movh, ovl, ovh;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
t1 = ev_multiply16_ssf (ah, bh, &movh);
t2 = ev_multiply16_ssf (al, bl, &movl);
th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1);
@@ -1128,13 +1128,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1281:EVX:e500:evmhessiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
int ovl, ovh;
- al = (signed32)(signed16)EV_HIHALF(*rA);
- ah = (signed32)(signed16)EV_HIHALF(*rAh);
- bl = (signed32)(signed16)EV_HIHALF(*rB);
- bh = (signed32)(signed16)EV_HIHALF(*rBh);
+ al = (int32_t)(int16_t)EV_HIHALF(*rA);
+ ah = (int32_t)(int16_t)EV_HIHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_HIHALF(*rB);
+ bh = (int32_t)(int16_t)EV_HIHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH + t1;
@@ -1149,14 +1149,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1291:EVX:e500:evmhesmfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate into Words
- signed16 al, ah, bl, bh;
- signed32 t1, t2, th, tl;
+ int16_t al, ah, bl, bh;
+ int32_t t1, t2, th, tl;
int dummy;
- al = (signed16)EV_HIHALF(*rA);
- ah = (signed16)EV_HIHALF(*rAh);
- bl = (signed16)EV_HIHALF(*rB);
- bh = (signed16)EV_HIHALF(*rBh);
+ al = (int16_t)EV_HIHALF(*rA);
+ ah = (int16_t)EV_HIHALF(*rAh);
+ bl = (int16_t)EV_HIHALF(*rB);
+ bh = (int16_t)EV_HIHALF(*rBh);
t1 = ev_multiply16_smf (ah, bh, &dummy);
t2 = ev_multiply16_smf (al, bl, &dummy);
th = EV_ACCHIGH + t1;
@@ -1165,12 +1165,12 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1289:EVX:e500:evmhesmiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
- al = (signed32)(signed16)EV_HIHALF(*rA);
- ah = (signed32)(signed16)EV_HIHALF(*rAh);
- bl = (signed32)(signed16)EV_HIHALF(*rB);
- bh = (signed32)(signed16)EV_HIHALF(*rBh);
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
+ al = (int32_t)(int16_t)EV_HIHALF(*rA);
+ ah = (int32_t)(int16_t)EV_HIHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_HIHALF(*rB);
+ bh = (int32_t)(int16_t)EV_HIHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH + t1;
@@ -1179,18 +1179,18 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1280:EVX:e500:evmheusiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate into Words
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
- signed64 tl, th;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
+ int64_t tl, th;
int ovl, ovh;
- al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
+ al = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_HIHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
- th = (signed64)EV_ACCHIGH + (signed64)t1;
- tl = (signed64)EV_ACCLOW + (signed64)t2;
+ th = (int64_t)EV_ACCHIGH + (int64_t)t1;
+ tl = (int64_t)EV_ACCLOW + (int64_t)t2;
ovh = EV_SAT_P_U32(th);
ovl = EV_SAT_P_U32(tl);
EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th),
@@ -1199,13 +1199,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1288:EVX:e500:evmheumiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate into Words
- unsigned32 al, ah, bl, bh;
- unsigned32 t1, t2;
- unsigned64 tl, th;
- al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
+ uint32_t al, ah, bl, bh;
+ uint32_t t1, t2;
+ uint64_t tl, th;
+ al = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_HIHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH + t1;
@@ -1215,15 +1215,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.1415:EVX:e500:evmhossfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate Negative into Words
- signed16 al, ah, bl, bh;
- signed32 t1, t2;
- signed64 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t t1, t2;
+ int64_t tl, th;
int movl, movh, ovl, ovh;
- al = (signed16) EV_LOHALF (*rA);
- ah = (signed16) EV_LOHALF (*rAh);
- bl = (signed16) EV_LOHALF (*rB);
- bh = (signed16) EV_LOHALF (*rBh);
+ al = (int16_t) EV_LOHALF (*rA);
+ ah = (int16_t) EV_LOHALF (*rAh);
+ bl = (int16_t) EV_LOHALF (*rB);
+ bh = (int16_t) EV_LOHALF (*rBh);
t1 = ev_multiply16_ssf (ah, bh, &movh);
t2 = ev_multiply16_ssf (al, bl, &movl);
th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1);
@@ -1236,13 +1236,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1413:EVX:e500:evmhossianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate Negative into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
int ovl, ovh;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH - t1;
@@ -1256,26 +1256,26 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1423:EVX:e500:evmhosmfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate Negative into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
- t1 = ((signed64)ah * bh) << 1;
- t2 = ((signed64)al * bl) << 1;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
+ t1 = ((int64_t)ah * bh) << 1;
+ t2 = ((int64_t)al * bl) << 1;
th = EV_ACCHIGH - (t1 & 0xffffffff);
tl = EV_ACCLOW - (t2 & 0xffffffff);
EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1421:EVX:e500:evmhosmianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate Negative into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
- al = (signed32)(signed16)EV_LOHALF(*rA);
- ah = (signed32)(signed16)EV_LOHALF(*rAh);
- bl = (signed32)(signed16)EV_LOHALF(*rB);
- bh = (signed32)(signed16)EV_LOHALF(*rBh);
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
+ al = (int32_t)(int16_t)EV_LOHALF(*rA);
+ ah = (int32_t)(int16_t)EV_LOHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_LOHALF(*rB);
+ bh = (int32_t)(int16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH - t1;
@@ -1284,18 +1284,18 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1412:EVX:e500:evmhousianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate Negative into Words
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
- signed64 tl, th;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
+ int64_t tl, th;
int ovl, ovh;
- al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
+ al = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
- th = (signed64)EV_ACCHIGH - (signed64)t1;
- tl = (signed64)EV_ACCLOW - (signed64)t2;
+ th = (int64_t)EV_ACCHIGH - (int64_t)t1;
+ tl = (int64_t)EV_ACCLOW - (int64_t)t2;
ovl = EV_SAT_P_U32(tl);
ovh = EV_SAT_P_U32(th);
EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th),
@@ -1306,13 +1306,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1420:EVX:e500:evmhoumianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate Negative into Words
- unsigned32 al, ah, bl, bh;
- unsigned32 t1, t2;
- unsigned64 tl, th;
- al = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_LOHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_LOHALF(*rBh);
+ uint32_t al, ah, bl, bh;
+ uint32_t t1, t2;
+ uint64_t tl, th;
+ al = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH - t1;
@@ -1321,15 +1321,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1411:EVX:e500:evmhessfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate Negative into Words
- signed16 al, ah, bl, bh;
- signed32 t1, t2;
- signed64 tl, th;
+ int16_t al, ah, bl, bh;
+ int32_t t1, t2;
+ int64_t tl, th;
int movl, movh, ovl, ovh;
- al = (signed16) EV_HIHALF (*rA);
- ah = (signed16) EV_HIHALF (*rAh);
- bl = (signed16) EV_HIHALF (*rB);
- bh = (signed16) EV_HIHALF (*rBh);
+ al = (int16_t) EV_HIHALF (*rA);
+ ah = (int16_t) EV_HIHALF (*rAh);
+ bl = (int16_t) EV_HIHALF (*rB);
+ bh = (int16_t) EV_HIHALF (*rBh);
t1 = ev_multiply16_ssf (ah, bh, &movh);
t2 = ev_multiply16_ssf (al, bl, &movl);
th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1);
@@ -1342,13 +1342,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1409:EVX:e500:evmhessianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate Negative into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
int ovl, ovh;
- al = (signed32)(signed16)EV_HIHALF(*rA);
- ah = (signed32)(signed16)EV_HIHALF(*rAh);
- bl = (signed32)(signed16)EV_HIHALF(*rB);
- bh = (signed32)(signed16)EV_HIHALF(*rBh);
+ al = (int32_t)(int16_t)EV_HIHALF(*rA);
+ ah = (int32_t)(int16_t)EV_HIHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_HIHALF(*rB);
+ bh = (int32_t)(int16_t)EV_HIHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH - t1;
@@ -1361,26 +1361,26 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1419:EVX:e500:evmhesmfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate Negative into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
- al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
- t1 = ((signed64)ah * bh) << 1;
- t2 = ((signed64)al * bl) << 1;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
+ al = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_HIHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh);
+ t1 = ((int64_t)ah * bh) << 1;
+ t2 = ((int64_t)al * bl) << 1;
th = EV_ACCHIGH - (t1 & 0xffffffff);
tl = EV_ACCLOW - (t2 & 0xffffffff);
EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1417:EVX:e500:evmhesmianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate Negative into Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
- al = (signed32)(signed16)EV_HIHALF(*rA);
- ah = (signed32)(signed16)EV_HIHALF(*rAh);
- bl = (signed32)(signed16)EV_HIHALF(*rB);
- bh = (signed32)(signed16)EV_HIHALF(*rBh);
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
+ al = (int32_t)(int16_t)EV_HIHALF(*rA);
+ ah = (int32_t)(int16_t)EV_HIHALF(*rAh);
+ bl = (int32_t)(int16_t)EV_HIHALF(*rB);
+ bh = (int32_t)(int16_t)EV_HIHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH - t1;
@@ -1391,18 +1391,18 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1408:EVX:e500:evmheusianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate Negative into Words
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
- signed64 tl, th;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
+ int64_t tl, th;
int ovl, ovh;
- al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
+ al = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_HIHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
- th = (signed64)EV_ACCHIGH - (signed64)t1;
- tl = (signed64)EV_ACCLOW - (signed64)t2;
+ th = (int64_t)EV_ACCHIGH - (int64_t)t1;
+ tl = (int64_t)EV_ACCLOW - (int64_t)t2;
ovl = EV_SAT_P_U32(tl);
ovh = EV_SAT_P_U32(th);
EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th),
@@ -1413,13 +1413,13 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1416:EVX:e500:evmheumianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate Negative into Words
- unsigned32 al, ah, bl, bh;
- unsigned32 t1, t2;
- unsigned64 tl, th;
- al = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- ah = (unsigned32)(unsigned16)EV_HIHALF(*rAh);
- bl = (unsigned32)(unsigned16)EV_HIHALF(*rB);
- bh = (unsigned32)(unsigned16)EV_HIHALF(*rBh);
+ uint32_t al, ah, bl, bh;
+ uint32_t t1, t2;
+ uint64_t tl, th;
+ al = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh);
+ bl = (uint32_t)(uint16_t)EV_HIHALF(*rB);
+ bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh);
t1 = ah * bh;
t2 = al * bl;
th = EV_ACCHIGH - t1;
@@ -1428,66 +1428,66 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1327:EVX:e500:evmhogsmfaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate
- signed32 a, b;
- signed64 t1, t2;
- a = (signed32)(signed16)EV_LOHALF(*rA);
- b = (signed32)(signed16)EV_LOHALF(*rB);
+ int32_t a, b;
+ int64_t t1, t2;
+ a = (int32_t)(int16_t)EV_LOHALF(*rA);
+ b = (int32_t)(int16_t)EV_LOHALF(*rB);
t1 = EV_MUL16_SSF(a, b);
- if (t1 & ((unsigned64)1 << 32))
+ if (t1 & ((uint64_t)1 << 32))
t1 |= 0xfffffffe00000000;
t2 = ACC + t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1325:EVX:e500:evmhogsmiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate
- signed32 a, b;
- signed64 t1, t2;
- a = (signed32)(signed16)EV_LOHALF(*rA);
- b = (signed32)(signed16)EV_LOHALF(*rB);
- t1 = (signed64)a * (signed64)b;
- t2 = (signed64)ACC + t1;
+ int32_t a, b;
+ int64_t t1, t2;
+ a = (int32_t)(int16_t)EV_LOHALF(*rA);
+ b = (int32_t)(int16_t)EV_LOHALF(*rB);
+ t1 = (int64_t)a * (int64_t)b;
+ t2 = (int64_t)ACC + t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
//printf("evmhogsmiaa: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2);
//printf("evmhogsmiaa: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1324:EVX:e500:evmhogumiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate
- unsigned32 a, b;
- unsigned64 t1, t2;
- a = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- b = (unsigned32)(unsigned16)EV_LOHALF(*rB);
+ uint32_t a, b;
+ uint64_t t1, t2;
+ a = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ b = (uint32_t)(uint16_t)EV_LOHALF(*rB);
t1 = a * b;
t2 = ACC + t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1323:EVX:e500:evmhegsmfaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate
- signed32 a, b;
- signed64 t1, t2;
- a = (signed32)(signed16)EV_HIHALF(*rA);
- b = (signed32)(signed16)EV_HIHALF(*rB);
+ int32_t a, b;
+ int64_t t1, t2;
+ a = (int32_t)(int16_t)EV_HIHALF(*rA);
+ b = (int32_t)(int16_t)EV_HIHALF(*rB);
t1 = EV_MUL16_SSF(a, b);
- if (t1 & ((unsigned64)1 << 32))
+ if (t1 & ((uint64_t)1 << 32))
t1 |= 0xfffffffe00000000;
t2 = ACC + t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1321:EVX:e500:evmhegsmiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate
- signed32 a, b;
- signed64 t1, t2;
- a = (signed32)(signed16)EV_HIHALF(*rA);
- b = (signed32)(signed16)EV_HIHALF(*rB);
- t1 = (signed64)(a * b);
+ int32_t a, b;
+ int64_t t1, t2;
+ a = (int32_t)(int16_t)EV_HIHALF(*rA);
+ b = (int32_t)(int16_t)EV_HIHALF(*rB);
+ t1 = (int64_t)(a * b);
t2 = ACC + t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1320:EVX:e500:evmhegumiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate
- unsigned32 a, b;
- unsigned64 t1, t2;
- a = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- b = (unsigned32)(unsigned16)EV_HIHALF(*rB);
+ uint32_t a, b;
+ uint64_t t1, t2;
+ a = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ b = (uint32_t)(uint16_t)EV_HIHALF(*rB);
t1 = a * b;
t2 = ACC + t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
@@ -1495,23 +1495,23 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.1455:EVX:e500:evmhogsmfan %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate Negative
- signed32 a, b;
- signed64 t1, t2;
- a = (signed32)(signed16)EV_LOHALF(*rA);
- b = (signed32)(signed16)EV_LOHALF(*rB);
+ int32_t a, b;
+ int64_t t1, t2;
+ a = (int32_t)(int16_t)EV_LOHALF(*rA);
+ b = (int32_t)(int16_t)EV_LOHALF(*rB);
t1 = EV_MUL16_SSF(a, b);
- if (t1 & ((unsigned64)1 << 32))
+ if (t1 & ((uint64_t)1 << 32))
t1 |= 0xfffffffe00000000;
t2 = ACC - t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1453:EVX:e500:evmhogsmian %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate Negative
- signed32 a, b;
- signed64 t1, t2;
- a = (signed32)(signed16)EV_LOHALF(*rA);
- b = (signed32)(signed16)EV_LOHALF(*rB);
- t1 = (signed64)a * (signed64)b;
+ int32_t a, b;
+ int64_t t1, t2;
+ a = (int32_t)(int16_t)EV_LOHALF(*rA);
+ b = (int32_t)(int16_t)EV_LOHALF(*rB);
+ t1 = (int64_t)a * (int64_t)b;
t2 = ACC - t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
//printf("evmhogsmian: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2);
@@ -1519,51 +1519,51 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1452:EVX:e500:evmhogumian %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate Negative
- unsigned32 a, b;
- unsigned64 t1, t2;
- a = (unsigned32)(unsigned16)EV_LOHALF(*rA);
- b = (unsigned32)(unsigned16)EV_LOHALF(*rB);
- t1 = (unsigned64)a * (unsigned64)b;
+ uint32_t a, b;
+ uint64_t t1, t2;
+ a = (uint32_t)(uint16_t)EV_LOHALF(*rA);
+ b = (uint32_t)(uint16_t)EV_LOHALF(*rB);
+ t1 = (uint64_t)a * (uint64_t)b;
t2 = ACC - t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1451:EVX:e500:evmhegsmfan %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate Negative
- signed32 a, b;
- signed64 t1, t2;
- a = (signed32)(signed16)EV_HIHALF(*rA);
- b = (signed32)(signed16)EV_HIHALF(*rB);
+ int32_t a, b;
+ int64_t t1, t2;
+ a = (int32_t)(int16_t)EV_HIHALF(*rA);
+ b = (int32_t)(int16_t)EV_HIHALF(*rB);
t1 = EV_MUL16_SSF(a, b);
- if (t1 & ((unsigned64)1 << 32))
+ if (t1 & ((uint64_t)1 << 32))
t1 |= 0xfffffffe00000000;
t2 = ACC - t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1449:EVX:e500:evmhegsmian %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate Negative
- signed32 a, b;
- signed64 t1, t2;
- a = (signed32)(signed16)EV_HIHALF(*rA);
- b = (signed32)(signed16)EV_HIHALF(*rB);
- t1 = (signed64)a * (signed64)b;
+ int32_t a, b;
+ int64_t t1, t2;
+ a = (int32_t)(int16_t)EV_HIHALF(*rA);
+ b = (int32_t)(int16_t)EV_HIHALF(*rB);
+ t1 = (int64_t)a * (int64_t)b;
t2 = ACC - t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1448:EVX:e500:evmhegumian %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate Negative
- unsigned32 a, b;
- unsigned64 t1, t2;
- a = (unsigned32)(unsigned16)EV_HIHALF(*rA);
- b = (unsigned32)(unsigned16)EV_HIHALF(*rB);
- t1 = (unsigned64)a * (unsigned64)b;
+ uint32_t a, b;
+ uint64_t t1, t2;
+ a = (uint32_t)(uint16_t)EV_HIHALF(*rA);
+ b = (uint32_t)(uint16_t)EV_HIHALF(*rB);
+ t1 = (uint64_t)a * (uint64_t)b;
t2 = ACC - t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1095:EVX:e500:evmwhssf %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
int movl, movh;
al = *rA;
ah = *rAh;
@@ -1577,8 +1577,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1127:EVX:e500:evmwhssfa %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional and Accumulate
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
int movl, movh;
al = *rA;
ah = *rAh;
@@ -1592,8 +1592,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1103:EVX:e500:evmwhsmf %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
@@ -1604,8 +1604,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1135:EVX:e500:evmwhsmfa %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional and Accumulate
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
@@ -1616,57 +1616,57 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1101:EVX:e500:evmwhsmi %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (signed64)al * (signed64)bl;
- t2 = (signed64)ah * (signed64)bh;
+ t1 = (int64_t)al * (int64_t)bl;
+ t2 = (int64_t)ah * (int64_t)bh;
EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1133:EVX:e500:evmwhsmia %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer and Accumulate
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (signed64)al * (signed64)bl;
- t2 = (signed64)ah * (signed64)bh;
+ t1 = (int64_t)al * (int64_t)bl;
+ t2 = (int64_t)ah * (int64_t)bh;
EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1100:EVX:e500:evmwhumi %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (unsigned64)al * (unsigned64)bl;
- t2 = (unsigned64)ah * (unsigned64)bh;
+ t1 = (uint64_t)al * (uint64_t)bl;
+ t2 = (uint64_t)ah * (uint64_t)bh;
EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1132:EVX:e500:evmwhumia %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer and Accumulate
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (unsigned64)al * (unsigned64)bl;
- t2 = (unsigned64)ah * (unsigned64)bh;
+ t1 = (uint64_t)al * (uint64_t)bl;
+ t2 = (uint64_t)ah * (uint64_t)bh;
EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1091:EVX:e500:evmwlssf %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
int movl, movh;
al = *rA;
ah = *rAh;
@@ -1680,8 +1680,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1123:EVX:e500:evmwlssfa %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
int movl, movh;
al = *rA;
ah = *rAh;
@@ -1695,8 +1695,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1099:EVX:e500:evmwlsmf %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
@@ -1707,8 +1707,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1131:EVX:e500:evmwlsmfa %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
@@ -1719,33 +1719,33 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1096:EVX:e500:evmwlumi %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (unsigned64)al * (unsigned64)bl;
- t2 = (unsigned64)ah * (unsigned64)bh;
+ t1 = (uint64_t)al * (uint64_t)bl;
+ t2 = (uint64_t)ah * (uint64_t)bh;
EV_SET_REG2(*rSh, *rS, t2, t1);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1128:EVX:e500:evmwlumia %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (unsigned64)al * (unsigned64)bl;
- t2 = (unsigned64)ah * (unsigned64)bh;
+ t1 = (uint64_t)al * (uint64_t)bl;
+ t2 = (uint64_t)ah * (uint64_t)bh;
EV_SET_REG2_ACC(*rSh, *rS, t2, t1);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1347:EVX:e500:evmwlssfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate in Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
int movl, movh, ovl, ovh;
al = *rA;
ah = *rAh;
@@ -1763,15 +1763,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1345:EVX:e500:evmwlssiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate in Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
int ovl, ovh;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (signed64)ah * (signed64)bh;
- t2 = (signed64)al * (signed64)bl;
+ t1 = (int64_t)ah * (int64_t)bh;
+ t2 = (int64_t)al * (int64_t)bl;
th = EV_ACCHIGH + (t1 & 0xffffffff);
tl = EV_ACCLOW + (t2 & 0xffffffff);
ovh = EV_SAT_P_S32(th);
@@ -1782,8 +1782,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1355:EVX:e500:evmwlsmfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate in Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
int mov;
al = *rA;
ah = *rAh;
@@ -1796,14 +1796,14 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1353:EVX:e500:evmwlsmiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate in Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (signed64)ah * (signed64)bh;
- t2 = (signed64)al * (signed64)bl;
+ t1 = (int64_t)ah * (int64_t)bh;
+ t2 = (int64_t)al * (int64_t)bl;
EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff),
EV_ACCLOW + (t2 & 0xffffffff));
//printf("evmwlsmiaaw: al %d ah %d bl %d bh %d t1 %qd t2 %qd\n", al, ah, bl, bh, t1, t2);
@@ -1811,15 +1811,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1344:EVX:e500:evmwlusiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate in Words
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2, tl, th;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2, tl, th;
int ovl, ovh;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (unsigned64)ah * (unsigned64)bh;
- t2 = (unsigned64)al * (unsigned64)bl;
+ t1 = (uint64_t)ah * (uint64_t)bh;
+ t2 = (uint64_t)al * (uint64_t)bl;
th = EV_ACCHIGH + (t1 & 0xffffffff);
tl = EV_ACCLOW + (t2 & 0xffffffff);
ovh = (th >> 32);
@@ -1830,22 +1830,22 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1352:EVX:e500:evmwlumiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate in Words
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (unsigned64)ah * (unsigned64)bh;
- t2 = (unsigned64)al * (unsigned64)bl;
+ t1 = (uint64_t)ah * (uint64_t)bh;
+ t2 = (uint64_t)al * (uint64_t)bl;
EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff),
EV_ACCLOW + (t2 & 0xffffffff));
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1475:EVX:e500:evmwlssfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate Negative in Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
int movl, movh, ovl, ovh;
al = *rA;
ah = *rAh;
@@ -1863,15 +1863,15 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1473:EVX:e500:evmwlssianw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate Negative in Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2, tl, th;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2, tl, th;
int ovl, ovh;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (signed64)ah * (signed64)bh;
- t2 = (signed64)al * (signed64)bl;
+ t1 = (int64_t)ah * (int64_t)bh;
+ t2 = (int64_t)al * (int64_t)bl;
th = EV_ACCHIGH - (t1 & 0xffffffff);
tl = EV_ACCLOW - (t2 & 0xffffffff);
ovh = EV_SAT_P_S32(th);
@@ -1882,8 +1882,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1483:EVX:e500:evmwlsmfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate Negative in Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
int mov;
al = *rA;
ah = *rAh;
@@ -1896,28 +1896,28 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1481:EVX:e500:evmwlsmianw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate Negative in Words
- signed32 al, ah, bl, bh;
- signed64 t1, t2;
+ int32_t al, ah, bl, bh;
+ int64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (signed64)ah * (signed64)bh;
- t2 = (signed64)al * (signed64)bl;
+ t1 = (int64_t)ah * (int64_t)bh;
+ t2 = (int64_t)al * (int64_t)bl;
EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff),
EV_ACCLOW - (t2 & 0xffffffff));
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1472:EVX:e500:evmwlusianw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate Negative in Words
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2, tl, th;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2, tl, th;
int ovl, ovh;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (unsigned64)ah * (unsigned64)bh;
- t2 = (unsigned64)al * (unsigned64)bl;
+ t1 = (uint64_t)ah * (uint64_t)bh;
+ t2 = (uint64_t)al * (uint64_t)bl;
th = EV_ACCHIGH - (t1 & 0xffffffff);
tl = EV_ACCLOW - (t2 & 0xffffffff);
ovh = (th >> 32);
@@ -1930,22 +1930,22 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1480:EVX:e500:evmwlumianw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate Negative in Words
- unsigned32 al, ah, bl, bh;
- unsigned64 t1, t2;
+ uint32_t al, ah, bl, bh;
+ uint64_t t1, t2;
al = *rA;
ah = *rAh;
bl = *rB;
bh = *rBh;
- t1 = (unsigned64)ah * (unsigned64)bh;
- t2 = (unsigned64)al * (unsigned64)bl;
+ t1 = (uint64_t)ah * (uint64_t)bh;
+ t2 = (uint64_t)al * (uint64_t)bl;
EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff),
EV_ACCLOW - (t2 & 0xffffffff));
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1107:EVX:e500:evmwssf %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional
- signed32 a, b;
- signed64 t;
+ int32_t a, b;
+ int64_t t;
int movl;
a = *rA;
b = *rB;
@@ -1955,8 +1955,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1139:EVX:e500:evmwssfa %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional and Accumulate
- signed32 a, b;
- signed64 t;
+ int32_t a, b;
+ int64_t t;
int movl;
a = *rA;
b = *rB;
@@ -1966,8 +1966,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1115:EVX:e500:evmwsmf %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional
- signed32 a, b;
- signed64 t;
+ int32_t a, b;
+ int64_t t;
int movl;
a = *rA;
b = *rB;
@@ -1976,8 +1976,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1147:EVX:e500:evmwsmfa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional and Accumulate
- signed32 a, b;
- signed64 t;
+ int32_t a, b;
+ int64_t t;
int movl;
a = *rA;
b = *rB;
@@ -1986,49 +1986,49 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1113:EVX:e500:evmwsmi %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer
- signed32 a, b;
- signed64 t;
+ int32_t a, b;
+ int64_t t;
int movl;
a = *rA;
b = *rB;
- t = (signed64)a * (signed64)b;
+ t = (int64_t)a * (int64_t)b;
EV_SET_REG1(*rSh, *rS, t);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1145:EVX:e500:evmwsmia %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer and Accumulate
- signed32 a, b;
- signed64 t;
+ int32_t a, b;
+ int64_t t;
int movl;
a = *rA;
b = *rB;
- t = (signed64)a * (signed64)b;
+ t = (int64_t)a * (int64_t)b;
EV_SET_REG1_ACC(*rSh, *rS, t);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1112:EVX:e500:evmwumi %RS,%RA,%RB:Vector Multiply Word Unigned Modulo Integer
- unsigned32 a, b;
- unsigned64 t;
+ uint32_t a, b;
+ uint64_t t;
int movl;
a = *rA;
b = *rB;
- t = (signed64)a * (signed64)b;
+ t = (int64_t)a * (int64_t)b;
EV_SET_REG1(*rSh, *rS, t);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1144:EVX:e500:evmwumia %RS,%RA,%RB:Vector Multiply Word Unigned Modulo Integer and Accumulate
- unsigned32 a, b;
- unsigned64 t;
+ uint32_t a, b;
+ uint64_t t;
int movl;
a = *rA;
b = *rB;
- t = (signed64)a * (signed64)b;
+ t = (int64_t)a * (int64_t)b;
EV_SET_REG1_ACC(*rSh, *rS, t);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1363:EVX:e500:evmwssfaa %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional Add and Accumulate
- signed64 t1, t2;
- signed32 a, b;
+ int64_t t1, t2;
+ int32_t a, b;
int movl;
a = *rA;
b = *rB;
@@ -2039,8 +2039,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1371:EVX:e500:evmwsmfaa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional Add and Accumulate
- signed64 t1, t2;
- signed32 a, b;
+ int64_t t1, t2;
+ int32_t a, b;
int movl;
a = *rA;
b = *rB;
@@ -2050,29 +2050,29 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1369:EVX:e500:evmwsmiaa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer And and Accumulate
- signed64 t1, t2;
- signed32 a, b;
+ int64_t t1, t2;
+ int32_t a, b;
a = *rA;
b = *rB;
- t1 = (signed64)a * (signed64)b;
+ t1 = (int64_t)a * (int64_t)b;
t2 = ACC + t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1368:EVX:e500:evmwumiaa %RS,%RA,%RB:Vector Multiply Word Unsigned Modulo Integer Add and Accumulate
- unsigned64 t1, t2;
- unsigned32 a, b;
+ uint64_t t1, t2;
+ uint32_t a, b;
a = *rA;
b = *rB;
- t1 = (unsigned64)a * (unsigned64)b;
+ t1 = (uint64_t)a * (uint64_t)b;
t2 = ACC + t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1491:EVX:e500:evmwssfan %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional and Accumulate Negative
- signed64 t1, t2;
- signed32 a, b;
+ int64_t t1, t2;
+ int32_t a, b;
int movl;
a = *rA;
b = *rB;
@@ -2083,8 +2083,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.1499:EVX:e500:evmwsmfan %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional and Accumulate Negative
- signed64 t1, t2;
- signed32 a, b;
+ int64_t t1, t2;
+ int32_t a, b;
int movl;
a = *rA;
b = *rB;
@@ -2094,61 +2094,61 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1497:EVX:e500:evmwsmian %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer and Accumulate Negative
- signed64 t1, t2;
- signed32 a, b;
+ int64_t t1, t2;
+ int32_t a, b;
a = *rA;
b = *rB;
- t1 = (signed64)a * (signed64)b;
+ t1 = (int64_t)a * (int64_t)b;
t2 = ACC - t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1496:EVX:e500:evmwumian %RS,%RA,%RB:Vector Multiply Word Unsigned Modulo Integer and Accumulate Negative
- unsigned64 t1, t2;
- unsigned32 a, b;
+ uint64_t t1, t2;
+ uint32_t a, b;
a = *rA;
b = *rB;
- t1 = (unsigned64)a * (unsigned64)b;
+ t1 = (uint64_t)a * (uint64_t)b;
t2 = ACC - t1;
EV_SET_REG1_ACC(*rSh, *rS, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.1217:EVX:e500:evaddssiaaw %RS,%RA:Vector Add Signed Saturate Integer to Accumulator Word
- signed64 t1, t2;
- signed32 al, ah;
+ int64_t t1, t2;
+ int32_t al, ah;
int ovl, ovh;
al = *rA;
ah = *rAh;
- t1 = (signed64)EV_ACCHIGH + (signed64)ah;
- t2 = (signed64)EV_ACCLOW + (signed64)al;
+ t1 = (int64_t)EV_ACCHIGH + (int64_t)ah;
+ t2 = (int64_t)EV_ACCLOW + (int64_t)al;
ovh = EV_SAT_P_S32(t1);
ovl = EV_SAT_P_S32(t2);
- EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1 & ((unsigned64)1 << 32), 0x80000000, 0x7fffffff, t1),
- EV_SATURATE_ACC(ovl, t2 & ((unsigned64)1 << 32), 0x80000000, 0x7fffffff, t2));
+ EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1 & ((uint64_t)1 << 32), 0x80000000, 0x7fffffff, t1),
+ EV_SATURATE_ACC(ovl, t2 & ((uint64_t)1 << 32), 0x80000000, 0x7fffffff, t2));
EV_SET_SPEFSCR_OV(ovl, ovh);
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.0,21.1225:EVX:e500:evaddsmiaaw %RS,%RA:Vector Add Signed Modulo Integer to Accumulator Word
- signed64 t1, t2;
- signed32 al, ah;
+ int64_t t1, t2;
+ int32_t al, ah;
al = *rA;
ah = *rAh;
- t1 = (signed64)EV_ACCHIGH + (signed64)ah;
- t2 = (signed64)EV_ACCLOW + (signed64)al;
+ t1 = (int64_t)EV_ACCHIGH + (int64_t)ah;
+ t2 = (int64_t)EV_ACCLOW + (int64_t)al;
EV_SET_REG2_ACC(*rSh, *rS, t1, t2);
//printf("evaddsmiaaw: al %d ah %d t1 %qd t2 %qd\n", al, ah, t1, t2);
//printf("evaddsmiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.1216:EVX:e500:evaddusiaaw %RS,%RA:Vector Add Unsigned Saturate Integer to Accumulator Word
- signed64 t1, t2;
- unsigned32 al, ah;
+ int64_t t1, t2;
+ uint32_t al, ah;
int ovl, ovh;
al = *rA;
ah = *rAh;
- t1 = (signed64)EV_ACCHIGH + (signed64)ah;
- t2 = (signed64)EV_ACCLOW + (signed64)al;
+ t1 = (int64_t)EV_ACCHIGH + (int64_t)ah;
+ t2 = (int64_t)EV_ACCLOW + (int64_t)al;
ovh = EV_SAT_P_U32(t1);
ovl = EV_SAT_P_U32(t2);
EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, t1),
@@ -2159,24 +2159,24 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.0,21.1224:EVX:e500:evaddumiaaw %RS,%RA:Vector Add Unsigned Modulo Integer to Accumulator Word
- unsigned64 t1, t2;
- unsigned32 al, ah;
+ uint64_t t1, t2;
+ uint32_t al, ah;
al = *rA;
ah = *rAh;
- t1 = (unsigned64)EV_ACCHIGH + (unsigned64)ah;
+ t1 = (uint64_t)EV_ACCHIGH + (uint64_t)ah;
t2 = EV_ACCLOW + al;
EV_SET_REG2_ACC(*rSh, *rS, t1, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.1219:EVX:e500:evsubfssiaaw %RS,%RA:Vector Subtract Signed Saturate Integer to Accumulator Word
- signed64 t1, t2;
- signed32 al, ah;
+ int64_t t1, t2;
+ int32_t al, ah;
int ovl, ovh;
al = *rA;
ah = *rAh;
- t1 = (signed64)EV_ACCHIGH - (signed64)ah;
- t2 = (signed64)EV_ACCLOW - (signed64)al;
+ t1 = (int64_t)EV_ACCHIGH - (int64_t)ah;
+ t2 = (int64_t)EV_ACCLOW - (int64_t)al;
ovh = EV_SAT_P_S32(t1);
ovl = EV_SAT_P_S32(t2);
EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1, 0x80000000, 0x7fffffff, t1),
@@ -2185,24 +2185,24 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.0,21.1227:EVX:e500:evsubfsmiaaw %RS,%RA:Vector Subtract Signed Modulo Integer to Accumulator Word
- signed64 t1, t2;
- signed32 al, ah;
+ int64_t t1, t2;
+ int32_t al, ah;
al = *rA;
ah = *rAh;
- t1 = (signed64)EV_ACCHIGH - (signed64)ah;
- t2 = (signed64)EV_ACCLOW - (signed64)al;
+ t1 = (int64_t)EV_ACCHIGH - (int64_t)ah;
+ t2 = (int64_t)EV_ACCLOW - (int64_t)al;
EV_SET_REG2_ACC(*rSh, *rS, t1, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.1218:EVX:e500:evsubfusiaaw %RS,%RA:Vector Subtract Unsigned Saturate Integer to Accumulator Word
- signed64 t1, t2;
- unsigned32 al, ah;
+ int64_t t1, t2;
+ uint32_t al, ah;
int ovl, ovh;
al = *rA;
ah = *rAh;
- t1 = (signed64)EV_ACCHIGH - (signed64)ah;
- t2 = (signed64)EV_ACCLOW - (signed64)al;
+ t1 = (int64_t)EV_ACCHIGH - (int64_t)ah;
+ t2 = (int64_t)EV_ACCLOW - (int64_t)al;
ovh = EV_SAT_P_U32(t1);
ovl = EV_SAT_P_U32(t2);
EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0, t1),
@@ -2211,12 +2211,12 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.0,21.1226:EVX:e500:evsubfumiaaw %RS,%RA:Vector Subtract Unsigned Modulo Integer to Accumulator Word
- unsigned64 t1, t2;
- unsigned32 al, ah;
+ uint64_t t1, t2;
+ uint32_t al, ah;
al = *rA;
ah = *rAh;
- t1 = (unsigned64)EV_ACCHIGH - (unsigned64)ah;
- t2 = (unsigned64)EV_ACCLOW - (unsigned64)al;
+ t1 = (uint64_t)EV_ACCHIGH - (uint64_t)ah;
+ t2 = (uint64_t)EV_ACCLOW - (uint64_t)al;
EV_SET_REG2_ACC(*rSh, *rS, t1, t2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
@@ -2226,8 +2226,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.1222:EVX:e500:evdivws %RS,%RA,%RB:Vector Divide Word Signed
- signed32 dividendh, dividendl, divisorh, divisorl;
- signed32 w1, w2;
+ int32_t dividendh, dividendl, divisorh, divisorl;
+ int32_t w1, w2;
int ovh, ovl;
dividendh = *rAh;
dividendl = *rA;
@@ -2265,8 +2265,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.1223:EVX:e500:evdivwu %RS,%RA,%RB:Vector Divide Word Unsigned
- unsigned32 dividendh, dividendl, divisorh, divisorl;
- unsigned32 w1, w2;
+ uint32_t dividendh, dividendl, divisorh, divisorl;
+ uint32_t w1, w2;
int ovh, ovl;
dividendh = *rAh;
dividendl = *rA;
@@ -2296,21 +2296,21 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
#
0.4,6.RS,11.RA,16.0,21.644:EVX:e500:evfsabs %RS,%RA:Vector Floating-Point Absolute Value
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rAh & 0x7fffffff;
w2 = *rA & 0x7fffffff;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.645:EVX:e500:evfsnabs %RS,%RA:Vector Floating-Point Negative Absolute Value
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rAh | 0x80000000;
w2 = *rA | 0x80000000;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.646:EVX:e500:evfsneg %RS,%RA:Vector Floating-Point Negate
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rAh;
w2 = *rA;
w1 = (w1 & 0x7fffffff) | ((~w1) & 0x80000000);
@@ -2319,28 +2319,28 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.640:EVX:e500:evfsadd %RS,%RA,%RB:Vector Floating-Point Add
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = ev_fs_add (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor);
w2 = ev_fs_add (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor);
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.641:EVX:e500:evfssub %RS,%RA,%RB:Vector Floating-Point Subtract
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = ev_fs_sub (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor);
w2 = ev_fs_sub (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor);
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.648:EVX:e500:evfsmul %RS,%RA,%RB:Vector Floating-Point Multiply
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = ev_fs_mul (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor);
w2 = ev_fs_mul (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor);
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.649:EVX:e500:evfsdiv %RS,%RA,%RB:Vector Floating-Point Divide
- signed32 w1, w2;
+ int32_t w1, w2;
w1 = ev_fs_div (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fdbzh, spefscr_fgh, spefscr_fxh, processor);
w2 = ev_fs_div (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fdbz, spefscr_fg, spefscr_fx, processor);
EV_SET_REG2(*rSh, *rS, w1, w2);
@@ -2473,7 +2473,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.RS,11.0,16.RB,21.656:EVX:e500:evfscfui %RS,%RB:Vector Convert Floating-Point from Unsigned Integer
- unsigned32 f, w1, w2;
+ uint32_t f, w1, w2;
sim_fpu b;
sim_fpu_u32to (&b, *rBh, sim_fpu_round_default);
@@ -2485,7 +2485,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.664:EVX:e500:evfsctuiz %RS,%RB:Vector Convert Floating-Point to Unsigned Integer with Round toward Zero
- unsigned32 w1, w2;
+ uint32_t w1, w2;
sim_fpu b;
sim_fpu_32to (&b, *rBh);
@@ -2497,7 +2497,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.657:EVX:e500:evfscfsi %RS,%RB:Vector Convert Floating-Point from Signed Integer
- signed32 w1, w2;
+ int32_t w1, w2;
sim_fpu b, x, y;
sim_fpu_i32to (&b, *rBh, sim_fpu_round_default);
@@ -2509,7 +2509,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.658:EVX:e500:evfscfuf %RS,%RB:Vector Convert Floating-Point from Unsigned Fraction
- unsigned32 w1, w2, bh, bl;
+ uint32_t w1, w2, bh, bl;
sim_fpu b, x, y;
bh = *rBh;
if (bh == 0xffffffff)
@@ -2533,7 +2533,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.659:EVX:e500:evfscfsf %RS,%RB:Vector Convert Floating-Point from Signed Fraction
- unsigned32 w1, w2;
+ uint32_t w1, w2;
sim_fpu b, x, y;
sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default);
@@ -2550,7 +2550,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.660:EVX:e500:evfsctui %RS,%RB:Vector Convert Floating-Point to Unsigned Integer
- unsigned32 w1, w2;
+ uint32_t w1, w2;
sim_fpu b;
sim_fpu_32to (&b, *rBh);
@@ -2562,7 +2562,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.661:EVX:e500:evfsctsi %RS,%RB:Vector Convert Floating-Point to Signed Integer
- signed32 w1, w2;
+ int32_t w1, w2;
sim_fpu b;
sim_fpu_32to (&b, *rBh);
@@ -2574,7 +2574,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.666:EVX:e500:evfsctsiz %RS,%RB:Vector Convert Floating-Point to Signed Integer with Round toward Zero
- signed32 w1, w2;
+ int32_t w1, w2;
sim_fpu b;
sim_fpu_32to (&b, *rBh);
@@ -2586,7 +2586,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.662:EVX:e500:evfsctuf %RS,%RB:Vector Convert Floating-Point to Unsigned Fraction
- unsigned32 w1, w2;
+ uint32_t w1, w2;
sim_fpu b, x, y;
sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default);
@@ -2603,7 +2603,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.663:EVX:e500:evfsctsf %RS,%RB:Vector Convert Floating-Point to Signed Fraction
- signed32 w1, w2;
+ int32_t w1, w2;
sim_fpu b, x, y;
sim_fpu_32to (&y, *rBh);
@@ -2621,46 +2621,46 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.0,21.708:EVX:e500:efsabs %RS,%RA:Floating-Point Absolute Value
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rSh;
w2 = *rA & 0x7fffffff;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.709:EVX:e500:efsnabs %RS,%RA:Floating-Point Negative Absolute Value
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rSh;
w2 = *rA | 0x80000000;
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.0,21.710:EVX:e500:efsneg %RS,%RA:Floating-Point Negate
- unsigned32 w1, w2;
+ uint32_t w1, w2;
w1 = *rSh;
w2 = (*rA & 0x7fffffff) | ((~*rA) & 0x80000000);
EV_SET_REG2(*rSh, *rS, w1, w2);
PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0);
0.4,6.RS,11.RA,16.RB,21.704:EVX:e500:efsadd %RS,%RA,%RB:Floating-Point Add
- unsigned32 w;
+ uint32_t w;
w = ev_fs_add (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor);
EV_SET_REG(*rS, w);
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.705:EVX:e500:efssub %RS,%RA,%RB:Floating-Point Subtract
- unsigned32 w;
+ uint32_t w;
w = ev_fs_sub (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor);
EV_SET_REG(*rS, w);
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.712:EVX:e500:efsmul %RS,%RA,%RB:Floating-Point Multiply
- unsigned32 w;
+ uint32_t w;
w = ev_fs_mul (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor);
EV_SET_REG(*rS, w);
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
0.4,6.RS,11.RA,16.RB,21.713:EVX:e500:efsdiv %RS,%RA,%RB:Floating-Point Divide
- unsigned32 w;
+ uint32_t w;
w = ev_fs_div (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fdbz, spefscr_fg, spefscr_fx, processor);
EV_SET_REG(*rS, w);
PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr);
@@ -2750,7 +2750,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK);
0.4,6.RS,11.0,16.RB,21.721:EVX:e500:efscfsi %RS,%RB:Convert Floating-Point from Signed Integer
- signed32 f, w1, w2;
+ int32_t f, w1, w2;
sim_fpu b;
w1 = *rSh;
sim_fpu_i32to (&b, *rB, sim_fpu_round_default);
@@ -2759,7 +2759,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.720:EVX:e500:efscfui %RS,%RB:Convert Floating-Point from Unsigned Integer
- unsigned32 w1, w2;
+ uint32_t w1, w2;
sim_fpu b;
w1 = *rSh;
sim_fpu_u32to (&b, *rB, sim_fpu_round_default);
@@ -2768,7 +2768,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.723:EVX:e500:efscfsf %RS,%RB:Convert Floating-Point from Signed Fraction
- unsigned32 w1, w2;
+ uint32_t w1, w2;
sim_fpu b, x, y;
w1 = *rSh;
sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default);
@@ -2779,7 +2779,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.722:EVX:e500:efscfuf %RS,%RB:Convert Floating-Point from Unsigned Fraction
- unsigned32 w1, w2, bl;
+ uint32_t w1, w2, bl;
sim_fpu b, x, y;
w1 = *rSh;
bl = *rB;
@@ -2795,8 +2795,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.725:EVX:e500:efsctsi %RS,%RB:Convert Floating-Point to Signed Integer
- signed64 temp;
- signed32 w1, w2;
+ int64_t temp;
+ int32_t w1, w2;
sim_fpu b;
w1 = *rSh;
sim_fpu_32to (&b, *rB);
@@ -2805,8 +2805,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.730:EVX:e500:efsctsiz %RS,%RB:Convert Floating-Point to Signed Integer with Round toward Zero
- signed64 temp;
- signed32 w1, w2;
+ int64_t temp;
+ int32_t w1, w2;
sim_fpu b;
w1 = *rSh;
sim_fpu_32to (&b, *rB);
@@ -2815,8 +2815,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.724:EVX:e500:efsctui %RS,%RB:Convert Floating-Point to Unsigned Integer
- unsigned64 temp;
- signed32 w1, w2;
+ uint64_t temp;
+ int32_t w1, w2;
sim_fpu b;
w1 = *rSh;
sim_fpu_32to (&b, *rB);
@@ -2825,8 +2825,8 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.728:EVX:e500:efsctuiz %RS,%RB:Convert Floating-Point to Unsigned Integer with Round toward Zero
- unsigned64 temp;
- signed32 w1, w2;
+ uint64_t temp;
+ int32_t w1, w2;
sim_fpu b;
w1 = *rSh;
sim_fpu_32to (&b, *rB);
@@ -2835,7 +2835,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.727:EVX:e500:efsctsf %RS,%RB:Convert Floating-Point to Signed Fraction
- unsigned32 w1, w2;
+ uint32_t w1, w2;
sim_fpu b, x, y;
w1 = *rSh;
sim_fpu_32to (&y, *rB);
@@ -2847,7 +2847,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0);
0.4,6.RS,11.0,16.RB,21.726:EVX:e500:efsctuf %RS,%RB:Convert Floating-Point to Unsigned Fraction
- unsigned32 w1, w2;
+ uint32_t w1, w2;
sim_fpu b, x, y;
w1 = *rSh;
sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default);
@@ -2863,7 +2863,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
#
0.4,6.RS,11.RA,16.UIMM,21.769:EVX:e500:evldd %RS,%RA,%UIMM:Vector Load Double Word into Double Word
- unsigned64 m;
+ uint64_t m;
unsigned_word b;
unsigned_word EA;
if (RA_is_0) b = 0;
@@ -2875,7 +2875,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0);
0.4,6.RS,11.RA,16.RB,21.768:EVX:e500:evlddx %RS,%RA,%RB:Vector Load Double Word into Double Word Indexed
- unsigned64 m;
+ uint64_t m;
unsigned_word b;
unsigned_word EA;
if (RA_is_0) b = 0;
@@ -2888,7 +2888,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.771:EVX:e500:evldw %RS,%RA,%UIMM:Vector Load Double into Two Words
unsigned_word b;
unsigned_word EA;
- unsigned32 w1, w2;
+ uint32_t w1, w2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 3);
@@ -2900,7 +2900,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.770:EVX:e500:evldwx %RS,%RA,%RB:Vector Load Double into Two Words Indexed
unsigned_word b;
unsigned_word EA;
- unsigned32 w1, w2;
+ uint32_t w1, w2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -2912,7 +2912,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.773:EVX:e500:evldh %RS,%RA,%UIMM:Vector Load Double into 4 Half Words
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2, h3, h4;
+ uint16_t h1, h2, h3, h4;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 3);
@@ -2926,7 +2926,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.772:EVX:e500:evldhx %RS,%RA,%RB:Vector Load Double into 4 Half Words Indexed
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2, h3, h4;
+ uint16_t h1, h2, h3, h4;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -2940,7 +2940,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.785:EVX:e500:evlwhe %RS,%RA,%UIMM:Vector Load Word into Two Half Words Even
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2, h3, h4;
+ uint16_t h1, h2, h3, h4;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 2);
@@ -2954,7 +2954,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.784:EVX:e500:evlwhex %RS,%RA,%RB:Vector Load Word into Two Half Words Even Indexed
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2, h3, h4;
+ uint16_t h1, h2, h3, h4;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -2968,7 +2968,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.789:EVX:e500:evlwhou %RS,%RA,%UIMM:Vector Load Word into Two Half Words Odd Unsigned zero-extended
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2, h3, h4;
+ uint16_t h1, h2, h3, h4;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 2);
@@ -2982,7 +2982,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.788:EVX:e500:evlwhoux %RS,%RA,%RB:Vector Load Word into Two Half Words Odd Unsigned Indexed zero-extended
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2, h3, h4;
+ uint16_t h1, h2, h3, h4;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -2996,7 +2996,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.791:EVX:e500:evlwhos %RS,%RA,%UIMM:Vector Load Word into Half Words Odd Signed with sign extension
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2, h3, h4;
+ uint16_t h1, h2, h3, h4;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 2);
@@ -3016,7 +3016,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.790:EVX:e500:evlwhosx %RS,%RA,%RB:Vector Load Word into Half Words Odd Signed Indexed with sign extension
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2, h3, h4;
+ uint16_t h1, h2, h3, h4;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3036,7 +3036,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.793:EVX:e500:evlwwsplat %RS,%RA,%UIMM:Vector Load Word into Word and Splat
unsigned_word b;
unsigned_word EA;
- unsigned32 w1;
+ uint32_t w1;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 2);
@@ -3047,7 +3047,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.792:EVX:e500:evlwwsplatx %RS,%RA,%RB:Vector Load Word into Word and Splat Indexed
unsigned_word b;
unsigned_word EA;
- unsigned32 w1;
+ uint32_t w1;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3058,7 +3058,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.797:EVX:e500:evlwhsplat %RS,%RA,%UIMM:Vector Load Word into 2 Half Words and Splat
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2;
+ uint16_t h1, h2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 2);
@@ -3070,7 +3070,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.796:EVX:e500:evlwhsplatx %RS,%RA,%RB:Vector Load Word into 2 Half Words and Splat Indexed
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2;
+ uint16_t h1, h2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3082,7 +3082,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.777:EVX:e500:evlhhesplat %RS,%RA,%UIMM:Vector Load Half Word into Half Words Even and Splat
unsigned_word b;
unsigned_word EA;
- unsigned16 h;
+ uint16_t h;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 1);
@@ -3093,7 +3093,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.776:EVX:e500:evlhhesplatx %RS,%RA,%RB:Vector Load Half Word into Half Words Even and Splat Indexed
unsigned_word b;
unsigned_word EA;
- unsigned16 h;
+ uint16_t h;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3104,7 +3104,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.781:EVX:e500:evlhhousplat %RS,%RA,%UIMM:Vector Load Half Word into Half Word Odd Unsigned and Splat
unsigned_word b;
unsigned_word EA;
- unsigned16 h;
+ uint16_t h;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 1);
@@ -3115,7 +3115,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.780:EVX:e500:evlhhousplatx %RS,%RA,%RB:Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed
unsigned_word b;
unsigned_word EA;
- unsigned16 h;
+ uint16_t h;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3126,7 +3126,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.783:EVX:e500:evlhhossplat %RS,%RA,%UIMM:Vector Load Half Word into Half Word Odd Signed and Splat
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2;
+ uint16_t h1, h2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 1);
@@ -3141,7 +3141,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.782:EVX:e500:evlhhossplatx %RS,%RA,%RB:Vector Load Half Word into Half Word Odd Signed and Splat Indexed
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2;
+ uint16_t h1, h2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3177,7 +3177,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.803:EVX:e500:evstdw %RS,%RA,%UIMM:Vector Store Double of Two Words
unsigned_word b;
unsigned_word EA;
- unsigned32 w1, w2;
+ uint32_t w1, w2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 3);
@@ -3190,7 +3190,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.802:EVX:e500:evstdwx %RS,%RA,%RB:Vector Store Double of Two Words Indexed
unsigned_word b;
unsigned_word EA;
- unsigned32 w1, w2;
+ uint32_t w1, w2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3203,7 +3203,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.805:EVX:e500:evstdh %RS,%RA,%UIMM:Vector Store Double of Four Half Words
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2, h3, h4;
+ uint16_t h1, h2, h3, h4;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 3);
@@ -3220,7 +3220,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.804:EVX:e500:evstdhx %RS,%RA,%RB:Vector Store Double of Four Half Words Indexed
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2, h3, h4;
+ uint16_t h1, h2, h3, h4;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3237,7 +3237,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.825:EVX:e500:evstwwe %RS,%RA,%UIMM:Vector Store Word of Word from Even
unsigned_word b;
unsigned_word EA;
- unsigned32 w;
+ uint32_t w;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 3);
@@ -3248,7 +3248,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.824:EVX:e500:evstwwex %RS,%RA,%RB:Vector Store Word of Word from Even Indexed
unsigned_word b;
unsigned_word EA;
- unsigned32 w;
+ uint32_t w;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3259,7 +3259,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.829:EVX:e500:evstwwo %RS,%RA,%UIMM:Vector Store Word of Word from Odd
unsigned_word b;
unsigned_word EA;
- unsigned32 w;
+ uint32_t w;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 3);
@@ -3270,7 +3270,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.828:EVX:e500:evstwwox %RS,%RA,%RB:Vector Store Word of Word from Odd Indexed
unsigned_word b;
unsigned_word EA;
- unsigned32 w;
+ uint32_t w;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3281,7 +3281,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.817:EVX:e500:evstwhe %RS,%RA,%UIMM:Vector Store Word of Two Half Words from Even
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2;
+ uint16_t h1, h2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 3);
@@ -3294,7 +3294,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.816:EVX:e500:evstwhex %RS,%RA,%RB:Vector Store Word of Two Half Words from Even Indexed
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2;
+ uint16_t h1, h2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
@@ -3307,7 +3307,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.UIMM,21.821:EVX:e500:evstwho %RS,%RA,%UIMM:Vector Store Word of Two Half Words from Odd
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2;
+ uint16_t h1, h2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + (UIMM << 3);
@@ -3320,7 +3320,7 @@ void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr
0.4,6.RS,11.RA,16.RB,21.820:EVX:e500:evstwhox %RS,%RA,%RB:Vector Store Word of Two Half Words from Odd Indexed
unsigned_word b;
unsigned_word EA;
- unsigned16 h1, h2;
+ uint16_t h1, h2;
if (RA_is_0) b = 0;
else b = *rA;
EA = b + *rB;
diff --git a/sim/ppc/e500_expression.h b/sim/ppc/e500_expression.h
index 81b834cd8292..1a27bb189e85 100644
--- a/sim/ppc/e500_expression.h
+++ b/sim/ppc/e500_expression.h
@@ -28,7 +28,7 @@
#define EV_SET_REG4_ACC(sh, sl, h0, h1, h2, h3) do { \
(sh) = (((h0) & 0xffff) << 16) | ((h1) & 0xffff); \
(sl) = (((h2) & 0xffff) << 16) | ((h3) & 0xffff); \
- ACC = ((unsigned64)(sh) << 32) | (sl & 0xffffffff); \
+ ACC = ((uint64_t)(sh) << 32) | (sl & 0xffffffff); \
} while (0)
#define EV_SET_REG2(sh, sl, dh, dl) do { \
@@ -38,15 +38,15 @@
#define EV_SET_REG2_ACC(sh, sl, dh, dl) do { \
(sh) = (dh) & 0xffffffff; \
(sl) = (dl) & 0xffffffff; \
- ACC = ((unsigned64)(sh) << 32) | ((sl) & 0xffffffff); \
+ ACC = ((uint64_t)(sh) << 32) | ((sl) & 0xffffffff); \
} while (0)
#define EV_SET_REG1(sh, sl, d) do { \
- (sh) = ((unsigned64)(d) >> 32) & 0xffffffff; \
+ (sh) = ((uint64_t)(d) >> 32) & 0xffffffff; \
(sl) = (d) & 0xffffffff; \
} while (0)
#define EV_SET_REG1_ACC(sh, sl, d) do { \
- (sh) = ((unsigned64)(d) >> 32) & 0xffffffff; \
+ (sh) = ((uint64_t)(d) >> 32) & 0xffffffff; \
(sl) = (d) & 0xffffffff; \
ACC = (d); \
} while (0)
@@ -56,12 +56,12 @@
} while (0)
/* get the low or high half word of a word */
-#define EV_LOHALF(x) ((unsigned32)(x) & 0xffff)
-#define EV_HIHALF(x) (((unsigned32)(x) >> 16) & 0xffff)
+#define EV_LOHALF(x) ((uint32_t)(x) & 0xffff)
+#define EV_HIHALF(x) (((uint32_t)(x) >> 16) & 0xffff)
/* partially visible accumulator accessors */
#define EV_SET_ACC(rh, rl) \
- ACC = ((unsigned64)(rh) << 32) | ((rl) & 0xffffffff)
+ ACC = ((uint64_t)(rh) << 32) | ((rl) & 0xffffffff)
#define EV_ACCLOW (ACC & 0xffffffff)
#define EV_ACCHIGH ((ACC >> 32) & 0xffffffff)
@@ -86,11 +86,11 @@
| (((x) & 0x8000) >> 15)
/* saturation helpers */
-#define EV_MUL16_SSF(a,b) ((signed64)((signed32)(signed16)(a) * (signed32)(signed16)(b)) << 1)
+#define EV_MUL16_SSF(a,b) ((int64_t)((int32_t)(int16_t)(a) * (int32_t)(int16_t)(b)) << 1)
/* this one loses the top sign bit; be careful */
-#define EV_MUL32_SSF(a,b) (((signed64)(signed32)(a) * (signed64)(signed32)(b)) << 1)
-#define EV_SAT_P_S32(x) ((((signed64)(x)) < -0x80000000LL) || (((signed64)(x)) > 0x7fffffffLL))
-#define EV_SAT_P_U32(x) ((((signed64)(x)) < -0LL) || (((signed64)(x)) > 0xffffffffLL))
+#define EV_MUL32_SSF(a,b) (((int64_t)(int32_t)(a) * (int64_t)(int32_t)(b)) << 1)
+#define EV_SAT_P_S32(x) ((((int64_t)(x)) < -0x80000000LL) || (((int64_t)(x)) > 0x7fffffffLL))
+#define EV_SAT_P_U32(x) ((((int64_t)(x)) < -0LL) || (((int64_t)(x)) > 0xffffffffLL))
#define EV_SATURATE(flag, sat_val, val) \
((flag) ? (sat_val) : (val))
@@ -116,7 +116,7 @@
EV_SET_SPEFSCR(SPREG(spr_spefscr) | (s))
#define EV_SET_SPEFSCR_OV(l,h) do { \
- unsigned32 _sPefScR = SPREG(spr_spefscr); \
+ uint32_t _sPefScR = SPREG(spr_spefscr); \
if (l) \
_sPefScR |= spefscr_ov | spefscr_sov; \
else \
diff --git a/sim/ppc/e500_registers.h b/sim/ppc/e500_registers.h
index cc3342f3dc2d..d02bcc9ff352 100644
--- a/sim/ppc/e500_registers.h
+++ b/sim/ppc/e500_registers.h
@@ -22,7 +22,7 @@
/* e500 accumulator. */
-typedef unsigned64 accreg;
+typedef uint64_t accreg;
enum {
msr_e500_spu_enable = BIT(38)
@@ -81,4 +81,4 @@ struct e500_regs {
We need to cast the gpr value to an unsigned type so that it
doesn't get sign-extended when it's or-ed with a 64-bit value; that
would wipe out the upper 32 bits of the register's value. */
-#define EVR(N) ((((unsigned64)GPRH(N)) << 32) | (unsigned32) GPR(N))
+#define EVR(N) ((((uint64_t)GPRH(N)) << 32) | (uint32_t) GPR(N))
diff --git a/sim/ppc/emul_chirp.c b/sim/ppc/emul_chirp.c
index 2c9316cf280b..a72a34e85287 100644
--- a/sim/ppc/emul_chirp.c
+++ b/sim/ppc/emul_chirp.c
@@ -1381,7 +1381,7 @@ chirp_emul_milliseconds(os_emul_data *data,
/*out*/
unsigned_cell ms;
} args;
- unsigned64 time;
+ uint64_t time;
/* read in the arguments */
if (chirp_read_t2h_args(&args, sizeof(args), 1, 1, data, processor, cia))
return -1;
@@ -1465,12 +1465,12 @@ static chirp_services services[] = {
typedef struct _chirp_note_desc {
- signed32 real_mode;
- signed32 real_base;
- signed32 real_size;
- signed32 virt_base;
- signed32 virt_size;
- signed32 load_base;
+ int32_t real_mode;
+ int32_t real_base;
+ int32_t real_size;
+ int32_t virt_base;
+ int32_t virt_size;
+ int32_t load_base;
} chirp_note_desc;
typedef enum {
@@ -1484,9 +1484,9 @@ typedef struct _chirp_note {
} chirp_note;
typedef struct _chirp_note_head {
- unsigned32 namesz;
- unsigned32 descsz;
- unsigned32 type;
+ uint32_t namesz;
+ uint32_t descsz;
+ uint32_t type;
} chirp_note_head;
static void
@@ -1519,7 +1519,7 @@ map_over_chirp_note(bfd *image,
printf_filtered("chirp: note name (%s) not `PowerPC'\n", name);
}
/* check the size */
- if (head.descsz == sizeof(note->desc) - sizeof(signed32)) {
+ if (head.descsz == sizeof(note->desc) - sizeof(int32_t)) {
sim_io_printf_filtered("chirp: note descriptor missing load-base\n");
}
else if (head.descsz != sizeof(note->desc)) {
@@ -1543,7 +1543,7 @@ map_over_chirp_note(bfd *image,
if (head.descsz == sizeof(note->desc))
note->desc.load_base = bfd_get_32(image, (void*)¬e->desc.load_base);
else
- note->desc.load_base = (signed32)-1;
+ note->desc.load_base = (int32_t)-1;
}
}
@@ -1648,7 +1648,7 @@ emul_chirp_create(device *root,
/* resolve real-base */
if (note.found == note_correct
- && note.desc.real_base != (signed32)-1)
+ && note.desc.real_base != (int32_t)-1)
chirp->real_base = note.desc.real_base;
else if (tree_find_property(root, "/options/real-base") != NULL)
chirp->real_base = tree_find_integer_property(root, "/options/real-base");
@@ -1664,7 +1664,7 @@ emul_chirp_create(device *root,
/* resolve real-size */
if (note.found == note_correct
- && note.desc.real_size != (signed32)-1
+ && note.desc.real_size != (int32_t)-1
&& note.desc.real_size != 0
&& chirp->real_size > note.desc.real_size)
error("chirp: insufficient physical memory for firmware\n");
@@ -1697,7 +1697,7 @@ emul_chirp_create(device *root,
/* resolve virt-size */
chirp->virt_size = chirp->real_size;
if (note.found == note_correct
- && note.desc.virt_size != (signed32)-1
+ && note.desc.virt_size != (int32_t)-1
&& note.desc.virt_size != 0
&& !chirp->real_mode
&& chirp->virt_size > note.desc.virt_size)
@@ -1712,7 +1712,7 @@ emul_chirp_create(device *root,
/* resolve load-base */
if (note.found == note_correct
- && note.desc.load_base != (signed32)-1)
+ && note.desc.load_base != (int32_t)-1)
chirp->load_base = note.desc.load_base;
else if (tree_find_property(root, "/options/load-base") != NULL)
chirp->load_base = tree_find_integer_property(root, "/options/load-base");
diff --git a/sim/ppc/emul_generic.c b/sim/ppc/emul_generic.c
index 9d57bc6c01ae..031973008fa1 100644
--- a/sim/ppc/emul_generic.c
+++ b/sim/ppc/emul_generic.c
@@ -58,12 +58,12 @@ emul_syscall_exit(emul_syscall *emul,
}
-INLINE_EMUL_GENERIC unsigned64
+INLINE_EMUL_GENERIC uint64_t
emul_read_gpr64(cpu *processor,
int g)
{
- unsigned32 hi;
- unsigned32 lo;
+ uint32_t hi;
+ uint32_t lo;
if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) {
hi = cpu_registers(processor)->gpr[g];
lo = cpu_registers(processor)->gpr[g+1];
@@ -79,10 +79,10 @@ emul_read_gpr64(cpu *processor,
INLINE_EMUL_GENERIC void
emul_write_gpr64(cpu *processor,
int g,
- unsigned64 val)
+ uint64_t val)
{
- unsigned32 hi = EXTRACTED64(val, 0, 31);
- unsigned32 lo = EXTRACTED64(val, 32, 63);
+ uint32_t hi = EXTRACTED64(val, 0, 31);
+ uint32_t lo = EXTRACTED64(val, 32, 63);
if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) {
cpu_registers(processor)->gpr[g] = hi;
cpu_registers(processor)->gpr[g+1] = lo;
diff --git a/sim/ppc/emul_generic.h b/sim/ppc/emul_generic.h
index 8e0ebcaabd33..81fcb51019a2 100644
--- a/sim/ppc/emul_generic.h
+++ b/sim/ppc/emul_generic.h
@@ -111,14 +111,14 @@ INLINE_EMUL_GENERIC void emul_do_system_call
unsigned_word cia);
-INLINE_EMUL_GENERIC unsigned64 emul_read_gpr64
+INLINE_EMUL_GENERIC uint64_t emul_read_gpr64
(cpu *processor,
int g);
INLINE_EMUL_GENERIC void emul_write_gpr64
(cpu *processor,
int g,
- unsigned64 val);
+ uint64_t val);
INLINE_EMUL_GENERIC void emul_write_status
(cpu *processor,
diff --git a/sim/ppc/emul_unix.c b/sim/ppc/emul_unix.c
index 191e26abd8ee..57691d4befcd 100644
--- a/sim/ppc/emul_unix.c
+++ b/sim/ppc/emul_unix.c
@@ -150,13 +150,13 @@ struct _os_emul_data {
/* Structures that are common agmonst the UNIX varients */
struct unix_timeval {
- signed32 tv_sec; /* seconds */
- signed32 tv_usec; /* microseconds */
+ int32_t tv_sec; /* seconds */
+ int32_t tv_usec; /* microseconds */
};
struct unix_timezone {
- signed32 tz_minuteswest; /* minutes west of Greenwich */
- signed32 tz_dsttime; /* type of dst correction */
+ int32_t tz_minuteswest; /* minutes west of Greenwich */
+ int32_t tz_dsttime; /* type of dst correction */
};
#define UNIX_RUSAGE_SELF 0
@@ -166,20 +166,20 @@ struct unix_timezone {
struct unix_rusage {
struct unix_timeval ru_utime; /* user time used */
struct unix_timeval ru_stime; /* system time used */
- signed32 ru_maxrss; /* maximum resident set size */
- signed32 ru_ixrss; /* integral shared memory size */
- signed32 ru_idrss; /* integral unshared data size */
- signed32 ru_isrss; /* integral unshared stack size */
- signed32 ru_minflt; /* any page faults not requiring I/O */
- signed32 ru_majflt; /* any page faults requiring I/O */
- signed32 ru_nswap; /* swaps */
- signed32 ru_inblock; /* block input operations */
- signed32 ru_oublock; /* block output operations */
- signed32 ru_msgsnd; /* messages sent */
- signed32 ru_msgrcv; /* messages received */
- signed32 ru_nsignals; /* signals received */
- signed32 ru_nvcsw; /* voluntary context switches */
- signed32 ru_nivcsw; /* involuntary " */
+ int32_t ru_maxrss; /* maximum resident set size */
+ int32_t ru_ixrss; /* integral shared memory size */
+ int32_t ru_idrss; /* integral unshared data size */
+ int32_t ru_isrss; /* integral unshared stack size */
+ int32_t ru_minflt; /* any page faults not requiring I/O */
+ int32_t ru_majflt; /* any page faults requiring I/O */
+ int32_t ru_nswap; /* swaps */
+ int32_t ru_inblock; /* block input operations */
+ int32_t ru_oublock; /* block output operations */
+ int32_t ru_msgsnd; /* messages sent */
+ int32_t ru_msgrcv; /* messages received */
+ int32_t ru_nsignals; /* signals received */
+ int32_t ru_nvcsw; /* voluntary context switches */
+ int32_t ru_nivcsw; /* involuntary " */
};
@@ -1051,15 +1051,15 @@ emul_unix_create(device *root,
/* Solaris specific implementation */
-typedef signed32 solaris_uid_t;
-typedef signed32 solaris_gid_t;
-typedef signed32 solaris_off_t;
-typedef signed32 solaris_pid_t;
-typedef signed32 solaris_time_t;
-typedef unsigned32 solaris_dev_t;
-typedef unsigned32 solaris_ino_t;
-typedef unsigned32 solaris_mode_t;
-typedef unsigned32 solaris_nlink_t;
+typedef int32_t solaris_uid_t;
+typedef int32_t solaris_gid_t;
+typedef int32_t solaris_off_t;
+typedef int32_t solaris_pid_t;
+typedef int32_t solaris_time_t;
+typedef uint32_t solaris_dev_t;
+typedef uint32_t solaris_ino_t;
+typedef uint32_t solaris_mode_t;
+typedef uint32_t solaris_nlink_t;
#ifdef HAVE_SYS_STAT_H
#define SOLARIS_ST_FSTYPSZ 16 /* array size for file system type name */
@@ -1071,23 +1071,23 @@ typedef unsigned32 solaris_nlink_t;
struct solaris_stat {
solaris_dev_t st_dev;
- signed32 st_pad1[3]; /* reserved for network id */
+ int32_t st_pad1[3]; /* reserved for network id */
solaris_ino_t st_ino;
solaris_mode_t st_mode;
solaris_nlink_t st_nlink;
solaris_uid_t st_uid;
solaris_gid_t st_gid;
solaris_dev_t st_rdev;
- signed32 st_pad2[2];
+ int32_t st_pad2[2];
solaris_off_t st_size;
- signed32 st_pad3; /* future off_t expansion */
+ int32_t st_pad3; /* future off_t expansion */
struct unix_timeval st_atim;
struct unix_timeval st_mtim;
struct unix_timeval st_ctim;
- signed32 st_blksize;
- signed32 st_blocks;
+ int32_t st_blksize;
+ int32_t st_blocks;
char st_fstype[SOLARIS_ST_FSTYPSZ];
- signed32 st_pad4[8]; /* expansion area */
+ int32_t st_pad4[8]; /* expansion area */
};
/* Convert from host stat structure to solaris stat structure */
@@ -1264,12 +1264,12 @@ do_solaris_fstat(os_emul_data *emul,
/* Convert to/from host termio structure */
struct solaris_termio {
- unsigned16 c_iflag; /* input modes */
- unsigned16 c_oflag; /* output modes */
- unsigned16 c_cflag; /* control modes */
- unsigned16 c_lflag; /* line discipline modes */
- unsigned8 c_line; /* line discipline */
- unsigned8 c_cc[SOLARIS_NCC]; /* control chars */
+ uint16_t c_iflag; /* input modes */
+ uint16_t c_oflag; /* output modes */
+ uint16_t c_cflag; /* control modes */
+ uint16_t c_lflag; /* line discipline modes */
+ uint8_t c_line; /* line discipline */
+ uint8_t c_cc[SOLARIS_NCC]; /* control chars */
};
STATIC_INLINE_EMUL_UNIX void
@@ -1339,9 +1339,9 @@ convert_to_solaris_termio(unsigned_word addr,
#ifdef HAVE_TERMIOS_STRUCTURE
/* Convert to/from host termios structure */
-typedef unsigned32 solaris_tcflag_t;
-typedef unsigned8 solaris_cc_t;
-typedef unsigned32 solaris_speed_t;
+typedef uint32_t solaris_tcflag_t;
+typedef uint8_t solaris_cc_t;
+typedef uint32_t solaris_speed_t;
struct solaris_termios {
solaris_tcflag_t c_iflag;
@@ -2002,20 +2002,20 @@ const os_emul emul_solaris = {
/* Linux specific implementation */
-typedef unsigned32 linux_dev_t;
-typedef unsigned32 linux_ino_t;
-typedef unsigned32 linux_mode_t;
-typedef unsigned16 linux_nlink_t;
-typedef signed32 linux_off_t;
-typedef signed32 linux_pid_t;
-typedef unsigned32 linux_uid_t;
-typedef unsigned32 linux_gid_t;
-typedef unsigned32 linux_size_t;
-typedef signed32 linux_ssize_t;
-typedef signed32 linux_ptrdiff_t;
-typedef signed32 linux_time_t;
-typedef signed32 linux_clock_t;
-typedef signed32 linux_daddr_t;
+typedef uint32_t linux_dev_t;
+typedef uint32_t linux_ino_t;
+typedef uint32_t linux_mode_t;
+typedef uint16_t linux_nlink_t;
+typedef int32_t linux_off_t;
+typedef int32_t linux_pid_t;
+typedef uint32_t linux_uid_t;
+typedef uint32_t linux_gid_t;
+typedef uint32_t linux_size_t;
+typedef int32_t linux_ssize_t;
+typedef int32_t linux_ptrdiff_t;
+typedef int32_t linux_time_t;
+typedef int32_t linux_clock_t;
+typedef int32_t linux_daddr_t;
#ifdef HAVE_SYS_STAT_H
/* For the PowerPC, don't both with the 'old' stat structure, since there
@@ -2030,16 +2030,16 @@ struct linux_stat {
linux_gid_t st_gid;
linux_dev_t st_rdev;
linux_off_t st_size;
- unsigned32 st_blksize;
- unsigned32 st_blocks;
- unsigned32 st_atimx; /* don't use st_{a,c,m}time, that might a macro */
- unsigned32 __unused1; /* defined by the host's stat.h */
- unsigned32 st_mtimx;
- unsigned32 __unused2;
- unsigned32 st_ctimx;
- unsigned32 __unused3;
- unsigned32 __unused4;
- unsigned32 __unused5;
+ uint32_t st_blksize;
+ uint32_t st_blocks;
+ uint32_t st_atimx; /* don't use st_{a,c,m}time, that might a macro */
+ uint32_t __unused1; /* defined by the host's stat.h */
+ uint32_t st_mtimx;
+ uint32_t __unused2;
+ uint32_t st_ctimx;
+ uint32_t __unused3;
+ uint32_t __unused4;
+ uint32_t __unused5;
};
/* Convert from host stat structure to solaris stat structure */
@@ -2237,12 +2237,12 @@ do_linux_fstat(os_emul_data *emul,
/* Convert to/from host termio structure */
struct linux_termio {
- unsigned16 c_iflag; /* input modes */
- unsigned16 c_oflag; /* output modes */
- unsigned16 c_cflag; /* control modes */
- unsigned16 c_lflag; /* line discipline modes */
- unsigned8 c_line; /* line discipline */
- unsigned8 c_cc[LINUX_NCC]; /* control chars */
+ uint16_t c_iflag; /* input modes */
+ uint16_t c_oflag; /* output modes */
+ uint16_t c_cflag; /* control modes */
+ uint16_t c_lflag; /* line discipline modes */
+ uint8_t c_line; /* line discipline */
+ uint8_t c_cc[LINUX_NCC]; /* control chars */
};
STATIC_INLINE_EMUL_UNIX void
@@ -2319,9 +2319,9 @@ convert_to_linux_termio(unsigned_word addr,
#ifdef HAVE_TERMIOS_STRUCTURE
/* Convert to/from host termios structure */
-typedef unsigned32 linux_tcflag_t;
-typedef unsigned8 linux_cc_t;
-typedef unsigned32 linux_speed_t;
+typedef uint32_t linux_tcflag_t;
+typedef uint8_t linux_cc_t;
+typedef uint32_t linux_speed_t;
struct linux_termios {
linux_tcflag_t c_iflag;
@@ -2330,8 +2330,8 @@ struct linux_termios {
linux_tcflag_t c_lflag;
linux_cc_t c_cc[LINUX_NCCS];
linux_cc_t c_line;
- signed32 c_ispeed;
- signed32 c_ospeed;
+ int32_t c_ispeed;
+ int32_t c_ospeed;
};
STATIC_INLINE_EMUL_UNIX void
diff --git a/sim/ppc/events.c b/sim/ppc/events.c
index 898810c7b741..f281e973329b 100644
--- a/sim/ppc/events.c
+++ b/sim/ppc/events.c
@@ -55,7 +55,7 @@ typedef struct _event_entry event_entry;
struct _event_entry {
void *data;
event_handler *handler;
- signed64 time_of_event;
+ int64_t time_of_event;
event_entry *next;
};
@@ -64,8 +64,8 @@ struct _event_queue {
event_entry *queue;
event_entry *volatile held;
event_entry *volatile *volatile held_end;
- signed64 time_of_event;
- signed64 time_from_event;
+ int64_t time_of_event;
+ int64_t time_from_event;
};
@@ -142,7 +142,7 @@ event_queue_init(event_queue *queue)
}
INLINE_EVENTS\
-(signed64)
+(int64_t)
event_queue_time(event_queue *queue)
{
return queue->time_of_event - queue->time_from_event;
@@ -152,7 +152,7 @@ STATIC_INLINE_EVENTS\
(void)
update_time_from_event(event_queue *events)
{
- signed64 current_time = event_queue_time(events);
+ int64_t current_time = event_queue_time(events);
if (events->queue != NULL) {
events->time_from_event = (events->queue->time_of_event - current_time);
events->time_of_event = events->queue->time_of_event;
@@ -186,11 +186,11 @@ STATIC_INLINE_EVENTS\
(void)
insert_event_entry(event_queue *events,
event_entry *new_event,
- signed64 delta)
+ int64_t delta)
{
event_entry *curr;
event_entry **prev;
- signed64 time_of_event;
+ int64_t time_of_event;
if (delta < 0)
error("what is past is past!\n");
@@ -221,7 +221,7 @@ insert_event_entry(event_queue *events,
INLINE_EVENTS\
(event_entry_tag)
event_queue_schedule(event_queue *events,
- signed64 delta_time,
+ int64_t delta_time,
event_handler *handler,
void *data)
{
@@ -242,7 +242,7 @@ event_queue_schedule(event_queue *events,
INLINE_EVENTS\
(event_entry_tag)
event_queue_schedule_after_signal(event_queue *events,
- signed64 delta_time,
+ int64_t delta_time,
event_handler *handler,
void *data)
{
@@ -323,7 +323,7 @@ INLINE_EVENTS\
(int)
event_queue_tick(event_queue *events)
{
- signed64 time_from_event;
+ int64_t time_from_event;
/* we should only be here when the previous tick has been fully processed */
ASSERT(!events->processing);
@@ -372,7 +372,7 @@ INLINE_EVENTS\
(void)
event_queue_process(event_queue *events)
{
- signed64 event_time = event_queue_time(events);
+ int64_t event_time = event_queue_time(events);
ASSERT((events->time_from_event == -1 && events->queue != NULL)
|| events->processing); /* something to do */
diff --git a/sim/ppc/events.h b/sim/ppc/events.h
index 648a82aa8b64..2a78d6ff00ff 100644
--- a/sim/ppc/events.h
+++ b/sim/ppc/events.h
@@ -40,14 +40,14 @@ INLINE_EVENTS\
INLINE_EVENTS\
(event_entry_tag) event_queue_schedule
(event_queue *queue,
- signed64 delta_time,
+ int64_t delta_time,
event_handler *handler,
void *data);
INLINE_EVENTS\
(event_entry_tag) event_queue_schedule_after_signal
(event_queue *queue,
- signed64 delta_time,
+ int64_t delta_time,
event_handler *handler,
void *data);
@@ -72,7 +72,7 @@ INLINE_EVENTS\
/* local concept of time */
INLINE_EVENTS\
-(signed64) event_queue_time
+(int64_t) event_queue_time
(event_queue *queue);
#endif /* _EVENTS_H_ */
diff --git a/sim/ppc/hw_disk.c b/sim/ppc/hw_disk.c
index a2ea9340bc5a..3a825202784d 100644
--- a/sim/ppc/hw_disk.c
+++ b/sim/ppc/hw_disk.c
@@ -412,9 +412,9 @@ hw_disk_instance_seek(device_instance *instance,
static int
hw_disk_max_transfer(device_instance *instance,
int n_stack_args,
- unsigned32 stack_args[/*n_stack_args*/],
+ uint32_t stack_args[/*n_stack_args*/],
int n_stack_returns,
- unsigned32 stack_returns[/*n_stack_returns*/])
+ uint32_t stack_returns[/*n_stack_returns*/])
{
device *me = device_instance_device(instance);
if ((n_stack_args != 0)
@@ -439,9 +439,9 @@ hw_disk_max_transfer(device_instance *instance,
static int
hw_disk_block_size(device_instance *instance,
int n_stack_args,
- unsigned32 stack_args[/*n_stack_args*/],
+ uint32_t stack_args[/*n_stack_args*/],
int n_stack_returns,
- unsigned32 stack_returns[/*n_stack_returns*/])
+ uint32_t stack_returns[/*n_stack_returns*/])
{
device *me = device_instance_device(instance);
if ((n_stack_args != 0)
@@ -466,9 +466,9 @@ hw_disk_block_size(device_instance *instance,
static int
hw_disk_nr_blocks(device_instance *instance,
int n_stack_args,
- unsigned32 stack_args[/*n_stack_args*/],
+ uint32_t stack_args[/*n_stack_args*/],
int n_stack_returns,
- unsigned32 stack_returns[/*n_stack_returns*/])
+ uint32_t stack_returns[/*n_stack_returns*/])
{
device *me = device_instance_device(instance);
if ((n_stack_args != 0)
diff --git a/sim/ppc/hw_eeprom.c b/sim/ppc/hw_eeprom.c
index b0a3ac635b16..2bbcd77773d1 100644
--- a/sim/ppc/hw_eeprom.c
+++ b/sim/ppc/hw_eeprom.c
@@ -178,20 +178,20 @@ state2a(hw_eeprom_states state)
typedef struct _hw_eeprom_device {
/* general */
hw_eeprom_states state;
- unsigned8 *memory;
+ uint8_t *memory;
unsigned sizeof_memory;
unsigned erase_delay;
- signed64 program_start_time;
- signed64 program_finish_time;
- unsigned8 manufacture_code;
- unsigned8 device_code;
- unsigned8 toggle_bit;
+ int64_t program_start_time;
+ int64_t program_finish_time;
+ uint8_t manufacture_code;
+ uint8_t device_code;
+ uint8_t toggle_bit;
/* initialization */
const char *input_file_name;
const char *output_file_name;
/* for sector and sector programming */
hw_eeprom_states sector_state;
- unsigned8 *sectors;
+ uint8_t *sectors;
unsigned nr_sectors;
unsigned sizeof_sector;
unsigned sector_start_delay;
@@ -199,12 +199,12 @@ typedef struct _hw_eeprom_device {
/* byte and byte programming */
unsigned byte_write_delay;
unsigned_word byte_program_address;
- unsigned8 byte_program_byte;
+ uint8_t byte_program_byte;
} hw_eeprom_device;
typedef struct _hw_eeprom_reg_spec {
- unsigned32 base;
- unsigned32 size;
+ uint32_t base;
+ uint32_t size;
} hw_eeprom_reg_spec;
static void
@@ -275,7 +275,7 @@ static void
invalid_write(device *me,
hw_eeprom_states state,
unsigned_word address,
- unsigned8 data,
+ uint8_t data,
const char *reason)
{
DTRACE(eeprom, ("Invalid write of 0x%lx to 0x%lx while in state %s (%s)\n",
@@ -312,9 +312,9 @@ static void
start_programming_byte(device *me,
hw_eeprom_device *eeprom,
unsigned_word address,
- unsigned8 new_byte)
+ uint8_t new_byte)
{
- unsigned8 old_byte = eeprom->memory[address];
+ uint8_t old_byte = eeprom->memory[address];
DTRACE(eeprom, ("start-programing-byte - address 0x%lx, new 0x%lx, old 0x%lx\n",
(unsigned long)address,
(unsigned long)new_byte,
@@ -415,15 +415,15 @@ finish_erasing_sector(device *me,
/* eeprom reads */
-static unsigned8
+static uint8_t
toggle(hw_eeprom_device *eeprom,
- unsigned8 byte)
+ uint8_t byte)
{
eeprom->toggle_bit = eeprom->toggle_bit ^ 0x40; /* le-bit 6 */
return eeprom->toggle_bit ^ byte;
}
-static unsigned8
+static uint8_t
read_byte(device *me,
hw_eeprom_device *eeprom,
unsigned_word address)
@@ -519,8 +519,8 @@ hw_eeprom_io_read_buffer(device *me,
int i;
for (i = 0; i < nr_bytes; i++) {
unsigned_word address = (addr + i) % eeprom->sizeof_memory;
- unsigned8 byte = read_byte(me, eeprom, address);
- ((unsigned8*)dest)[i] = byte;
+ uint8_t byte = read_byte(me, eeprom, address);
+ ((uint8_t*)dest)[i] = byte;
}
return nr_bytes;
}
@@ -532,7 +532,7 @@ static void
write_byte(device *me,
hw_eeprom_device *eeprom,
unsigned_word address,
- unsigned8 data)
+ uint8_t data)
{
/* may need multiple transitions to process a write */
while (1) {
@@ -709,7 +709,7 @@ hw_eeprom_io_write_buffer(device *me,
int i;
for (i = 0; i < nr_bytes; i++) {
unsigned_word address = (addr + i) % eeprom->sizeof_memory;
- unsigned8 byte = ((unsigned8*)source)[i];
+ uint8_t byte = ((uint8_t*)source)[i];
write_byte(me, eeprom, address, byte);
}
return nr_bytes;
@@ -741,7 +741,7 @@ hw_eeprom_instance_read(device_instance *instance,
if (data->eeprom->state != read_reset)
DITRACE(eeprom, ("eeprom not idle during instance read\n"));
for (i = 0; i < len; i++) {
- ((unsigned8*)buf)[i] = data->eeprom->memory[data->pos];
+ ((uint8_t*)buf)[i] = data->eeprom->memory[data->pos];
data->pos = (data->pos + 1) % data->eeprom->sizeof_memory;
}
return len;
@@ -757,7 +757,7 @@ hw_eeprom_instance_write(device_instance *instance,
if (data->eeprom->state != read_reset)
DITRACE(eeprom, ("eeprom not idle during instance write\n"));
for (i = 0; i < len; i++) {
- data->eeprom->memory[data->pos] = ((unsigned8*)buf)[i];
+ data->eeprom->memory[data->pos] = ((uint8_t*)buf)[i];
data->pos = (data->pos + 1) % data->eeprom->sizeof_memory;
}
dump_eeprom(data->me, data->eeprom);
diff --git a/sim/ppc/hw_htab.c b/sim/ppc/hw_htab.c
index e7b6371e1dd4..ce098341c82d 100644
--- a/sim/ppc/hw_htab.c
+++ b/sim/ppc/hw_htab.c
@@ -204,8 +204,8 @@
static void
htab_decode_hash_table(device *me,
- unsigned32 *htaborg,
- unsigned32 *htabmask)
+ uint32_t *htaborg,
+ uint32_t *htabmask)
{
unsigned_word htab_ra;
unsigned htab_nr_bytes;
@@ -242,27 +242,27 @@ htab_decode_hash_table(device *me,
static void
htab_map_page(device *me,
unsigned_word ra,
- unsigned64 va,
+ uint64_t va,
unsigned wimg,
unsigned pp,
- unsigned32 htaborg,
- unsigned32 htabmask)
+ uint32_t htaborg,
+ uint32_t htabmask)
{
/* keep everything left shifted so that the numbering is easier */
- unsigned64 vpn = va << 12;
- unsigned32 vsid = INSERTED32(EXTRACTED64(vpn, 0, 23), 0, 23);
- unsigned32 vpage = INSERTED32(EXTRACTED64(vpn, 24, 39), 0, 15);
- unsigned32 hash = INSERTED32(EXTRACTED32(vsid, 5, 23)
+ uint64_t vpn = va << 12;
+ uint32_t vsid = INSERTED32(EXTRACTED64(vpn, 0, 23), 0, 23);
+ uint32_t vpage = INSERTED32(EXTRACTED64(vpn, 24, 39), 0, 15);
+ uint32_t hash = INSERTED32(EXTRACTED32(vsid, 5, 23)
^ EXTRACTED32(vpage, 0, 15),
7, 31-6);
int h;
for (h = 0; h < 2; h++) {
- unsigned32 pteg = (htaborg | (hash & htabmask));
+ uint32_t pteg = (htaborg | (hash & htabmask));
int pti;
for (pti = 0; pti < 8; pti++) {
- unsigned32 pte = pteg + 8 * pti;
- unsigned32 current_target_pte0;
- unsigned32 current_pte0;
+ uint32_t pte = pteg + 8 * pti;
+ uint32_t current_target_pte0;
+ uint32_t current_pte0;
if (device_dma_read_buffer(device_parent(me),
¤t_target_pte0,
0, /*space*/
@@ -273,9 +273,9 @@ htab_map_page(device *me,
if (MASKED32(current_pte0, 0, 0)) {
/* full pte, check it isn't already mapping the same virtual
address */
- unsigned32 curr_vsid = INSERTED32(EXTRACTED32(current_pte0, 1, 24), 0, 23);
- unsigned32 curr_api = INSERTED32(EXTRACTED32(current_pte0, 26, 31), 0, 5);
- unsigned32 curr_h = EXTRACTED32(current_pte0, 25, 25);
+ uint32_t curr_vsid = INSERTED32(EXTRACTED32(current_pte0, 1, 24), 0, 23);
+ uint32_t curr_api = INSERTED32(EXTRACTED32(current_pte0, 26, 31), 0, 5);
+ uint32_t curr_h = EXTRACTED32(current_pte0, 25, 25);
if (curr_h == h
&& curr_vsid == vsid
&& curr_api == MASKED32(vpage, 0, 5))
@@ -292,15 +292,15 @@ htab_map_page(device *me,
}
else {
/* empty pte fill it */
- unsigned32 pte0 = (MASK32(0, 0)
+ uint32_t pte0 = (MASK32(0, 0)
| INSERTED32(EXTRACTED32(vsid, 0, 23), 1, 24)
| INSERTED32(h, 25, 25)
| INSERTED32(EXTRACTED32(vpage, 0, 5), 26, 31));
- unsigned32 target_pte0 = H2T_4(pte0);
- unsigned32 pte1 = (INSERTED32(EXTRACTED32(ra, 0, 19), 0, 19)
+ uint32_t target_pte0 = H2T_4(pte0);
+ uint32_t pte1 = (INSERTED32(EXTRACTED32(ra, 0, 19), 0, 19)
| INSERTED32(wimg, 25, 28)
| INSERTED32(pp, 30, 31));
- unsigned32 target_pte1 = H2T_4(pte1);
+ uint32_t target_pte1 = H2T_4(pte1);
if (device_dma_write_buffer(device_parent(me),
&target_pte0,
0, /*space*/
@@ -339,8 +339,8 @@ claim_memory(device *me,
unsigned_word ra,
unsigned_word size)
{
- unsigned32 args[3];
- unsigned32 results[1];
+ uint32_t args[3];
+ uint32_t results[1];
int status;
args[0] = 0; /* alignment */
args[1] = size;
@@ -355,15 +355,15 @@ static void
htab_map_region(device *me,
device_instance *memory,
unsigned_word pte_ra,
- unsigned64 pte_va,
+ uint64_t pte_va,
unsigned nr_bytes,
unsigned wimg,
unsigned pp,
- unsigned32 htaborg,
- unsigned32 htabmask)
+ uint32_t htaborg,
+ uint32_t htabmask)
{
unsigned_word ra;
- unsigned64 va;
+ uint64_t va;
/* claim the memory */
if (memory != NULL)
claim_memory(me, memory, pte_ra, nr_bytes);
@@ -499,8 +499,8 @@ htab_map_binary(device *me,
unsigned wimg,
unsigned pp,
const char *file_name,
- unsigned32 htaborg,
- unsigned32 htabmask)
+ uint32_t htaborg,
+ uint32_t htabmask)
{
htab_binary_sizes sizes;
bfd *image;
@@ -615,8 +615,8 @@ htab_init_data_callback(device *me)
/* for the pte, do all the real work */
if (strcmp(device_name(me), "pte") == 0) {
- unsigned32 htaborg;
- unsigned32 htabmask;
+ uint32_t htaborg;
+ uint32_t htabmask;
htab_decode_hash_table(me, &htaborg, &htabmask);
@@ -626,7 +626,7 @@ htab_init_data_callback(device *me)
unsigned pte_pp = device_find_integer_property(me, "pp");
const char *file_name = device_find_string_property(me, "file-name");
if (device_find_property(me, "real-address") != NULL) {
- unsigned32 pte_ra = device_find_integer_property(me, "real-address");
+ uint32_t pte_ra = device_find_integer_property(me, "real-address");
DTRACE(htab, ("pte - ra=0x%lx, wimg=%ld, pp=%ld, file-name=%s\n",
(unsigned long)pte_ra,
(unsigned long)pte_wimg,
@@ -646,8 +646,8 @@ htab_init_data_callback(device *me)
}
else {
/* handle a normal mapping definition */
- unsigned64 pte_va = 0;
- unsigned32 pte_ra = device_find_integer_property(me, "real-address");
+ uint64_t pte_va = 0;
+ uint32_t pte_ra = device_find_integer_property(me, "real-address");
unsigned pte_nr_bytes = device_find_integer_property(me, "nr-bytes");
unsigned pte_wimg = device_find_integer_property(me, "wimg");
unsigned pte_pp = device_find_integer_property(me, "pp");
diff --git a/sim/ppc/hw_ide.c b/sim/ppc/hw_ide.c
index 6c5e05163ba1..af61eeccab6f 100644
--- a/sim/ppc/hw_ide.c
+++ b/sim/ppc/hw_ide.c
@@ -224,8 +224,8 @@ typedef struct _ide_drive {
typedef struct _ide_controller {
int nr;
ide_states state;
- unsigned8 reg[nr_ide_registers];
- unsigned8 fifo[nr_fifo_entries];
+ uint8_t reg[nr_ide_registers];
+ uint8_t fifo[nr_fifo_entries];
int fifo_pos;
int fifo_size;
ide_drive *current_drive;
@@ -235,7 +235,7 @@ typedef struct _ide_controller {
device *me;
event_entry_tag event_tag;
int is_interrupting;
- signed64 ready_delay;
+ int64_t ready_delay;
} ide_controller;
@@ -488,7 +488,7 @@ do_command(device *me,
}
}
-static unsigned8
+static uint8_t
get_status(device *me,
ide_controller *controller)
{
@@ -744,11 +744,11 @@ hw_ide_io_read_buffer(device *me,
do_fifo_read(me, controller, dest, nr_bytes);
break;
case ide_status_reg:
- *(unsigned8*)dest = get_status(me, controller);
+ *(uint8_t*)dest = get_status(me, controller);
clear_interrupt(me, controller);
break;
case ide_alternate_status_reg:
- *(unsigned8*)dest = get_status(me, controller);
+ *(uint8_t*)dest = get_status(me, controller);
break;
case ide_error_reg:
case ide_sector_count_reg:
@@ -763,7 +763,7 @@ hw_ide_io_read_buffer(device *me,
case ide_dma_prd_table_address_reg1:
case ide_dma_prd_table_address_reg2:
case ide_dma_prd_table_address_reg3:
- *(unsigned8*)dest = controller->reg[reg];
+ *(uint8_t*)dest = controller->reg[reg];
break;
default:
device_error(me, "bus-error at address 0x%lx", (unsigned long)addr);
@@ -797,10 +797,10 @@ hw_ide_io_write_buffer(device *me,
do_fifo_write(me, controller, source, nr_bytes);
break;
case ide_command_reg:
- do_command(me, controller, *(unsigned8*)source);
+ do_command(me, controller, *(uint8_t*)source);
break;
case ide_control_reg:
- controller->reg[reg] = *(unsigned8*)source;
+ controller->reg[reg] = *(uint8_t*)source;
/* possibly cancel interrupts */
if ((controller->reg[reg] & 0x02) == 0x02)
clear_interrupt(me, controller);
@@ -817,7 +817,7 @@ hw_ide_io_write_buffer(device *me,
case ide_dma_prd_table_address_reg1:
case ide_dma_prd_table_address_reg2:
case ide_dma_prd_table_address_reg3:
- controller->reg[reg] = *(unsigned8*)source;
+ controller->reg[reg] = *(uint8_t*)source;
break;
default:
device_error(me, "bus-error at 0x%lx", (unsigned long)addr);
diff --git a/sim/ppc/hw_nvram.c b/sim/ppc/hw_nvram.c
index 0580dcc2a43d..e26b5476a36b 100644
--- a/sim/ppc/hw_nvram.c
+++ b/sim/ppc/hw_nvram.c
@@ -62,7 +62,7 @@
*/
typedef struct _hw_nvram_device {
- unsigned8 *memory;
+ uint8_t *memory;
unsigned sizeof_memory;
time_t host_time;
unsigned timezone;
@@ -87,8 +87,8 @@ hw_nvram_create(const char *name,
}
typedef struct _hw_nvram_reg_spec {
- unsigned32 base;
- unsigned32 size;
+ uint32_t base;
+ uint32_t size;
} hw_nvram_reg_spec;
static void
@@ -200,9 +200,9 @@ hw_nvram_io_read_buffer(device *me,
hw_nvram_device *nvram = (hw_nvram_device*)device_data(me);
for (i = 0; i < nr_bytes; i++) {
unsigned address = (addr + i) % nvram->sizeof_memory;
- unsigned8 data = nvram->memory[address];
+ uint8_t data = nvram->memory[address];
hw_nvram_update_clock(nvram, processor);
- ((unsigned8*)dest)[i] = data;
+ ((uint8_t*)dest)[i] = data;
}
return nr_bytes;
}
@@ -220,7 +220,7 @@ hw_nvram_io_write_buffer(device *me,
hw_nvram_device *nvram = (hw_nvram_device*)device_data(me);
for (i = 0; i < nr_bytes; i++) {
unsigned address = (addr + i) % nvram->sizeof_memory;
- unsigned8 data = ((unsigned8*)source)[i];
+ uint8_t data = ((uint8_t*)source)[i];
if (address == nvram->addr_control
&& (data & 0x80) == 0
&& (nvram->memory[address] & 0x80) == 0x80)
diff --git a/sim/ppc/hw_opic.c b/sim/ppc/hw_opic.c
index 9404204aa2f3..42474115a717 100644
--- a/sim/ppc/hw_opic.c
+++ b/sim/ppc/hw_opic.c
@@ -305,7 +305,7 @@ typedef struct _opic_timer {
hw_opic_device *opic; /* ditto */
unsigned base_count;
int inhibited;
- signed64 count; /* *ONLY* if inhibited */
+ int64_t count; /* *ONLY* if inhibited */
event_entry_tag timeout_event;
opic_interrupt_source *interrupt_source;
} opic_timer;
@@ -347,7 +347,7 @@ struct _hw_opic_device {
unsigned timer_frequency;
/* init register */
- unsigned32 init;
+ uint32_t init;
/* address maps */
opic_idu idu;
diff --git a/sim/ppc/hw_register.c b/sim/ppc/hw_register.c
index de65c9f01838..6d78a7c2ff2a 100644
--- a/sim/ppc/hw_register.c
+++ b/sim/ppc/hw_register.c
@@ -80,7 +80,7 @@ do_register_init(device *me,
psim *system = device_system(me);
if (prop != NULL) {
const char *name = prop->name;
- unsigned32 value = device_find_integer_property(me, name);
+ uint32_t value = device_find_integer_property(me, name);
int processor;
do_register_init(me, device_next_property(prop));
diff --git a/sim/ppc/hw_sem.c b/sim/ppc/hw_sem.c
index 5f3595204d2c..937e2ad6f812 100644
--- a/sim/ppc/hw_sem.c
+++ b/sim/ppc/hw_sem.c
@@ -187,7 +187,7 @@ hw_sem_io_read_buffer(device *me,
hw_sem_device *sem = (hw_sem_device*)device_data(me);
struct sembuf sb;
int status;
- unsigned32 u32;
+ uint32_t u32;
union semun help;
/* do we need to worry about out of range addresses? */
diff --git a/sim/ppc/hw_trace.c b/sim/ppc/hw_trace.c
index 9490bfb97f4a..e150e58333fc 100644
--- a/sim/ppc/hw_trace.c
+++ b/sim/ppc/hw_trace.c
@@ -69,7 +69,7 @@ hw_trace_ioctl(device *me,
const device_property *prop = device_find_property(me, NULL);
while (prop != NULL) {
const char *name = prop->name;
- unsigned32 value = device_find_integer_property(me, name);
+ uint32_t value = device_find_integer_property(me, name);
trace_option(name, value);
prop = device_next_property(prop);
}
diff --git a/sim/ppc/idecode_expression.h b/sim/ppc/idecode_expression.h
index 01b7ebb74a3b..9c4cb7a55a98 100644
--- a/sim/ppc/idecode_expression.h
+++ b/sim/ppc/idecode_expression.h
@@ -30,7 +30,7 @@
/* 32bit target expressions:
Each calculation is performed three times using each of the
- signed64, unsigned64 and long integer types. The macro ALU_END
+ int64_t, uint64_t and long integer types. The macro ALU_END
(in _ALU_RESULT_VAL) then selects which of the three alternative
results will be used in the final assignment of the target
register. As this selection is determined at compile time by
@@ -57,8 +57,8 @@
/* Macro's to type cast 32bit constants to 64bits */
-#define SIGNED64(val) ((signed64)(signed32)(val))
-#define UNSIGNED64(val) ((unsigned64)(unsigned32)(val))
+#define SIGNED64(val) ((int64_t)(int32_t)(val))
+#define UNSIGNED64(val) ((uint64_t)(uint32_t)(val))
/* Start a section of ALU code */
@@ -66,8 +66,8 @@
#define ALU_BEGIN(val) \
{ \
signed_word alu_val; \
- unsigned64 alu_carry_val; \
- signed64 alu_overflow_val; \
+ uint64_t alu_carry_val; \
+ int64_t alu_overflow_val; \
ALU_SET(val)
@@ -78,7 +78,7 @@
signed_word const alu_result = _ALU_RESULT_VAL(CA,OE,Rc); \
/* determine the overflow bit if needed */ \
if (OE) { \
- if ((((unsigned64)(alu_overflow_val & BIT64(0))) \
+ if ((((uint64_t)(alu_overflow_val & BIT64(0))) \
>> 32) \
== (alu_overflow_val & BIT64(32))) \
XER &= (~xer_overflow); \
@@ -118,23 +118,23 @@
#define ALU_SET(val) \
do { \
alu_val = val; \
- alu_carry_val = ((unsigned64)alu_val) >> 32; \
- alu_overflow_val = ((signed64)alu_val) >> 32; \
+ alu_carry_val = ((uint64_t)alu_val) >> 32; \
+ alu_overflow_val = ((int64_t)alu_val) >> 32; \
} while (0)
#endif
#if (WITH_TARGET_WORD_BITSIZE == 32)
#define ALU_SET(val) \
do { \
alu_val = val; \
- alu_carry_val = (unsigned32)(alu_val); \
- alu_overflow_val = (signed32)(alu_val); \
+ alu_carry_val = (uint32_t)(alu_val); \
+ alu_overflow_val = (int32_t)(alu_val); \
} while (0)
#endif
#if (WITH_TARGET_WORD_BITSIZE == 64)
#define ALU_ADD(val) \
do { \
- unsigned64 alu_lo = (UNSIGNED64(alu_val) \
+ uint64_t alu_lo = (UNSIGNED64(alu_val) \
+ UNSIGNED64(val)); \
signed alu_carry = ((alu_lo & BIT(31)) != 0); \
alu_carry_val = (alu_carry_val \
@@ -150,8 +150,8 @@ do { \
#define ALU_ADD(val) \
do { \
alu_val += val; \
- alu_carry_val += (unsigned32)(val); \
- alu_overflow_val += (signed32)(val); \
+ alu_carry_val += (uint32_t)(val); \
+ alu_overflow_val += (int32_t)(val); \
} while (0)
#endif
@@ -179,8 +179,8 @@ do { \
#define ALU_SUB(val) \
do { \
alu_val -= val; \
- alu_carry_val -= (unsigned32)(val); \
- alu_overflow_val -= (signed32)(val); \
+ alu_carry_val -= (uint32_t)(val); \
+ alu_overflow_val -= (int32_t)(val); \
} while (0)
#endif
#endif
@@ -191,8 +191,8 @@ do { \
#define ALU_OR(val) \
do { \
alu_val |= val; \
- alu_carry_val = (unsigned32)(alu_val); \
- alu_overflow_val = (signed32)(alu_val); \
+ alu_carry_val = (uint32_t)(alu_val); \
+ alu_overflow_val = (int32_t)(alu_val); \
} while (0)
#endif
@@ -203,8 +203,8 @@ do { \
#define ALU_XOR(val) \
do { \
alu_val ^= val; \
- alu_carry_val = (unsigned32)(alu_val); \
- alu_overflow_val = (signed32)(alu_val); \
+ alu_carry_val = (uint32_t)(alu_val); \
+ alu_overflow_val = (int32_t)(alu_val); \
} while (0)
#endif
@@ -229,8 +229,8 @@ do { \
#define ALU_AND(val) \
do { \
alu_val &= val; \
- alu_carry_val = (unsigned32)(alu_val); \
- alu_overflow_val = (signed32)(alu_val); \
+ alu_carry_val = (uint32_t)(alu_val); \
+ alu_overflow_val = (int32_t)(alu_val); \
} while (0)
#endif
@@ -238,7 +238,7 @@ do { \
#if (WITH_TARGET_WORD_BITSIZE == 64)
#define ALU_NOT \
do { \
- signed64 new_alu_val = ~alu_val; \
+ int64_t new_alu_val = ~alu_val; \
ALU_SET(new_alu_val); \
} while (0)
#endif
diff --git a/sim/ppc/pk_disklabel.c b/sim/ppc/pk_disklabel.c
index d424c0480aeb..2dbce134f8df 100644
--- a/sim/ppc/pk_disklabel.c
+++ b/sim/ppc/pk_disklabel.c
@@ -52,32 +52,32 @@
/* PPCbug location structure */
typedef struct ppcboot_location {
- unsigned8 ind;
- unsigned8 head;
- unsigned8 sector;
- unsigned8 cylinder;
+ uint8_t ind;
+ uint8_t head;
+ uint8_t sector;
+ uint8_t cylinder;
} ppcboot_location_t;
/* PPCbug partition table layout */
typedef struct ppcboot_partition {
ppcboot_location_t partition_begin; /* partition begin */
ppcboot_location_t partition_end; /* partition end */
- unsigned8 sector_begin[4]; /* 32-bit start RBA (zero-based), little endian */
- unsigned8 sector_length[4]; /* 32-bit RBA count (one-based), little endian */
+ uint8_t sector_begin[4]; /* 32-bit start RBA (zero-based), little endian */
+ uint8_t sector_length[4]; /* 32-bit RBA count (one-based), little endian */
} ppcboot_partition_t;
#if 0
/* PPCbug boot layout. */
typedef struct ppcboot_hdr {
- unsigned8 pc_compatibility[446]; /* x86 instruction field */
+ uint8_t pc_compatibility[446]; /* x86 instruction field */
ppcboot_partition_t partition[4]; /* partition information */
- unsigned8 signature[2]; /* 0x55 and 0xaa */
- unsigned8 entry_offset[4]; /* entry point offset, little endian */
- unsigned8 length[4]; /* load image length, little endian */
- unsigned8 flags; /* flag field */
- unsigned8 os_id; /* OS_ID */
+ uint8_t signature[2]; /* 0x55 and 0xaa */
+ uint8_t entry_offset[4]; /* entry point offset, little endian */
+ uint8_t length[4]; /* load image length, little endian */
+ uint8_t flags; /* flag field */
+ uint8_t os_id; /* OS_ID */
char partition_name[32]; /* partition name */
- unsigned8 reserved1[470]; /* reserved */
+ uint8_t reserved1[470]; /* reserved */
} ppcboot_hdr_t;
#endif
@@ -92,7 +92,7 @@ typedef struct _disklabel {
static unsigned_word
-sector2uw(unsigned8 s[4])
+sector2uw(uint8_t s[4])
{
return ((s[3] << 24)
+ (s[2] << 16)
@@ -169,7 +169,7 @@ static const device_instance_callbacks package_disklabel_callbacks = {
/* Reconize different types of boot block */
static int
-block0_is_bpb(const unsigned8 block[])
+block0_is_bpb(const uint8_t block[])
{
const char ebdic_ibma[] = { 0xc9, 0xc2, 0xd4, 0xc1 };
/* ref PowerPC Microprocessor CHRP bindings 1.2b - page 47 */
@@ -196,7 +196,7 @@ static int
is_iso9660(device_instance *raw_disk)
{
/* ref PowerPC Microprocessor CHRP bindings 1.2b - page 47 */
- unsigned8 block[512];
+ uint8_t block[512];
if (device_instance_seek(raw_disk, 0, 512 * 64) < 0)
return 0;
if (device_instance_read(raw_disk, block, sizeof(block)) != sizeof(block))
@@ -220,7 +220,7 @@ is_iso9660(device_instance *raw_disk)
Return -1: no active partition */
static int
-block0_is_fdisk(const unsigned8 block[])
+block0_is_fdisk(const uint8_t block[])
{
const int partition_type_fields[] = { 0, 0x1c2, 0x1d2, 0x1e2, 0x1f2 };
const int partition_active_fields[] = { 0, 0x1be, 0x1ce, 0x1de, 0xee };
@@ -279,7 +279,7 @@ block0_is_fdisk(const unsigned8 block[])
/* Verify that block0 corresponds to a MAC disk */
static int
-block0_is_mac_disk(const unsigned8 block[])
+block0_is_mac_disk(const uint8_t block[])
{
/* ref PowerPC Microprocessor CHRP bindings 1.2b - page 47 */
/* signature - BEx4552 at offset 0 */
@@ -318,7 +318,7 @@ pk_disklabel_create_instance(device_instance *raw_disk,
return raw_disk;
}
else {
- unsigned8 boot_block[512];
+ uint8_t boot_block[512];
/* get the boot block for examination */
if (device_instance_seek(raw_disk, 0, 0) < 0)
device_error(device_instance_device(raw_disk),
diff --git a/sim/ppc/ppc-instructions b/sim/ppc/ppc-instructions
index 2278b6263765..60840fe843c8 100644
--- a/sim/ppc/ppc-instructions
+++ b/sim/ppc/ppc-instructions
@@ -35,49 +35,49 @@
:cache::::RA:RA:
:cache:::signed_word *:rA:RA:(cpu_registers(processor)->gpr + RA)
-:cache:::unsigned32:RA_BITMASK:RA:(1 << RA)
+:cache:::uint32_t:RA_BITMASK:RA:(1 << RA)
:compute:::int:RA_is_0:RA:(RA == 0)
:cache::::RT:RT:
:cache:::signed_word *:rT:RT:(cpu_registers(processor)->gpr + RT)
-:cache:::unsigned32:RT_BITMASK:RT:(1 << RT)
+:cache:::uint32_t:RT_BITMASK:RT:(1 << RT)
:cache::::RS:RS:
:cache:::signed_word *:rS:RS:(cpu_registers(processor)->gpr + RS)
-:cache:::unsigned32:RS_BITMASK:RS:(1 << RS)
+:cache:::uint32_t:RS_BITMASK:RS:(1 << RS)
:cache::::RB:RB:
:cache:::signed_word *:rB:RB:(cpu_registers(processor)->gpr + RB)
-:cache:::unsigned32:RB_BITMASK:RB:(1 << RB)
+:cache:::uint32_t:RB_BITMASK:RB:(1 << RB)
:scratch::::FRA:FRA:
-:cache:::unsigned64 *:frA:FRA:(cpu_registers(processor)->fpr + FRA)
-:cache:::unsigned32:FRA_BITMASK:FRA:(1 << FRA)
+:cache:::uint64_t *:frA:FRA:(cpu_registers(processor)->fpr + FRA)
+:cache:::uint32_t:FRA_BITMASK:FRA:(1 << FRA)
:scratch::::FRB:FRB:
-:cache:::unsigned64 *:frB:FRB:(cpu_registers(processor)->fpr + FRB)
-:cache:::unsigned32:FRB_BITMASK:FRB:(1 << FRB)
+:cache:::uint64_t *:frB:FRB:(cpu_registers(processor)->fpr + FRB)
+:cache:::uint32_t:FRB_BITMASK:FRB:(1 << FRB)
:scratch::::FRC:FRC:
-:cache:::unsigned64 *:frC:FRC:(cpu_registers(processor)->fpr + FRC)
-:cache:::unsigned32:FRC_BITMASK:FRC:(1 << FRC)
+:cache:::uint64_t *:frC:FRC:(cpu_registers(processor)->fpr + FRC)
+:cache:::uint32_t:FRC_BITMASK:FRC:(1 << FRC)
:scratch::::FRS:FRS:
-:cache:::unsigned64 *:frS:FRS:(cpu_registers(processor)->fpr + FRS)
-:cache:::unsigned32:FRS_BITMASK:FRS:(1 << FRS)
+:cache:::uint64_t *:frS:FRS:(cpu_registers(processor)->fpr + FRS)
+:cache:::uint32_t:FRS_BITMASK:FRS:(1 << FRS)
:scratch::::FRT:FRT:
-:cache:::unsigned64 *:frT:FRT:(cpu_registers(processor)->fpr + FRT)
-:cache:::unsigned32:FRT_BITMASK:FRT:(1 << FRT)
-:cache:::unsigned_word:EXTS_SI:SI:((signed_word)(signed16)instruction)
+:cache:::uint64_t *:frT:FRT:(cpu_registers(processor)->fpr + FRT)
+:cache:::uint32_t:FRT_BITMASK:FRT:(1 << FRT)
+:cache:::unsigned_word:EXTS_SI:SI:((signed_word)(int16_t)instruction)
:scratch::::BI:BI:
:cache::::BIT32_BI:BI:BIT32(BI)
:cache::::BF:BF:
-:cache:::unsigned32:BF_BITMASK:BF:(1 << BF)
+:cache:::uint32_t:BF_BITMASK:BF:(1 << BF)
:scratch::::BA:BA:
:cache::::BIT32_BA:BA:BIT32(BA)
-:cache:::unsigned32:BA_BITMASK:BA:(1 << BA)
+:cache:::uint32_t:BA_BITMASK:BA:(1 << BA)
:scratch::::BB:BB:
:cache::::BIT32_BB:BB:BIT32(BB)
-:cache:::unsigned32:BB_BITMASK:BB:(1 << BB)
+:cache:::uint32_t:BB_BITMASK:BB:(1 << BB)
:cache::::BT:BT:
-:cache:::unsigned32:BT_BITMASK:BT:(1 << BT)
-:cache:::unsigned_word:EXTS_BD_0b00:BD:(((signed_word)(signed16)instruction) & ~3)
-:cache:::unsigned_word:EXTS_LI_0b00:LI:((((signed_word)(signed32)(instruction << 6)) >> 6) & ~0x3)
-:cache:::unsigned_word:EXTS_D:D:((signed_word)(signed16)(instruction))
-:cache:::unsigned_word:EXTS_DS_0b00:DS:(((signed_word)(signed16)instruction) & ~0x3)
+:cache:::uint32_t:BT_BITMASK:BT:(1 << BT)
+:cache:::unsigned_word:EXTS_BD_0b00:BD:(((signed_word)(int16_t)instruction) & ~3)
+:cache:::unsigned_word:EXTS_LI_0b00:LI:((((signed_word)(int32_t)(instruction << 6)) >> 6) & ~0x3)
+:cache:::unsigned_word:EXTS_D:D:((signed_word)(int16_t)(instruction))
+:cache:::unsigned_word:EXTS_DS_0b00:DS:(((signed_word)(int16_t)instruction) & ~0x3)
#:compute:::int:SPR_is_256:SPR:(SPR == 256)
\f
# PowerPC models
@@ -174,9 +174,9 @@
struct _model_time {
ppc_function_unit first_unit; /* first functional unit this insn could use */
ppc_function_unit second_unit; /* second functional unit this insn could use */
- signed16 issue; /* # cycles before function unit can process other insns */
- signed16 done; /* # cycles before insn is done */
- unsigned32 flags; /* any flags that are needed */
+ int16_t issue; /* # cycles before function unit can process other insns */
+ int16_t done; /* # cycles before insn is done */
+ uint32_t flags; /* any flags that are needed */
};
/* Register mappings in status masks */
@@ -193,15 +193,15 @@
struct _model_busy {
model_busy *next; /* next function unit */
ppc_function_unit unit; /* function unit name */
- unsigned32 int_busy; /* int registers that are busy */
- unsigned32 fp_busy; /* floating point registers that are busy */
- unsigned32 cr_fpscr_busy; /* CR/FPSCR registers that are busy */
- signed16 spr_busy; /* SPR register that is busy or PPC_NO_SPR */
- unsigned32 vr_busy; /* AltiVec registers that are busy */
- signed16 vscr_busy; /* AltiVec status register busy */
- signed16 issue; /* # of cycles until unit can accept another insn */
- signed16 done; /* # of cycles until insn is done */
- signed16 nr_writebacks; /* # of registers this unit writes back */
+ uint32_t int_busy; /* int registers that are busy */
+ uint32_t fp_busy; /* floating point registers that are busy */
+ uint32_t cr_fpscr_busy; /* CR/FPSCR registers that are busy */
+ int16_t spr_busy; /* SPR register that is busy or PPC_NO_SPR */
+ uint32_t vr_busy; /* AltiVec registers that are busy */
+ int16_t vscr_busy; /* AltiVec status register busy */
+ int16_t issue; /* # of cycles until unit can accept another insn */
+ int16_t done; /* # of cycles until insn is done */
+ int16_t nr_writebacks; /* # of registers this unit writes back */
};
/* Structure to hold the current state information for the simulated CPU model */
@@ -225,13 +225,13 @@
count_type nr_stalls_writeback; /* # of stalls waiting for a writeback slot */
count_type nr_units[nr_ppc_function_units]; /* function unit counts */
int max_nr_writebacks; /* max # of writeback slots available */
- unsigned32 int_busy; /* int registers that are busy */
- unsigned32 fp_busy; /* floating point registers that are busy */
- unsigned32 cr_fpscr_busy; /* CR/FPSCR registers that are busy */
- unsigned8 spr_busy[nr_of_sprs]; /* SPR registers that are busy */
- unsigned32 vr_busy; /* AltiVec registers that are busy */
- unsigned8 vscr_busy; /* AltiVec SC register busy */
- unsigned8 busy[nr_ppc_function_units]; /* whether a function is busy or not */
+ uint32_t int_busy; /* int registers that are busy */
+ uint32_t fp_busy; /* floating point registers that are busy */
+ uint32_t cr_fpscr_busy; /* CR/FPSCR registers that are busy */
+ uint8_t spr_busy[nr_of_sprs]; /* SPR registers that are busy */
+ uint32_t vr_busy; /* AltiVec registers that are busy */
+ uint8_t vscr_busy; /* AltiVec SC register busy */
+ uint8_t busy[nr_ppc_function_units]; /* whether a function is busy or not */
};
static const char *const ppc_function_unit_name[ (int)nr_ppc_function_units ] = {
@@ -334,7 +334,7 @@ void::model-static::model_trace_release:model_data *model_ptr, model_busy *busy
TRACE(trace_model, ("VSCR Register %s is now available.\n", spr_name(busy->spr_busy)));
# Trace making registers busy
-void::model-static::model_trace_make_busy:model_data *model_ptr, unsigned32 int_mask, unsigned32 fp_mask, unsigned32 cr_mask
+void::model-static::model_trace_make_busy:model_data *model_ptr, uint32_t int_mask, uint32_t fp_mask, uint32_t cr_mask
int i;
if (int_mask) {
for(i = 0; i < 32; i++) {
@@ -359,7 +359,7 @@ void::model-static::model_trace_make_busy:model_data *model_ptr, unsigned32 int_
}
# Trace waiting for registers to become available
-void::model-static::model_trace_busy_p:model_data *model_ptr, unsigned32 int_busy, unsigned32 fp_busy, unsigned32 cr_or_fpscr_busy, int spr_busy
+void::model-static::model_trace_busy_p:model_data *model_ptr, uint32_t int_busy, uint32_t fp_busy, uint32_t cr_or_fpscr_busy, int spr_busy
int i;
if (int_busy) {
int_busy &= model_ptr->int_busy;
@@ -520,7 +520,7 @@ void::model-function::model_serialize:itable_index index, model_data *model_ptr
# Wait for a CR to become unbusy
void::model-function::model_wait_for_cr:model_data *model_ptr, unsigned CRBIT
unsigned u;
- unsigned32 cr_mask;
+ uint32_t cr_mask;
int cr_var = 0;
for (u = 0xc0000000; (u != 0) && (CRBIT & u) == 0; u >>= 4 )
cr_var++;
@@ -533,8 +533,8 @@ void::model-function::model_wait_for_cr:model_data *model_ptr, unsigned CRBIT
}
# Schedule an instruction that takes integer input registers and produces output registers
-void::model-function::ppc_insn_int:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask
- const unsigned32 int_mask = out_mask | in_mask;
+void::model-function::ppc_insn_int:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask
+ const uint32_t int_mask = out_mask | in_mask;
model_busy *busy_ptr;
if ((model_ptr->int_busy & int_mask) != 0) {
@@ -559,8 +559,8 @@ void::model-function::ppc_insn_int:itable_index index, model_data *model_ptr, co
model_trace_make_busy(model_ptr, out_mask, 0, 0);
# Schedule an instruction that takes integer input registers and produces output registers & sets a CR register
-void::model-function::ppc_insn_int_cr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned32 cr_mask
- const unsigned32 int_mask = out_mask | in_mask;
+void::model-function::ppc_insn_int_cr:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask, const uint32_t cr_mask
+ const uint32_t int_mask = out_mask | in_mask;
model_busy *busy_ptr;
if ((model_ptr->int_busy & int_mask) || (model_ptr->cr_fpscr_busy & cr_mask)) {
@@ -591,8 +591,8 @@ void::model-function::ppc_insn_int_cr:itable_index index, model_data *model_ptr,
# Schedule an instruction that takes CR input registers and produces output CR registers
-void::model-function::ppc_insn_cr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask
- const unsigned32 cr_mask = out_mask | in_mask;
+void::model-function::ppc_insn_cr:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask
+ const uint32_t cr_mask = out_mask | in_mask;
model_busy *busy_ptr;
if ((model_ptr->cr_fpscr_busy & cr_mask) != 0) {
@@ -618,8 +618,8 @@ void::model-function::ppc_insn_cr:itable_index index, model_data *model_ptr, con
# Schedule an instruction that takes floating point input registers and produces an output fp register
-void::model-function::ppc_insn_float:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask
- const unsigned32 fp_mask = out_mask | in_mask;
+void::model-function::ppc_insn_float:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask
+ const uint32_t fp_mask = out_mask | in_mask;
model_busy *busy_ptr;
if ((model_ptr->fp_busy & fp_mask) != 0) {
@@ -643,8 +643,8 @@ void::model-function::ppc_insn_float:itable_index index, model_data *model_ptr,
# Schedule an instruction that takes floating point input registers and produces an output fp register & sets a CR reg
-void::model-function::ppc_insn_float_cr:itable_index index, model_data *model_ptr, const unsigned32 out_mask, const unsigned32 in_mask, const unsigned32 cr_mask
- const unsigned32 fp_mask = out_mask | in_mask;
+void::model-function::ppc_insn_float_cr:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask, const uint32_t cr_mask
+ const uint32_t fp_mask = out_mask | in_mask;
model_busy *busy_ptr;
if ((model_ptr->fp_busy & fp_mask) || (model_ptr->cr_fpscr_busy & cr_mask)) {
@@ -670,9 +670,9 @@ void::model-function::ppc_insn_float_cr:itable_index index, model_data *model_pt
# Schedule an instruction that takes both int/float input registers and produces output int/float registers
-void::model-function::ppc_insn_int_float:itable_index index, model_data *model_ptr, const unsigned32 out_int_mask, const unsigned32 out_fp_mask, const unsigned32 in_int_mask, const unsigned32 in_fp_mask
- const unsigned32 int_mask = out_int_mask | in_int_mask;
- const unsigned32 fp_mask = out_fp_mask | in_fp_mask;
+void::model-function::ppc_insn_int_float:itable_index index, model_data *model_ptr, const uint32_t out_int_mask, const uint32_t out_fp_mask, const uint32_t in_int_mask, const uint32_t in_fp_mask
+ const uint32_t int_mask = out_int_mask | in_int_mask;
+ const uint32_t fp_mask = out_fp_mask | in_fp_mask;
model_busy *busy_ptr;
if ((model_ptr->int_busy & int_mask) || (model_ptr->fp_busy & fp_mask)) {
@@ -698,7 +698,7 @@ void::model-function::ppc_insn_int_float:itable_index index, model_data *model_p
}
# Schedule an MFSPR instruction that takes 1 special purpose register and produces an integer output register
-void::model-function::ppc_insn_from_spr:itable_index index, model_data *model_ptr, const unsigned32 int_mask, const unsigned nSPR
+void::model-function::ppc_insn_from_spr:itable_index index, model_data *model_ptr, const uint32_t int_mask, const unsigned nSPR
model_busy *busy_ptr;
while ((model_ptr->int_busy & int_mask) != 0 || model_ptr->spr_busy[nSPR] != 0) {
@@ -717,7 +717,7 @@ void::model-function::ppc_insn_from_spr:itable_index index, model_data *model_pt
model_trace_make_busy(model_ptr, int_mask, 0, 0);
# Schedule an MTSPR instruction that takes 1 integer register and produces a special purpose output register
-void::model-function::ppc_insn_to_spr:itable_index index, model_data *model_ptr, const unsigned32 int_mask, const unsigned nSPR
+void::model-function::ppc_insn_to_spr:itable_index index, model_data *model_ptr, const uint32_t int_mask, const unsigned nSPR
model_busy *busy_ptr;
while ((model_ptr->int_busy & int_mask) != 0 || model_ptr->spr_busy[nSPR] != 0) {
@@ -735,8 +735,8 @@ void::model-function::ppc_insn_to_spr:itable_index index, model_data *model_ptr,
TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR)));
# Schedule a MFCR instruction that moves the CR into an integer register
-void::model-function::ppc_insn_mfcr:itable_index index, model_data *model_ptr, unsigned32 int_mask
- const unsigned32 cr_mask = 0xff;
+void::model-function::ppc_insn_mfcr:itable_index index, model_data *model_ptr, uint32_t int_mask
+ const uint32_t cr_mask = 0xff;
model_busy *busy_ptr;
while (((model_ptr->int_busy & int_mask) | (model_ptr->cr_fpscr_busy & cr_mask)) != 0) {
@@ -755,10 +755,10 @@ void::model-function::ppc_insn_mfcr:itable_index index, model_data *model_ptr, u
model_trace_make_busy(model_ptr, int_mask, 0, 0);
# Schedule a MTCR instruction that moves an integer register into the CR
-void::model-function::ppc_insn_mtcr:itable_index index, model_data *model_ptr, unsigned32 int_mask, unsigned FXM
+void::model-function::ppc_insn_mtcr:itable_index index, model_data *model_ptr, uint32_t int_mask, unsigned FXM
int f;
int nr_crs = 0;
- unsigned32 cr_mask = 0;
+ uint32_t cr_mask = 0;
const model_time *normal_time = &model_ptr->timing[index];
static const model_time ppc604_1bit_time = { PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1, 1, 0 };
model_busy *busy_ptr;
@@ -996,8 +996,8 @@ void::model-function::model_branch_predict:model_data *model_ptr, int success
#
# Convert 32bit single to 64bit double
-unsigned64::function::DOUBLE:unsigned32 WORD
- unsigned64 FRT;
+uint64_t::function::DOUBLE:uint32_t WORD
+ uint64_t FRT;
if (EXTRACTED32(WORD, 1, 8) > 0
&& EXTRACTED32(WORD, 1, 8) < 255) {
/* normalized operand */
@@ -1013,7 +1013,7 @@ unsigned64::function::DOUBLE:unsigned32 WORD
/* denormalized operand */
int sign = EXTRACTED32(WORD, 0, 0);
int exp = -126;
- unsigned64 frac = INSERTED64(EXTRACTED32(WORD, 9, 31), 1, (52 - 29));
+ uint64_t frac = INSERTED64(EXTRACTED32(WORD, 9, 31), 1, (52 - 29));
/* normalize the operand */
while (MASKED64(frac, 0, 0) == 0) {
frac <<= 1;
@@ -1038,8 +1038,8 @@ unsigned64::function::DOUBLE:unsigned32 WORD
return FRT;
# Convert 64bit single to 32bit double
-unsigned32::function::SINGLE:unsigned64 FRS
- unsigned32 WORD;
+uint32_t::function::SINGLE:uint64_t FRS
+ uint32_t WORD;
if (EXTRACTED64(FRS, 1, 11) > 896
|| EXTRACTED64(FRS, 1, 63) == 0) {
/* no denormalization required (includes Zero/Infinity/NaN) */
@@ -1051,7 +1051,7 @@ unsigned32::function::SINGLE:unsigned64 FRS
/* denormalization required */
int sign = EXTRACTED64(FRS, 0, 0);
int exp = EXTRACTED64(FRS, 1, 11) - 1023;
- unsigned64 frac = (BIT64(0)
+ uint64_t frac = (BIT64(0)
| INSERTED64(EXTRACTED64(FRS, 12, 63), 1, 52));
/* denormalize the operand */
while (exp < -126) {
@@ -1069,9 +1069,9 @@ unsigned32::function::SINGLE:unsigned64 FRS
# round 64bit double to 64bit but single
-void::function::Round_Single:cpu *processor, int sign, int *exp, unsigned64 *frac_grx
+void::function::Round_Single:cpu *processor, int sign, int *exp, uint64_t *frac_grx
/* comparisons ignore u bits */
- unsigned64 out;
+ uint64_t out;
int inc = 0;
int lsb = EXTRACTED64(*frac_grx, 23, 23);
int gbit = EXTRACTED64(*frac_grx, 24, 24);
@@ -1106,7 +1106,7 @@ void::function::Round_Single:cpu *processor, int sign, int *exp, unsigned64 *fra
#
-void::function::Round_Integer:cpu *processor, int sign, unsigned64 *frac, int *frac64, int gbit, int rbit, int xbit, fpscreg round_mode
+void::function::Round_Integer:cpu *processor, int sign, uint64_t *frac, int *frac64, int gbit, int rbit, int xbit, fpscreg round_mode
int inc = 0;
if (round_mode == fpscr_rn_round_to_nearest) {
if (*frac64 == 1 && gbit == 1) inc = 1;
@@ -1130,7 +1130,7 @@ void::function::Round_Integer:cpu *processor, int sign, unsigned64 *frac, int *f
FPSCR_SET_FI(gbit | rbit | xbit);
-void::function::Round_Float:cpu *processor, int sign, int *exp, unsigned64 *frac, fpscreg round_mode
+void::function::Round_Float:cpu *processor, int sign, int *exp, uint64_t *frac, fpscreg round_mode
int carry_out;
int inc = 0;
int lsb = EXTRACTED64(*frac, 52, 52);
@@ -1163,10 +1163,10 @@ void::function::Round_Float:cpu *processor, int sign, int *exp, unsigned64 *frac
# conversion of FP to integer
-void::function::convert_to_integer:cpu *processor, unsigned_word cia, unsigned64 *frt, unsigned64 frb, fpscreg round_mode, int tgt_precision
+void::function::convert_to_integer:cpu *processor, unsigned_word cia, uint64_t *frt, uint64_t frb, fpscreg round_mode, int tgt_precision
int i;
int exp = 0;
- unsigned64 frac = 0;
+ uint64_t frac = 0;
int frac64 = 0;
int gbit = 0;
int rbit = 0;
@@ -1206,16 +1206,16 @@ void::function::convert_to_integer:cpu *processor, unsigned_word cia, unsigned64
frac64 = (frac64 + 1) & 0x1;
}
if (tgt_precision == 32 /* can ignore frac64 in compare */
- && (signed64)frac > (signed64)MASK64(33+1, 63)/*2^31-1 >>1*/)
+ && (int64_t)frac > (int64_t)MASK64(33+1, 63)/*2^31-1 >>1*/)
GOTO(Large_Operand);
if (tgt_precision == 64 /* can ignore frac64 in compare */
- && (signed64)frac > (signed64)MASK64(1+1, 63)/*2^63-1 >>1*/)
+ && (int64_t)frac > (int64_t)MASK64(1+1, 63)/*2^63-1 >>1*/)
GOTO(Large_Operand);
if (tgt_precision == 32 /* can ignore frac64 in compare */
- && (signed64)frac < (signed64)MASK64(0, 32+1)/*-2^31 >>1*/)
+ && (int64_t)frac < (int64_t)MASK64(0, 32+1)/*-2^31 >>1*/)
GOTO(Large_Operand);
if (tgt_precision == 64 /* can ignore frac64 in compare */
- && (signed64)frac < (signed64)MASK64(0, 0+1)/*-2^63 >>1*/)
+ && (int64_t)frac < (int64_t)MASK64(0, 0+1)/*-2^63 >>1*/)
GOTO(Large_Operand);
FPSCR_SET_XX(FPSCR & fpscr_fi);
if (tgt_precision == 32)
@@ -1284,16 +1284,16 @@ void::function::convert_to_integer:cpu *processor, unsigned_word cia, unsigned64
# extract out raw fields of a FP number
-int::function::sign:unsigned64 FRS
+int::function::sign:uint64_t FRS
return (MASKED64(FRS, 0, 0)
? -1
: 1);
-int::function::biased_exp:unsigned64 frs, int single
+int::function::biased_exp:uint64_t frs, int single
if (single)
return EXTRACTED64(frs, 1, 8);
else
return EXTRACTED64(frs, 1, 11);
-unsigned64::function::fraction:unsigned64 frs, int single
+uint64_t::function::fraction:uint64_t frs, int single
if (single)
return EXTRACTED64(frs, 9, 31);
else
@@ -1301,50 +1301,50 @@ unsigned64::function::fraction:unsigned64 frs, int single
# a number?, each of the below return +1 or -1 (based on sign bit)
# if true.
-int::function::is_nor:unsigned64 frs, int single
+int::function::is_nor:uint64_t frs, int single
int exp = biased_exp(frs, single);
return (exp >= 1
&& exp <= (single ? 254 : 2046));
-int::function::is_zero:unsigned64 FRS
+int::function::is_zero:uint64_t FRS
return (MASKED64(FRS, 1, 63) == 0
? sign(FRS)
: 0);
-int::function::is_den:unsigned64 frs, int single
+int::function::is_den:uint64_t frs, int single
int exp = biased_exp(frs, single);
- unsigned64 frac = fraction(frs, single);
+ uint64_t frac = fraction(frs, single);
return (exp == 0 && frac != 0
? sign(frs)
: 0);
-int::function::is_inf:unsigned64 frs, int single
+int::function::is_inf:uint64_t frs, int single
int exp = biased_exp(frs, single);
- unsigned64 frac = fraction(frs, single);
+ uint64_t frac = fraction(frs, single);
return (exp == (single ? 255 : 2047) && frac == 0
? sign(frs)
: 0);
-int::function::is_NaN:unsigned64 frs, int single
+int::function::is_NaN:uint64_t frs, int single
int exp = biased_exp(frs, single);
- unsigned64 frac = fraction(frs, single);
+ uint64_t frac = fraction(frs, single);
return (exp == (single ? 255 : 2047) && frac != 0
? sign(frs)
: 0);
-int::function::is_SNaN:unsigned64 frs, int single
+int::function::is_SNaN:uint64_t frs, int single
return (is_NaN(frs, single)
&& !(frs & (single ? MASK64(9, 9) : MASK64(12, 12)))
? sign(frs)
: 0);
-int::function::is_QNaN:unsigned64 frs, int single
+int::function::is_QNaN:uint64_t frs, int single
return (is_NaN(frs, single) && !is_SNaN(frs, single));
-int::function::is_less_than:unsigned64 *fra, unsigned64 *frb
+int::function::is_less_than:uint64_t *fra, uint64_t *frb
return *(double*)fra < *(double*)frb;
-int::function::is_greater_than:unsigned64 *fra, unsigned64 *frb
+int::function::is_greater_than:uint64_t *fra, uint64_t *frb
return *(double*)fra > *(double*)frb;
-int::function::is_equan_to:unsigned64 *fra, unsigned64 *frb
+int::function::is_equan_to:uint64_t *fra, uint64_t *frb
return *(double*)fra == *(double*)frb;
# which quiet nan should become the result
-unsigned64::function::select_qnan:unsigned64 fra, unsigned64 frb, unsigned64 frc, int instruction_is_frsp, int generate_qnan, int single
- unsigned64 frt = 0;
+uint64_t::function::select_qnan:uint64_t fra, uint64_t frb, uint64_t frc, int instruction_is_frsp, int generate_qnan, int single
+ uint64_t frt = 0;
if (is_NaN(fra, single))
frt = fra;
else if (is_NaN(frb, single))
@@ -1362,7 +1362,7 @@ unsigned64::function::select_qnan:unsigned64 fra, unsigned64 frb, unsigned64 frc
# detect invalid operation
-int::function::is_invalid_operation:cpu *processor, unsigned_word cia, unsigned64 fra, unsigned64 frb, fpscreg check, int single, int negate
+int::function::is_invalid_operation:cpu *processor, unsigned_word cia, uint64_t fra, uint64_t frb, fpscreg check, int single, int negate
int fail = 0;
if ((check & fpscr_vxsnan)
&& (is_SNaN(fra, single) || is_SNaN(frb, single))) {
@@ -1419,7 +1419,7 @@ int::function::is_invalid_operation:cpu *processor, unsigned_word cia, unsigned6
# handle case of invalid operation
-void::function::invalid_arithemetic_operation:cpu *processor, unsigned_word cia, unsigned64 *frt, unsigned64 fra, unsigned64 frb, unsigned64 frc, int instruction_is_frsp, int instruction_is_convert_to_64bit, int instruction_is_convert_to_32bit, int single
+void::function::invalid_arithemetic_operation:cpu *processor, unsigned_word cia, uint64_t *frt, uint64_t fra, uint64_t frb, uint64_t frc, int instruction_is_frsp, int instruction_is_convert_to_64bit, int instruction_is_convert_to_32bit, int single
if (FPSCR & fpscr_ve) {
/* invalid operation exception enabled */
/* FRT unchaged */
@@ -1448,7 +1448,7 @@ void::function::invalid_arithemetic_operation:cpu *processor, unsigned_word cia,
# detect divide by zero
-int::function::is_invalid_zero_divide:cpu *processor, unsigned_word cia, unsigned64 fra, unsigned64 frb, int single
+int::function::is_invalid_zero_divide:cpu *processor, unsigned_word cia, uint64_t fra, uint64_t frb, int single
int fail = 0;
if (is_zero (frb)) {
FPSCR_SET_ZX (1);
@@ -1460,7 +1460,7 @@ int::function::is_invalid_zero_divide:cpu *processor, unsigned_word cia, unsigne
# handle case of invalid operation
-void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, unsigned64 *frt, unsigned64 fra, unsigned64 frb, int single
+void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, uint64_t *frt, uint64_t fra, uint64_t frb, int single
if (FPSCR & fpscr_ze) {
/* zero-divide exception enabled */
/* FRT unchaged */
@@ -2696,9 +2696,9 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603: PPC_UNIT_IU, PPC_UNIT_IU, 5, 5, 0
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 5, 5, 0
*604: PPC_UNIT_MCIU, PPC_UNIT_MCIU, 4, 4, 0
- signed64 a = (signed32)(*rA);
- signed64 b = (signed32)(*rB);
- signed64 prod = a * b;
+ int64_t a = (int32_t)(*rA);
+ int64_t b = (int32_t)(*rB);
+ int64_t prod = a * b;
signed_word t = prod;
*rT = *rA * *rB;
if (t != prod && OE)
@@ -2713,9 +2713,9 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603: PPC_UNIT_IU, PPC_UNIT_IU, 5, 5, 0
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 5, 5, 0
*604: PPC_UNIT_MCIU, PPC_UNIT_MCIU, 4, 4, 0
- signed64 a = (signed32)(*rA);
- signed64 b = (signed32)(*rB);
- signed64 prod = a * b;
+ int64_t a = (int32_t)(*rA);
+ int64_t b = (int32_t)(*rB);
+ int64_t prod = a * b;
signed_word t = EXTRACTED64(prod, 0, 31);
*rT = t;
CR0_COMPARE(t, 0, Rc);
@@ -2728,9 +2728,9 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603: PPC_UNIT_IU, PPC_UNIT_IU, 6, 6, 0
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 6, 6, 0
*604: PPC_UNIT_MCIU, PPC_UNIT_MCIU, 4, 4, 0
- unsigned64 a = (unsigned32)(*rA);
- unsigned64 b = (unsigned32)(*rB);
- unsigned64 prod = a * b;
+ uint64_t a = (uint32_t)(*rA);
+ uint64_t b = (uint32_t)(*rB);
+ uint64_t prod = a * b;
signed_word t = EXTRACTED64(prod, 0, 31);
*rT = t;
CR0_COMPARE(t, 0, Rc);
@@ -2743,8 +2743,8 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603: PPC_UNIT_IU, PPC_UNIT_IU, 37, 37, 0
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 37, 37, 0
*604: PPC_UNIT_MCIU, PPC_UNIT_MCIU, 20, 20, 0
- signed64 dividend = (signed32)(*rA);
- signed64 divisor = (signed32)(*rB);
+ int64_t dividend = (int32_t)(*rA);
+ int64_t divisor = (int32_t)(*rB);
if (divisor == 0 /* nb 0x8000..0 is sign extended */
|| (dividend == 0x80000000 && divisor == -1)) {
if (OE)
@@ -2752,7 +2752,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
CR0_COMPARE(0, 0, Rc);
}
else {
- signed64 quotent = dividend / divisor;
+ int64_t quotent = dividend / divisor;
*rT = quotent;
CR0_COMPARE((signed_word)quotent, 0, Rc);
}
@@ -2765,15 +2765,15 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603: PPC_UNIT_IU, PPC_UNIT_IU, 37, 37, 0
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 37, 37, 0
*604: PPC_UNIT_MCIU, PPC_UNIT_MCIU, 20, 20, 0
- unsigned64 dividend = (unsigned32)(*rA);
- unsigned64 divisor = (unsigned32)(*rB);
+ uint64_t dividend = (uint32_t)(*rA);
+ uint64_t divisor = (uint32_t)(*rB);
if (divisor == 0) {
if (OE)
XER |= (xer_overflow | xer_summary_overflow);
CR0_COMPARE(0, 0, Rc);
}
else {
- unsigned64 quotent = dividend / divisor;
+ uint64_t quotent = dividend / divisor;
*rT = quotent;
CR0_COMPARE((signed_word)quotent, 0, Rc);
}
@@ -3088,7 +3088,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603: PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*604: PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1, 1, 0
- *rA = (signed_word)(signed8)*rS;
+ *rA = (signed_word)(int8_t)*rS;
CR0_COMPARE(*rA, 0, Rc);
ITRACE(trace_alu, (" Result = %ld (0x%lx)\n", (long)*rA, (long)*rA));
PPC_INSN_INT(RA_BITMASK, RS_BITMASK, Rc);
@@ -3098,7 +3098,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603: PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*604: PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1, 1, 0
- *rA = (signed_word)(signed16)*rS;
+ *rA = (signed_word)(int16_t)*rS;
CR0_COMPARE(*rA, 0, Rc);
ITRACE(trace_alu, (" Result = %ld (0x%lx)\n", (long)*rA, (long)*rA));
PPC_INSN_INT(RA_BITMASK, RS_BITMASK, Rc);
@@ -3108,13 +3108,13 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603: PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*604: PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1, 1, 0
-# *rA = (signed_word)(signed32)*rS;
+# *rA = (signed_word)(int32_t)*rS;
# CR0_COMPARE(*rA, 0, Rc);
0.31,6.RS,11.RA,16./,21.58,31.Rc:X:64::Count Leading Zeros Doubleword
# int count = 0;
-# unsigned64 mask = BIT64(0);
-# unsigned64 source = *rS;
+# uint64_t mask = BIT64(0);
+# uint64_t source = *rS;
# while (!(source & mask) && mask != 0) {
# mask >>= 1;
# count++;
@@ -3128,8 +3128,8 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*604: PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1, 1, 0
int count = 0;
- unsigned32 mask = BIT32(0);
- unsigned32 source = *rS;
+ uint32_t mask = BIT32(0);
+ uint32_t source = *rS;
while (!(source & mask) && mask != 0) {
mask >>= 1;
count++;
@@ -3177,9 +3177,9 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*604: PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1, 1, 0
long n = SH;
- unsigned32 s = *rS;
- unsigned32 r = ROTL32(s, n);
- unsigned32 m = MASK(MB+32, ME+32);
+ uint32_t s = *rS;
+ uint32_t r = ROTL32(s, n);
+ uint32_t m = MASK(MB+32, ME+32);
signed_word result = r & m;
*rA = result;
CR0_COMPARE(result, 0, Rc);
@@ -3209,8 +3209,8 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
0.23,6.RS,11.RA,16.RB,21.MB,26.ME,31.Rc:M:::Rotate Left Word then AND with Mask
long n = MASKED(*rB, 59, 63);
- unsigned32 r = ROTL32(*rS, n);
- unsigned32 m = MASK(MB+32, ME+32);
+ uint32_t r = ROTL32(*rS, n);
+ uint32_t m = MASK(MB+32, ME+32);
signed_word result = r & m;
*rA = result;
CR0_COMPARE(result, 0, Rc);
@@ -3230,8 +3230,8 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*604: PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1, 1, 0
long n = SH;
- unsigned32 r = ROTL32(*rS, n);
- unsigned32 m = MASK(MB+32, ME+32);
+ uint32_t r = ROTL32(*rS, n);
+ uint32_t m = MASK(MB+32, ME+32);
signed_word result = (r & m) | (*rA & ~m);
*rA = result;
ITRACE(trace_alu, (": n=%ld *rS=0x%lx r=0x%lx m=0x%lx result=0x%lx\n",
@@ -3249,7 +3249,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*604: PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1, 1, 0
int n = MASKED(*rB, 58, 63);
- unsigned32 source = *rS;
+ uint32_t source = *rS;
signed_word shifted;
if (n < 32)
shifted = (source << n);
@@ -3270,7 +3270,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*604: PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1, 1, 0
int n = MASKED(*rB, 58, 63);
- unsigned32 source = *rS;
+ uint32_t source = *rS;
signed_word shifted;
if (n < 32)
shifted = (source >> n);
@@ -3312,18 +3312,18 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603: PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*603e:PPC_UNIT_IU, PPC_UNIT_IU, 1, 1, 0
*604: PPC_UNIT_SCIU1, PPC_UNIT_SCIU2, 1, 1, 0
- unsigned64 mask;
+ uint64_t mask;
int n = MASKED(*rB, 59, 63);
- signed32 source = (signed32)*rS; /* signed to keep sign bit */
+ int32_t source = (int32_t)*rS; /* signed to keep sign bit */
int S = (MASKED(*rS,32,32) != 0);
- signed64 r = ((unsigned64) source);
- r = ((unsigned64) source) << 32 | (unsigned32) source;
+ int64_t r = ((uint64_t) source);
+ r = ((uint64_t) source) << 32 | (uint32_t) source;
r = ROTL64(r,64-n);
if (MASKED(*rB,58,58) == 0)
- mask = (unsigned64) MASK64(n+32,63);
+ mask = (uint64_t) MASK64(n+32,63);
else
- mask = (unsigned64) 0;
- *rA = (signed_word) ((r & mask) | (((signed64) -1*S) & ~mask)); /* if 64bit will sign extend */
+ mask = (uint64_t) 0;
+ *rA = (signed_word) ((r & mask) | (((int64_t) -1*S) & ~mask)); /* if 64bit will sign extend */
if (S && (MASKED(r & ~mask,32,63)!=0))
XER |= xer_carry;
else
@@ -3450,7 +3450,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*603: PPC_UNIT_SRU, PPC_UNIT_SRU, 1, 1, 0
*603e:PPC_UNIT_SRU, PPC_UNIT_SRU, 1, 1, 0
*604: PPC_UNIT_MCIU, PPC_UNIT_MCIU, 3, 3, 0
- *rT = (unsigned32)CR;
+ *rT = (uint32_t)CR;
PPC_INSN_MFCR(RT_BITMASK);
#
@@ -3971,7 +3971,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
fpscr_vxsnan | fpscr_vximz,
0, /*single?*/
0) /*negate?*/) {
- union { double d; unsigned64 u; } tmp;
+ union { double d; uint64_t u; } tmp;
invalid_arithemetic_operation(processor, cia,
&tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
@@ -4018,7 +4018,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
fpscr_vxsnan | fpscr_vximz,
1, /*single?*/
0) /*negate?*/) {
- union { double d; unsigned64 u; } tmp;
+ union { double d; uint64_t u; } tmp;
invalid_arithemetic_operation(processor, cia,
&tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
@@ -4065,7 +4065,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
fpscr_vxsnan | fpscr_vximz,
0, /*single?*/
0) /*negate?*/) {
- union { double d; unsigned64 u; } tmp;
+ union { double d; uint64_t u; } tmp;
invalid_arithemetic_operation(processor, cia,
&tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
@@ -4112,7 +4112,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
fpscr_vxsnan | fpscr_vximz,
1, /*single?*/
0) /*negate?*/) {
- union { double d; unsigned64 u; } tmp;
+ union { double d; uint64_t u; } tmp;
invalid_arithemetic_operation(processor, cia,
&tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
@@ -4159,7 +4159,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
fpscr_vxsnan | fpscr_vximz,
0, /*single?*/
0) /*negate?*/) {
- union { double d; unsigned64 u; } tmp;
+ union { double d; uint64_t u; } tmp;
invalid_arithemetic_operation(processor, cia,
&tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
@@ -4206,7 +4206,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
fpscr_vxsnan | fpscr_vximz,
1, /*single?*/
0) /*negate?*/) {
- union { double d; unsigned64 u; } tmp;
+ union { double d; uint64_t u; } tmp;
invalid_arithemetic_operation(processor, cia,
&tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
@@ -4253,7 +4253,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
fpscr_vxsnan | fpscr_vximz,
0, /*single?*/
0) /*negate?*/) {
- union { double d; unsigned64 u; } tmp;
+ union { double d; uint64_t u; } tmp;
invalid_arithemetic_operation(processor, cia,
&tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
@@ -4300,7 +4300,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
fpscr_vxsnan | fpscr_vximz,
1, /*single?*/
0) /*negate?*/) {
- union { double d; unsigned64 u; } tmp;
+ union { double d; uint64_t u; } tmp;
invalid_arithemetic_operation(processor, cia,
&tmp.u, *frA, 0, *frC,
0, /*instruction_is_frsp*/
@@ -4346,7 +4346,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
*604: PPC_UNIT_FPU, PPC_UNIT_FPU, 1, 3, 0
int sign;
int exp;
- unsigned64 frac_grx;
+ uint64_t frac_grx;
/***/
/* split off cases for what to do */
if (EXTRACTED64(*frB, 1, 11) < 897
@@ -4582,7 +4582,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
0.63,6.FRT,11./,16.FRB,21.846,31.Rc:X:64,f::Floating Convert from Integer Doubleword
int sign = EXTRACTED64(*frB, 0, 0);
int exp = 63;
- unsigned64 frac = *frB;
+ uint64_t frac = *frB;
/***/
if (frac == 0) GOTO(Zero_Operand);
if (sign == 1) frac = ~frac + 1;
@@ -4699,13 +4699,13 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
0.63,6.BT,11./,16./,21.70,31.Rc:X:f::Move To FPSCR Bit 0
FPSCR_BEGIN;
- unsigned32 bit = BIT32(BT);
+ uint32_t bit = BIT32(BT);
FPSCR &= ~bit;
FPSCR_END(Rc);
0.63,6.BT,11./,16./,21.38,31.Rc:X:f::Move To FPSCR Bit 1
FPSCR_BEGIN;
- unsigned32 bit = BIT32(BT);
+ uint32_t bit = BIT32(BT);
if (bit & fpscr_fi)
bit |= fpscr_xx;
if ((bit & fpscr_vx_bits))
@@ -4744,7 +4744,7 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia,
if (CURRENT_MODEL == MODEL_ppc601) {
program_interrupt(processor, cia, optional_instruction_program_interrupt);
} else {
- unsigned64 zero = 0;
+ uint64_t zero = 0;
FPSCR_BEGIN;
if (is_NaN(*frA, 0) || is_less_than (frA, &zero)) *frT = *frB;
else *frT = *frC;
diff --git a/sim/ppc/psim.c b/sim/ppc/psim.c
index 34291b40cf8f..9f1db675e509 100644
--- a/sim/ppc/psim.c
+++ b/sim/ppc/psim.c
@@ -873,7 +873,7 @@ psim_read_register(psim *system,
break;
case reg_evr:
- *(unsigned64*)cooked_buf = EVR(description.index);
+ *(uint64_t*)cooked_buf = EVR(description.index);
break;
case reg_acc:
@@ -1046,8 +1046,8 @@ psim_write_register(psim *system,
case reg_evr:
{
- unsigned64 v;
- v = *(unsigned64*)cooked_buf;
+ uint64_t v;
+ v = *(uint64_t*)cooked_buf;
cpu_registers(processor)->e500.gprh[description.index] = v >> 32;
cpu_registers(processor)->gpr[description.index] = v;
break;
diff --git a/sim/ppc/registers.c b/sim/ppc/registers.c
index 2bab55a65fca..0ebb2a7a99d0 100644
--- a/sim/ppc/registers.c
+++ b/sim/ppc/registers.c
@@ -155,7 +155,7 @@ register_description(const char reg[])
else if (reg[0] == 'e' && reg[1] == 'v' && are_digits(reg + 2)) {
description.type = reg_evr;
description.index = atoi(reg+2);
- description.size = sizeof(unsigned64);
+ description.size = sizeof(uint64_t);
}
else if (reg[0] == 'r' && reg[1] == 'h' && are_digits(reg + 2)) {
description.type = reg_gprh;
@@ -165,7 +165,7 @@ register_description(const char reg[])
else if (!strcmp(reg, "acc")) {
description.type = reg_acc;
description.index = 0;
- description.size = sizeof(unsigned64);
+ description.size = sizeof(uint64_t);
}
#endif
else {
diff --git a/sim/ppc/registers.h b/sim/ppc/registers.h
index ffedf4b0e40c..eb15bca03802 100644
--- a/sim/ppc/registers.h
+++ b/sim/ppc/registers.h
@@ -53,7 +53,7 @@ typedef signed_word gpreg;
** Floating Point Registers
**/
-typedef unsigned64 fpreg;
+typedef uint64_t fpreg;
@@ -62,7 +62,7 @@ typedef unsigned64 fpreg;
**
**/
-typedef unsigned32 creg;
+typedef uint32_t creg;
/* The following sub bits are defined for the condition register */
enum {
@@ -106,7 +106,7 @@ enum {
** Floating-Point Status and Control Register
**/
-typedef unsigned32 fpscreg;
+typedef uint32_t fpscreg;
enum {
fpscr_fx_bit = 0,
fpscr_fx = BIT32(0),
@@ -170,7 +170,7 @@ enum {
** XER Register
**/
-typedef unsigned32 xereg;
+typedef uint32_t xereg;
enum {
xer_summary_overflow = BIT32(0), xer_summary_overflow_bit = 0,
@@ -192,7 +192,7 @@ enum {
** Segment Registers
**/
-typedef unsigned32 sreg;
+typedef uint32_t sreg;
enum {
nr_of_srs = 16
};
diff --git a/sim/ppc/sim-main.h b/sim/ppc/sim-main.h
index 047b36cbce4b..3a9c2e71f9a6 100644
--- a/sim/ppc/sim-main.h
+++ b/sim/ppc/sim-main.h
@@ -1,6 +1,6 @@
#include "sim-basics.h"
-typedef unsigned32 sim_cia;
+typedef uint32_t sim_cia;
#include "sim-base.h"
diff --git a/sim/ppc/tree.c b/sim/ppc/tree.c
index 4df862bb2867..6d20665505ea 100644
--- a/sim/ppc/tree.c
+++ b/sim/ppc/tree.c
@@ -855,7 +855,7 @@ tree_parse(device *current,
break;
case '[':
{
- unsigned8 words[1024];
+ uint8_t words[1024];
char *curr = spec.value + 1;
int nr_words = 0;
while (1) {
@@ -1050,7 +1050,7 @@ print_properties(device *me)
}
}
else {
- unsigned8 *w = (unsigned8*)property->array;
+ uint8_t *w = (uint8_t*)property->array;
printf_filtered(" [");
while ((char*)w - (char*)property->array < property->sizeof_array) {
printf_filtered(" 0x%2x", BE2H_1(*w));
diff --git a/sim/ppc/words.h b/sim/ppc/words.h
index df9278ad1166..e4a9ec13f283 100644
--- a/sim/ppc/words.h
+++ b/sim/ppc/words.h
@@ -27,8 +27,8 @@
/* TYPES:
- signed* signed type of the given size
- unsigned* The corresponding insigned type
+ intNN_t Signed type of the given bit size
+ uintNN_t The corresponding unsigned type
SIZES
@@ -47,27 +47,16 @@
#include <stdint.h>
-/* bit based */
-typedef int8_t signed8;
-typedef int16_t signed16;
-typedef int32_t signed32;
-typedef int64_t signed64;
-
-typedef uint8_t unsigned8;
-typedef uint16_t unsigned16;
-typedef uint32_t unsigned32;
-typedef uint64_t unsigned64;
-
/* byte based */
-typedef signed8 signed_1;
-typedef signed16 signed_2;
-typedef signed32 signed_4;
-typedef signed64 signed_8;
+typedef int8_t signed_1;
+typedef int16_t signed_2;
+typedef int32_t signed_4;
+typedef int64_t signed_8;
-typedef unsigned8 unsigned_1;
-typedef unsigned16 unsigned_2;
-typedef unsigned32 unsigned_4;
-typedef unsigned64 unsigned_8;
+typedef uint8_t unsigned_1;
+typedef uint16_t unsigned_2;
+typedef uint32_t unsigned_4;
+typedef uint64_t unsigned_8;
/* for general work, the following are defined */
@@ -78,19 +67,19 @@ typedef unsigned64 unsigned_8;
/* target architecture based */
#if (WITH_TARGET_WORD_BITSIZE == 64)
-typedef unsigned64 unsigned_word;
-typedef signed64 signed_word;
+typedef uint64_t unsigned_word;
+typedef int64_t signed_word;
#else
-typedef unsigned32 unsigned_word;
-typedef signed32 signed_word;
+typedef uint32_t unsigned_word;
+typedef int32_t signed_word;
#endif
/* Other instructions */
-typedef unsigned32 instruction_word;
+typedef uint32_t instruction_word;
/* IEEE 1275 cell size - only support 32bit mode at present */
-typedef unsigned32 unsigned_cell;
-typedef signed32 signed_cell;
+typedef uint32_t unsigned_cell;
+typedef int32_t signed_cell;
#endif /* _WORDS_H_ */
--
2.33.0
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-01-01 20:56 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-01 20:55 [PATCH 01/17] sim: cr16: migrate to standard uintXX_t types Mike Frysinger
2022-01-01 20:55 ` [PATCH 02/17] sim: d10v: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 03/17] sim: m68hc11: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 04/17] sim: v850: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 05/17] sim: mn10300: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 06/17] sim: erc32: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 07/17] sim: testsuite: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 08/17] sim: bfin: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 09/17] sim: riscv: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 10/17] sim: msp430: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 11/17] sim: synacor: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 12/17] sim: iq2000: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 13/17] sim: cris: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 14/17] sim: mips: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 15/17] sim: igen: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 16/17] sim: common: " Mike Frysinger
2022-01-01 20:55 ` [PATCH 17/17] sim: ppc: " Mike Frysinger
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