[RFC] gdb: RISC-V: Add support for RV64E/lp64e

[RFC] gdb: RISC-V: Add support for RV64E/lp64e

[Palmer Dabbelt]

RV64E is a legal base ISA, so don't convert 64-bit binaries with the RVE
flag set to 32-bit binaries.  This also adds the missing bits of support
for RV64E/LP64E wherever RV32E/ILP32E was.
---
This is all still in flight, but evidently RV64E exists so converting
64-bit binaries with the E flag set to 32-bit binaries isn't correct.
I haven't tested this at all, but given that we don't even have the ABI
docs lined up yet it's likely a bit away from being mergable.

It's probably also worth refactoring a handful of these, as we now have
exactly the same handling for RV32 and RV64 in a handful of places
(aside from some names).
---
 gdb/arch/riscv.c                   | 15 +++++++++++++--
 gdb/arch/riscv.h                   |  2 +-
 gdb/features/Makefile              |  1 +
 gdb/features/riscv/rv64e-xregs.c   | 30 +++++++++++++++++++++++++++++
 gdb/features/riscv/rv64e-xregs.xml | 31 ++++++++++++++++++++++++++++++
 gdb/riscv-tdep.c                   | 11 ++---------
 6 files changed, 78 insertions(+), 12 deletions(-)
 create mode 100644 gdb/features/riscv/rv64e-xregs.c
 create mode 100644 gdb/features/riscv/rv64e-xregs.xml

diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c
index 030c2cfdd98..ee238a4b5fa 100644
--- a/gdb/arch/riscv.c
+++ b/gdb/arch/riscv.c
@@ -25,6 +25,7 @@
 #include "../features/riscv/32bit-fpu.c"
 #include "../features/riscv/64bit-fpu.c"
 #include "../features/riscv/rv32e-xregs.c"
+#include "../features/riscv/rv64e-xregs.c"
 
 #ifndef GDBSERVER
 #define STATIC_IN_GDB static
@@ -51,7 +52,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features)
 	arch_name.append (":rv32i");
     }
   else if (features.xlen == 8)
-    arch_name.append (":rv64i");
+    {
+      if (features.embedded)
+	arch_name.append (":rv64e");
+      else
+	arch_name.append (":rv64i");
+    }
   else if (features.xlen == 16)
     arch_name.append (":rv128i");
 
@@ -76,7 +82,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features)
 	regnum = create_feature_riscv_32bit_cpu (tdesc.get (), regnum);
     }
   else if (features.xlen == 8)
-    regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum);
+    {
+      if (features.embedded)
+	regnum = create_feature_riscv_rv64e_xregs (tdesc.get (), regnum);
+      else
+	regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum);
+    }
 
   /* For now we only support creating 32-bit or 64-bit f-registers.  */
   if (features.flen == 4)
diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index 0aef54638fe..e2f989ab909 100644
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -52,7 +52,7 @@ struct riscv_gdbarch_features
      any vector size.  */
   int vlen = 0;
 
-  /* When true this target is RV32E.  */
+  /* When true this target is RVE.  */
   bool embedded = false;
 
   /* Equality operator.  */
diff --git a/gdb/features/Makefile b/gdb/features/Makefile
index 15d623c2681..b522a5bc906 100644
--- a/gdb/features/Makefile
+++ b/gdb/features/Makefile
@@ -232,6 +232,7 @@ FEATURE_XMLFILES = aarch64-core.xml \
 	loongarch/base32.xml \
 	loongarch/base64.xml \
 	riscv/rv32e-xregs.xml \
+	riscv/rv64e-xregs.xml \
 	riscv/32bit-cpu.xml \
 	riscv/32bit-fpu.xml \
 	riscv/64bit-cpu.xml \
diff --git a/gdb/features/riscv/rv64e-xregs.c b/gdb/features/riscv/rv64e-xregs.c
new file mode 100644
index 00000000000..4346c3004ba
--- /dev/null
+++ b/gdb/features/riscv/rv64e-xregs.c
@@ -0,0 +1,30 @@
+/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
+  Original: rv64e-xregs.xml */
+
+#include "gdbsupport/tdesc.h"
+
+static int
+create_feature_riscv_rv64e_xregs (struct target_desc *result, long regnum)
+{
+  struct tdesc_feature *feature;
+
+  feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.cpu");
+  tdesc_create_reg (feature, "zero", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "ra", regnum++, 1, NULL, 64, "code_ptr");
+  tdesc_create_reg (feature, "sp", regnum++, 1, NULL, 64, "data_ptr");
+  tdesc_create_reg (feature, "gp", regnum++, 1, NULL, 64, "data_ptr");
+  tdesc_create_reg (feature, "tp", regnum++, 1, NULL, 64, "data_ptr");
+  tdesc_create_reg (feature, "t0", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "t1", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "t2", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "fp", regnum++, 1, NULL, 64, "data_ptr");
+  tdesc_create_reg (feature, "s1", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a0", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a1", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a2", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a3", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a4", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "a5", regnum++, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "pc", regnum++, 1, NULL, 64, "code_ptr");
+  return regnum;
+}
diff --git a/gdb/features/riscv/rv64e-xregs.xml b/gdb/features/riscv/rv64e-xregs.xml
new file mode 100644
index 00000000000..0c114fb95e2
--- /dev/null
+++ b/gdb/features/riscv/rv64e-xregs.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+     compatibility with older versions of tools that didn't use xml
+     register descriptions.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+  <reg name="zero" bitsize="64" type="int" regnum="0"/>
+  <reg name="ra" bitsize="64" type="code_ptr"/>
+  <reg name="sp" bitsize="64" type="data_ptr"/>
+  <reg name="gp" bitsize="64" type="data_ptr"/>
+  <reg name="tp" bitsize="64" type="data_ptr"/>
+  <reg name="t0" bitsize="64" type="int"/>
+  <reg name="t1" bitsize="64" type="int"/>
+  <reg name="t2" bitsize="64" type="int"/>
+  <reg name="fp" bitsize="64" type="data_ptr"/>
+  <reg name="s1" bitsize="64" type="int"/>
+  <reg name="a0" bitsize="64" type="int"/>
+  <reg name="a1" bitsize="64" type="int"/>
+  <reg name="a2" bitsize="64" type="int"/>
+  <reg name="a3" bitsize="64" type="int"/>
+  <reg name="a4" bitsize="64" type="int"/>
+  <reg name="a5" bitsize="64" type="int"/>
+  <reg name="pc" bitsize="64" type="code_ptr"/>
+</feature>
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 69f2123dcdb..b74d0321013 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -2269,7 +2269,7 @@ struct riscv_call_info
     flen = riscv_abi_flen (gdbarch);
 
     /* Reduce the number of integer argument registers when using the
-       embedded abi (i.e. rv32e).  */
+       embedded abi (i.e. rve).  */
     if (riscv_abi_embedded (gdbarch))
       int_regs.last_regnum = RISCV_A0_REGNUM + 5;
 
@@ -3462,14 +3462,7 @@ riscv_features_from_bfd (const bfd *abfd)
 	features.flen = 4;
 
       if (e_flags & EF_RISCV_RVE)
-	{
-	  if (features.xlen == 8)
-	    {
-	      warning (_("64-bit ELF with RV32E flag set!  Assuming 32-bit"));
-	      features.xlen = 4;
-	    }
-	  features.embedded = true;
-	}
+	features.embedded = true;
     }
 
   return features;
-- 
2.34.1