[PATCH] [gdb/riscv] Fix test for riscv: zero register.

[Mark Goncharov <mark.goncharov@syntacore.com>]

From: mga-sc <mark.goncharov@syntacore.com>

x0 register in riscv must have permanent value.
We already have test for that: gdb/testsuite/riscv-reg-aliases.exp.
This patch fixes 4 test drops.
---
 gdb/riscv-tdep.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 2d41be96b20..20b613075d5 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -933,6 +933,12 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
   return name;
 }
 
+static int
+riscv_cannot_store_register (struct gdbarch *gdbarch, int regnum)
+{
+  return regnum == RISCV_ZERO_REGNUM;
+}
+
 /* Construct a type for 64-bit FP registers.  */
 
 static struct type *
@@ -3822,6 +3828,9 @@ riscv_gdbarch_init (struct gdbarch_info info,
      registers, no matter what the target description called them.  */
   set_gdbarch_register_name (gdbarch, riscv_register_name);
 
+  /* Zero register must have permanent value. */
+  set_gdbarch_cannot_store_register (gdbarch, riscv_cannot_store_register);
+
   /* Override the register group callback setup by the target description
      mechanism.  This allows us to force registers into the groups we
      want, ignoring what the target tells us.  */
-- 
2.37.1