From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 1/5] sim: riscv: drop subdir configure logic
Date: Mon, 7 Nov 2022 23:24:22 +0700 [thread overview]
Message-ID: <20221107162426.26097-1-vapier@gentoo.org> (raw)
We've been using this only to set the default word size to 32-vs-64
based on the $target. We can easily merge this with the top-level
configure script to clean things up a bit.
---
sim/Makefile.in | 16 +-
sim/configure | 32 +-
sim/configure.ac | 3 +-
sim/riscv/Makefile.in | 2 +
sim/riscv/acinclude.m4 | 21 +
sim/riscv/aclocal.m4 | 16 -
sim/riscv/configure | 3096 ----------------------------------------
sim/riscv/configure.ac | 17 -
8 files changed, 65 insertions(+), 3138 deletions(-)
create mode 100644 sim/riscv/acinclude.m4
delete mode 100644 sim/riscv/aclocal.m4
delete mode 100755 sim/riscv/configure
delete mode 100644 sim/riscv/configure.ac
diff --git a/sim/configure.ac b/sim/configure.ac
index 8bde2a49fdfc..97cea4b6dd8b 100644
--- a/sim/configure.ac
+++ b/sim/configure.ac
@@ -150,7 +150,7 @@ if test "${enable_sim}" != no; then
SIM_TARGET([or1k*-*-*], [or1k], [true])
SIM_TARGET([powerpc*-*-*], [ppc], [true])
SIM_TARGET([pru*-*-*], [pru])
- SIM_TARGET([riscv*-*-*], [riscv], [true])
+ SIM_TARGET([riscv*-*-*], [riscv])
SIM_TARGET([rl78-*-*], [rl78])
SIM_TARGET([rx-*-*], [rx])
SIM_TARGET([sh*-*-*], [sh])
@@ -203,6 +203,7 @@ AC_SUBST(sim_float)
dnl Some arches have unique configure flags.
m4_include([frv/acinclude.m4])
+m4_include([riscv/acinclude.m4])
m4_include([rx/acinclude.m4])
dnl Hack to output an "include" statement in the Makefile so automake doesn't
diff --git a/sim/riscv/Makefile.in b/sim/riscv/Makefile.in
index 9aa663b515a5..25a83f938982 100644
--- a/sim/riscv/Makefile.in
+++ b/sim/riscv/Makefile.in
@@ -24,4 +24,6 @@ SIM_OBJS = \
machs.o \
sim-main.o
+SIM_EXTRA_CFLAGS = -DWITH_TARGET_WORD_BITSIZE=@SIM_RISCV_BITSIZE@
+
## COMMON_POST_CONFIG_FRAG
diff --git a/sim/riscv/acinclude.m4 b/sim/riscv/acinclude.m4
new file mode 100644
index 000000000000..29dcaebc61d6
--- /dev/null
+++ b/sim/riscv/acinclude.m4
@@ -0,0 +1,21 @@
+dnl Copyright (C) 2022 Free Software Foundation, Inc.
+dnl
+dnl This program is free software; you can redistribute it and/or modify
+dnl it under the terms of the GNU General Public License as published by
+dnl the Free Software Foundation; either version 3 of the License, or
+dnl (at your option) any later version.
+dnl
+dnl This program is distributed in the hope that it will be useful,
+dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
+dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+dnl GNU General Public License for more details.
+dnl
+dnl You should have received a copy of the GNU General Public License
+dnl along with this program. If not, see <http://www.gnu.org/licenses/>.
+dnl
+dnl NB: This file is included in sim/configure, so keep settings namespaced.
+AC_MSG_CHECKING([riscv bitsize])
+SIM_RISCV_BITSIZE=64
+AS_CASE([$target],
+ [riscv32*], [SIM_RISCV_BITSIZE=32])
+AC_SUBST(SIM_RISCV_BITSIZE)
diff --git a/sim/riscv/configure.ac b/sim/riscv/configure.ac
deleted file mode 100644
index 0e74a1edda5c..000000000000
--- a/sim/riscv/configure.ac
+++ /dev/null
@@ -1,17 +0,0 @@
-dnl Process this file with autoconf to produce a configure script.
-AC_INIT(Makefile.in)
-AC_CONFIG_MACRO_DIRS([../m4 ../.. ../../config])
-
-dnl The sim shouldn't be checking $target and changing behavior. But it is,
-dnl and until we clean that up, we need to expand --target for use below.
-AC_CANONICAL_SYSTEM
-
-# Select the bitsize of the target.
-riscv_addr_bitsize=
-case "${target}" in
-riscv32*) riscv_addr_bitsize=32 ;;
-riscv*) riscv_addr_bitsize=64 ;;
-esac
-SIM_AC_OPTION_BITSIZE($riscv_addr_bitsize)
-
-SIM_AC_OUTPUT
--
2.38.1
next reply other threads:[~2022-11-07 16:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-07 16:24 Mike Frysinger [this message]
2022-11-07 16:24 ` [PATCH 2/5] sim: bpf: " Mike Frysinger
2022-11-07 16:24 ` [PATCH 3/5] sim: or1k: " Mike Frysinger
2022-11-07 16:24 ` [PATCH 4/5] sim: mn10300: " Mike Frysinger
2022-11-07 16:24 ` [PATCH 5/5] sim: v850: " Mike Frysinger
2022-11-07 16:45 ` [PATCH] sim: riscv: add missing AC_MSG_RESULT call Mike Frysinger
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