From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH] sim: riscv: add missing AC_MSG_RESULT call
Date: Mon, 7 Nov 2022 23:45:19 +0700 [thread overview]
Message-ID: <20221107164519.23146-1-vapier@gentoo.org> (raw)
In-Reply-To: <20221107162426.26097-1-vapier@gentoo.org>
Previous commit in here forgot to include this.
---
sim/configure | 2 ++
sim/riscv/acinclude.m4 | 1 +
2 files changed, 3 insertions(+)
diff --git a/sim/riscv/acinclude.m4 b/sim/riscv/acinclude.m4
index 29dcaebc61d6..0a421f4d4d53 100644
--- a/sim/riscv/acinclude.m4
+++ b/sim/riscv/acinclude.m4
@@ -18,4 +18,5 @@ AC_MSG_CHECKING([riscv bitsize])
SIM_RISCV_BITSIZE=64
AS_CASE([$target],
[riscv32*], [SIM_RISCV_BITSIZE=32])
+AC_MSG_RESULT([$SIM_RISCV_BITSIZE])
AC_SUBST(SIM_RISCV_BITSIZE)
--
2.38.1
prev parent reply other threads:[~2022-11-07 16:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-07 16:24 [PATCH 1/5] sim: riscv: drop subdir configure logic Mike Frysinger
2022-11-07 16:24 ` [PATCH 2/5] sim: bpf: " Mike Frysinger
2022-11-07 16:24 ` [PATCH 3/5] sim: or1k: " Mike Frysinger
2022-11-07 16:24 ` [PATCH 4/5] sim: mn10300: " Mike Frysinger
2022-11-07 16:24 ` [PATCH 5/5] sim: v850: " Mike Frysinger
2022-11-07 16:45 ` Mike Frysinger [this message]
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