[PATCH 1/9] sim: cpu: fix SMP msg prefix helper

[PATCH 1/9] sim: cpu: fix SMP msg prefix helper

[Mike Frysinger]

This code fails to compile when SMP is enabled due to some obvious
errors.  Fix those and change the logic to avoid CPP to prevent any
future rot from creeping back in.
---
 sim/common/sim-utils.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/sim/common/sim-utils.c b/sim/common/sim-utils.c
index 259b14cce295..d4a624c3b6ff 100644
--- a/sim/common/sim-utils.c
+++ b/sim/common/sim-utils.c
@@ -123,14 +123,17 @@ sim_cpu_lookup (SIM_DESC sd, const char *cpu_name)
 const char *
 sim_cpu_msg_prefix (sim_cpu *cpu)
 {
-#if MAX_NR_PROCESSORS == 1
-  return "";
-#else
   static char *prefix;
 
+  if (MAX_NR_PROCESSORS == 1)
+    return "";
+
   if (prefix == NULL)
     {
+      SIM_DESC sd = CPU_STATE (cpu);
       int maxlen = 0;
+      int i;
+
       for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 	{
 	  int len = strlen (CPU_NAME (STATE_CPU (sd, i)));
@@ -140,8 +143,8 @@ sim_cpu_msg_prefix (sim_cpu *cpu)
       prefix = (char *) xmalloc (maxlen + 5);
     }
   sprintf (prefix, "%s: ", CPU_NAME (cpu));
+
   return prefix;
-#endif
 }
 
 /* Cover fn to sim_io_eprintf.  */
-- 
2.39.0

[PATCH 2/9] sim: mn10300: fix SMP compile

[Mike Frysinger]

The igen tool sets up the SD define for code fragments to use, but
mn10300 was expecting "sd".  Change all the igen related code to use
SD so it actually compiles.
---
 sim/mn10300/am33.igen     |  8 ++++----
 sim/mn10300/mn10300-sim.h |  4 ++--
 sim/mn10300/mn10300.igen  | 24 ++++++++++++------------
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen
index 964f07521a8c..da8f88fa599f 100644
--- a/sim/mn10300/am33.igen
+++ b/sim/mn10300/am33.igen
@@ -256,8 +256,8 @@
       usp += 4;
     }
 
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
-      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+  if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x1)
@@ -307,8 +307,8 @@
   PC = cia;
   mask = REGS;
 
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
-      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+  if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x4)
diff --git a/sim/mn10300/mn10300-sim.h b/sim/mn10300/mn10300-sim.h
index f6e4d854a144..3eadc0fe1780 100644
--- a/sim/mn10300/mn10300-sim.h
+++ b/sim/mn10300/mn10300-sim.h
@@ -182,10 +182,10 @@ dw2u64 (dword data)
 /* Bring data in from the cold */
 
 #define IMEM8(EA) \
-(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA)))
+(sim_core_read_aligned_1(STATE_CPU (SD, 0), EA, exec_map, (EA)))
 
 #define IMEM8_IMMED(EA, N) \
-(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA) + (N)))
+(sim_core_read_aligned_1(STATE_CPU (SD, 0), EA, exec_map, (EA) + (N)))
 
 /* Function declarations.  */
 
diff --git a/sim/mn10300/mn10300.igen b/sim/mn10300/mn10300.igen
index 6330d6f0090a..42c0ead205d2 100644
--- a/sim/mn10300/mn10300.igen
+++ b/sim/mn10300/mn10300.igen
@@ -4024,8 +4024,8 @@
       sp += 4;
     }
 
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
-      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+  if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x1)
@@ -4080,8 +4080,8 @@
   PC = cia;
   mask = REGS;
 
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
-      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+  if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x4)
@@ -4183,8 +4183,8 @@
 
   mask = REGS;
 
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
-      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+  if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x4)
@@ -4293,8 +4293,8 @@
 
   mask = REGS;
 
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
-      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+  if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33_2
       )
     {
       if (mask & 0x4)
@@ -4401,8 +4401,8 @@
   offset = -4;
   mask = REGS;
 
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
-      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+  if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33_2
       )
     {
 
@@ -4507,8 +4507,8 @@
   offset = -4;
   mask = REGS;
 
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
-      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+  if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (SD)->mach == bfd_mach_am33_2
       )
     {
 
-- 
2.39.0

[PATCH 3/9] sim: or1k: fix iterator typo when setting up cpus

[Mike Frysinger]

This code loops over available cpus with "c", but then looks up the
cpu with "i".  Fix the typo so the code works correctly with smp.
---
 sim/or1k/sim-if.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sim/or1k/sim-if.c b/sim/or1k/sim-if.c
index d698d7035bf7..799812bb741e 100644
--- a/sim/or1k/sim-if.c
+++ b/sim/or1k/sim-if.c
@@ -244,7 +244,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
   }
 
   /* Do some final OpenRISC sim specific initializations.  */
-  for (c = 0; c < MAX_NR_PROCESSORS; ++c)
+  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
     {
       SIM_CPU *cpu = STATE_CPU (sd, i);
       /* Only needed for profiling, but the structure member is small.  */
-- 
2.39.0

[PATCH 4/9] sim: v850: fix SMP compile

[Mike Frysinger]

The igen tool sets up the SD & CPU defines for code fragments to use,
but v850 was expecting "sd".  Change all the igen related code to use
SD so it actually compiles, and fix a few places to use "CPU" instead
of hardcoding cpu0.
---
 sim/v850/simops.c   |   3 +
 sim/v850/v850-sim.h |   8 +--
 sim/v850/v850.igen  | 154 ++++++++++++++++++++++----------------------
 3 files changed, 84 insertions(+), 81 deletions(-)

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 5783f8606b30..69db8aaaa53d 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -48,6 +48,9 @@ int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
 #define SIZE_VALUES 11
 #endif
 
+/* TODO: This file largely assumes a single CPU.  */
+#define CPU STATE_CPU (sd, 0)
+
 
 uint32_t   trace_values[3];
 int          trace_num_values;
diff --git a/sim/v850/v850-sim.h b/sim/v850/v850-sim.h
index 35032306235f..6bd5fcfcc5c6 100644
--- a/sim/v850/v850-sim.h
+++ b/sim/v850/v850-sim.h
@@ -91,9 +91,9 @@ nia = PC
 #define GR  (V850_SIM_CPU (CPU)->reg.regs)
 #define SR  (V850_SIM_CPU (CPU)->reg.sregs)
 #define VR  (V850_SIM_CPU (CPU)->reg.vregs)
-#define MPU0_SR  (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu0_sregs)
-#define MPU1_SR  (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu1_sregs)
-#define FPU_SR   (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.fpu_sregs)
+#define MPU0_SR  (V850_SIM_CPU (CPU)->reg.mpu0_sregs)
+#define MPU1_SR  (V850_SIM_CPU (CPU)->reg.mpu1_sregs)
+#define FPU_SR   (V850_SIM_CPU (CPU)->reg.fpu_sregs)
 
 /* old */
 #define State    (V850_SIM_CPU (STATE_CPU (simulator, 0))->reg)
@@ -379,7 +379,7 @@ enum FPU_COMPARE {
 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
 
 #define IMEM16_IMMED(EA,N) \
-sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
+sim_core_read_aligned_2 (STATE_CPU (SD, 0), \
 			 PC, exec_map, (EA) + (N) * 2)
 
 #define load_mem(ADDR,LEN) \
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index 6bfabc08ea0a..bd8de8e2790d 100644
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -304,10 +304,10 @@ rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi
 
   addr = GR[reg1];
 
-  if (mpu_load_mem_test(sd, addr, 4, reg1) 
-      && mpu_store_mem_test(sd, addr, 4, reg1))
+  if (mpu_load_mem_test (SD, addr, 4, reg1)
+      && mpu_store_mem_test (SD, addr, 4, reg1))
     {
-      token = load_data_mem (sd, addr, 4);
+      token = load_data_mem (SD, addr, 4);
 
       TRACE_ALU_INPUT2 (token, GR[reg2]);
 
@@ -321,12 +321,12 @@ rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi
 
       if (result == 0)
 	{
-	  store_data_mem (sd, addr, 4, GR[reg3]);
+	  store_data_mem (SD, addr, 4, GR[reg3]);
 	  GR[reg3] = token;
 	}
       else
 	{
-	  store_data_mem (sd, addr, 4, token);
+	  store_data_mem (SD, addr, 4, token);
 	  GR[reg3] = token;
 	}
   
@@ -584,7 +584,7 @@ rrrrr,111111,RRRRR + wwwww,01011111100:XI:::divq
 
   divide_by   = GR[reg1];
   divide_this = GR[reg2];
-  v850_div (sd, divide_by, divide_this, &quotient, &remainder);
+  v850_div (SD, divide_by, divide_this, &quotient, &remainder);
   GR[reg2] = quotient;
   GR[reg3] = remainder;
 
@@ -608,7 +608,7 @@ rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu
   
   divide_by   = GR[reg1];
   divide_this = GR[reg2];
-  v850_divu (sd, divide_by, divide_this, &quotient, &remainder);
+  v850_divu (SD, divide_by, divide_this, &quotient, &remainder);
   GR[reg2] = quotient;
   GR[reg3] = remainder;
 
@@ -845,7 +845,7 @@ rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 *v850e3v5
 {
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = EXTEND8 (load_data_mem (sd, addr, 1));
+  uint32_t result = EXTEND8 (load_data_mem (SD, addr, 1));
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -862,7 +862,7 @@ rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 "ld.h <disp23>[r<reg1>], r<reg3>"
 {
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = EXTEND16 (load_data_mem (sd, addr, 2));
+  uint32_t result = EXTEND16 (load_data_mem (SD, addr, 2));
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -879,7 +879,7 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 "ld.w <disp23>[r<reg1>], r<reg3>"
 {
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = load_data_mem (sd, addr, 4);
+  uint32_t result = load_data_mem (SD, addr, 4);
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -889,10 +889,10 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 "ld.dw <disp23>[r<reg1>], r<reg3>"
 {
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = load_data_mem (sd, addr, 4);
+  uint32_t result = load_data_mem (SD, addr, 4);
   GR[reg3] = result;
   TRACE_LD (addr, result);
-  result = load_data_mem (sd, addr + 4, 4);
+  result = load_data_mem (SD, addr + 4, 4);
   GR[reg3 + 1] = result;
   TRACE_LD (addr + 4, result);
 }
@@ -914,7 +914,7 @@ rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 "ld.bu <disp23>[r<reg1>], r<reg3>"
 { 
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = load_data_mem (sd, addr, 1);
+  uint32_t result = load_data_mem (SD, addr, 1);
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -936,7 +936,7 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 "ld.hu <disp23>[r<reg1>], r<reg3>"
 {
   uint32_t addr = GR[reg1] + disp23;
-  uint32_t result = load_data_mem (sd, addr, 2);
+  uint32_t result = load_data_mem (SD, addr, 2);
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -1529,7 +1529,7 @@ rrrrr,111111,RRRRR + wwwww,00010100010:XI:::sar
 "sar r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_sar(sd, GR[reg1], GR[reg2], &GR[reg3]); 
+  v850_sar (SD, GR[reg1], GR[reg2], &GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -1568,7 +1568,7 @@ rrrrr,111111,RRRRR + wwwww,01110111010:XI:::satadd
 "satadd r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_satadd (sd, GR[reg1], GR[reg2], &GR[reg3]);
+  v850_satadd (SD, GR[reg1], GR[reg2], &GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -1588,7 +1588,7 @@ rrrrr,111111,RRRRR + wwwww,01110011010:XI:::satsub
 "satsub r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_satsub (sd, GR[reg1], GR[reg2], &GR[reg3]);
+  v850_satsub (SD, GR[reg1], GR[reg2], &GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -1829,7 +1829,7 @@ rrrrr,111111,RRRRR + wwwww,00011000010:XI:::shl
 "shl r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_shl(sd, GR[reg1], GR[reg2], &GR[reg3]);
+  v850_shl (SD, GR[reg1], GR[reg2], &GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -1841,7 +1841,7 @@ rrrrr,111111,RRRRR + wwwww,00010000010:XI:::shr
 "shr r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_shr(sd, GR[reg1], GR[reg2], &GR[reg3]);
+  v850_shr (SD, GR[reg1], GR[reg2], &GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -2036,7 +2036,7 @@ rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
 "st.b r<reg3>, <disp23>[r<reg1>]"
 {
   uint32_t addr = GR[reg1] + disp23;
-  store_data_mem (sd, addr, 1, GR[reg3]);
+  store_data_mem (SD, addr, 1, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
 }
 
@@ -2052,7 +2052,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
 "st.h r<reg3>, <disp23>[r<reg1>]"
 {
   uint32_t addr = GR[reg1] + disp23;
-  store_data_mem (sd, addr, 2, GR[reg3]);
+  store_data_mem (SD, addr, 2, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
 }
 
@@ -2068,7 +2068,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 "st.w r<reg3>, <disp23>[r<reg1>]"
 {
   uint32_t addr = GR[reg1] + disp23;
-  store_data_mem (sd, addr, 4, GR[reg3]);
+  store_data_mem (SD, addr, 4, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
 }
 
@@ -2077,9 +2077,9 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 "st.dw r<reg3>, <disp23>[r<reg1>]"
 {
   uint32_t addr = GR[reg1] + disp23;
-  store_data_mem (sd, addr, 4, GR[reg3]);
+  store_data_mem (SD, addr, 4, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
-  store_data_mem (sd, addr + 4, 4, GR[reg3 + 1]);
+  store_data_mem (SD, addr + 4, 4, GR[reg3 + 1]);
   TRACE_ST (addr + 4, GR[reg3 + 1]);
 }
 
@@ -2376,7 +2376,7 @@ rrrr,011111100000 + wwww,010001011000:F_I:::absf_d
   TRACE_FP_INPUT_FPU1 (&wop);
 
   status = sim_fpu_abs (&ans, &wop);
-  check_invalid_snan(sd, status, 1);
+  check_invalid_snan (SD, status, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
 
@@ -2396,7 +2396,7 @@ rrrrr,11111100000 + wwwww,10001001000:F_I:::absf_s
   TRACE_FP_INPUT_FPU1 (&wop);
 
   status = sim_fpu_abs (&ans, &wop);
-  check_invalid_snan(sd, status, 0);
+  check_invalid_snan (SD, status, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2418,7 +2418,7 @@ rrrr,0111111,RRRR,0 + wwww,010001110000:F_I:::addf_d
   status = sim_fpu_add (&ans, &wop1, &wop2);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2440,7 +2440,7 @@ rrrrr,111111,RRRRR + wwwww,10001100000:F_I:::addf_s
   status = sim_fpu_add (&ans, &wop1, &wop2);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2520,7 +2520,7 @@ rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d
   sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
   TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
 
-  result = v850_float_compare(sd, FFFF, wop2, wop1, 1);
+  result = v850_float_compare (SD, FFFF, wop2, wop1, 1);
 
   if (result)  
     SET_FPCC(bbb);
@@ -2545,7 +2545,7 @@ rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s
   sim_fpu_32to( &wop2, GR[reg2] );
   TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
 
-  result = v850_float_compare(sd, FFFF, wop2, wop1, 0);
+  result = v850_float_compare (SD, FFFF, wop2, wop1, 0);
 
   if (result)  
     SET_FPCC(bbb);
@@ -2571,7 +2571,7 @@ rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl
   status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
   status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND());
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3e] = ans;
   GR[reg3e+1] = ans>>32L;
@@ -2592,7 +2592,7 @@ rrrr,011111100011 + wwwww,10001010010:F_I:::cvtf_ds
 
   status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  check_cvt_fi(sd, status, 0);
+  check_cvt_fi (SD, status, 0);
 
   sim_fpu_to32 (&GR[reg3], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2614,7 +2614,7 @@ rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw
   status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
   status |= sim_fpu_to32i (&ans, &wop, FPSR_GET_ROUND());
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -2636,7 +2636,7 @@ rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld
   sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
   status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
 
-  check_cvt_if(sd, status, 1);
+  check_cvt_if (SD, status, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2658,7 +2658,7 @@ rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls
   sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
   status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
 
-  check_cvt_if(sd, status, 0);
+  check_cvt_if (SD, status, 0);
 
   sim_fpu_to32 (&GR[reg3], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2677,7 +2677,7 @@ rrrrr,11111100010 + wwww,010001010010:F_I:::cvtf_sd
   TRACE_FP_INPUT_FPU1 (&wop);
   status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  check_cvt_ff(sd, status, 1);
+  check_cvt_ff (SD, status, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2699,7 +2699,7 @@ rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl
   status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
   status |= sim_fpu_to64i (&ans, &wop, FPSR_GET_ROUND());
 
-  check_cvt_fi(sd, status, 0);
+  check_cvt_fi (SD, status, 0);
 
   GR[reg3e] = ans;
   GR[reg3e+1] = ans >> 32L;
@@ -2722,7 +2722,7 @@ rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw
   status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
   status |= sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 0);
+  check_cvt_fi (SD, status, 0);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -2741,7 +2741,7 @@ rrrrr,11111100000 + wwww,010001010010:F_I:::cvtf_wd
   sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND());
   status = sim_fpu_round_64 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
 
-  check_cvt_if(sd, status, 1);
+  check_cvt_if (SD, status, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2760,7 +2760,7 @@ rrrrr,11111100000 + wwwww,10001000010:F_I:::cvtf_ws
   sim_fpu_i32to (&wop, GR[reg2], FPSR_GET_ROUND());
   status = sim_fpu_round_32 (&wop, FPSR_GET_ROUND(), sim_fpu_denorm_zero);
 
-  check_cvt_if(sd, status, 0);
+  check_cvt_if (SD, status, 0);
 
   sim_fpu_to32 (&GR[reg3], &wop);
   TRACE_FP_RESULT_FPU1 (&wop);
@@ -2782,7 +2782,7 @@ rrrr,0111111,RRRR,0 + wwww,010001111110:F_I:::divf_d
   status = sim_fpu_div (&ans, &wop2, &wop1);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2804,7 +2804,7 @@ rrrrr,111111,RRRRR + wwwww,10001101110:F_I:::divf_s
   status = sim_fpu_div (&ans, &wop2, &wop1);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2828,7 +2828,7 @@ rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW,0:F_I:::maddf_s
   status |= sim_fpu_add (&ans, &wop1, &wop3);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg4], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2852,7 +2852,7 @@ rrrrr,111111,RRRRR + wwwww,10011100000:F_I:::fmaf_s
   status |= sim_fpu_add (&ans, &wop1, &wop3);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -2874,7 +2874,7 @@ rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d
     {
       if (FPSR & FPSR_XEV)
 	{
-	  SignalExceptionFPE(sd, 1);
+	  SignalExceptionFPE (SD, 1);
 	}
       else
 	{
@@ -2912,7 +2912,7 @@ rrrrr,111111,RRRRR + wwwww,10001101000:F_I:::maxf_s
     {
       if (FPSR & FPSR_XEV)
 	{
-	  SignalExceptionFPE(sd, 0);
+	  SignalExceptionFPE (SD, 0);
 	}
       else
 	{
@@ -2950,7 +2950,7 @@ rrrr,0111111,RRRR,0 + wwww,010001111010:F_I:::minf_d
     {
       if (FPSR & FPSR_XEV)
 	{
-	  SignalExceptionFPE(sd, 1);
+	  SignalExceptionFPE (SD, 1);
 	}
       else
 	{
@@ -2988,7 +2988,7 @@ rrrrr,111111,RRRRR + wwwww,10001101010:F_I:::minf_s
     {
       if (FPSR & FPSR_XEV)
 	{
-	  SignalExceptionFPE(sd, 0);
+	  SignalExceptionFPE (SD, 0);
 	}
       else
 	{
@@ -3029,7 +3029,7 @@ rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW,0:F_I:::msubf_s
   status |= sim_fpu_sub (&ans, &wop1, &wop3);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg4], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3054,7 +3054,7 @@ rrrrr,111111,RRRRR + wwwww,10011100010:F_I:::fmsf_s
   status |= sim_fpu_sub (&ans, &wop1, &wop3);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3076,7 +3076,7 @@ rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d
   status = sim_fpu_mul (&ans, &wop1, &wop2);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3098,7 +3098,7 @@ rrrrr,111111,RRRRR + wwwww,10001100100:F_I:::mulf_s
   status = sim_fpu_mul (&ans, &wop1, &wop2);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3118,7 +3118,7 @@ rrrr,011111100001 + wwww,010001011000:F_I:::negf_d
 
   status = sim_fpu_neg (&ans, &wop);
 
-  check_invalid_snan(sd, status, 1);
+  check_invalid_snan (SD, status, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3138,7 +3138,7 @@ rrrrr,11111100001 + wwwww,10001001000:F_I:::negf_s
 
   status = sim_fpu_neg (&ans, &wop);
 
-  check_invalid_snan(sd, status, 0);
+  check_invalid_snan (SD, status, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3164,7 +3164,7 @@ rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW,0:F_I:::nmaddf_s
   wop1 = ans;
   status |= sim_fpu_neg (&ans, &wop1);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg4], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3190,7 +3190,7 @@ rrrrr,111111,RRRRR + wwwww,10011100100:F_I:::fnmaf_s
   wop1 = ans;
   status |= sim_fpu_neg (&ans, &wop1);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3217,7 +3217,7 @@ rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s
   wop1 = ans;
   status |= sim_fpu_neg (&ans, &wop1);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg4], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3244,7 +3244,7 @@ rrrrr,111111,RRRRR + wwwww,10011100110:F_I:::fnmsf_s
   wop1 = ans;
   status |= sim_fpu_neg (&ans, &wop1);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3265,7 +3265,7 @@ rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d
   status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3286,7 +3286,7 @@ rrrrr,11111100001 + wwwww,10001001110:F_I:::recipf.s
   status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3310,7 +3310,7 @@ rrrr,011111100010 + wwww,010001011110:F_I:::rsqrtf.d
   status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3334,7 +3334,7 @@ rrrrr,11111100010 + wwwww,10001001110:F_I:::rsqrtf.s
   status = sim_fpu_div (&ans, &sim_fpu_one, &wop);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEZ | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3355,7 +3355,7 @@ rrrr,011111100000 + wwww,010001011110:F_I:::sqrtf.d
   status = sim_fpu_sqrt (&ans, &wop);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3376,7 +3376,7 @@ rrrrr,11111100000 + wwwww,10001001110:F_I:::sqrtf.s
   status = sim_fpu_sqrt (&ans, &wop);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3398,7 +3398,7 @@ rrrr,0111111,RRRR,0 + wwww,010001110010:F_I:::subf.d
   status = sim_fpu_sub (&ans, &wop2, &wop1);
   status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 1);
 
   sim_fpu_to232 (&GR[reg3e+1], &GR[reg3e], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3420,7 +3420,7 @@ rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s
   status = sim_fpu_sub (&ans, &wop2, &wop1);
   status |= sim_fpu_round_32 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
 
-  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+  update_fpsr (SD, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
 
   sim_fpu_to32 (&GR[reg3], &ans);
   TRACE_FP_RESULT_FPU1 (&ans);
@@ -3458,7 +3458,7 @@ rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl
 
   status = sim_fpu_to64i (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3e] = ans;
   GR[reg3e+1] = ans>>32L;
@@ -3480,7 +3480,7 @@ rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul
 
   status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3e] = ans;
   GR[reg3e+1] = ans>>32L;
@@ -3502,7 +3502,7 @@ rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
 
   status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -3523,7 +3523,7 @@ rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw
 
   status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 1);
+  check_cvt_fi (SD, status, 1);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -3584,7 +3584,7 @@ rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
 
   status = sim_fpu_to32i (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 0);
+  check_cvt_fi (SD, status, 0);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -3605,7 +3605,7 @@ rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw
 
   status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
 
-  check_cvt_fi(sd, status, 0);
+  check_cvt_fi (SD, status, 0);
 
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
@@ -3617,7 +3617,7 @@ rrrrr,111111,iiiii+wwwww,00011000100:VII:::rotl_imm
 "rotl imm5, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT1 (GR[reg2]);
-  v850_rotl (sd, imm5, GR[reg2], & GR[reg3]);
+  v850_rotl (SD, imm5, GR[reg2], & GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -3626,7 +3626,7 @@ rrrrr,111111,RRRRR+wwwww,00011000110:VII:::rotl
 "rotl r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
-  v850_rotl (sd, GR[reg1], GR[reg2], & GR[reg3]);
+  v850_rotl (SD, GR[reg1], GR[reg2], & GR[reg3]);
   TRACE_ALU_RESULT1 (GR[reg3]);
 }
 
@@ -3636,7 +3636,7 @@ rrrrr,111111,RRRRR+bbbb,B,0001001,BBB,0:IX:::bins_top
 "bins r<reg1>, <bit13> + 16, <bit4> - <bit13> + 17, r<reg2>"
 {
   TRACE_ALU_INPUT1 (GR[reg1]);
-  v850_bins (sd, GR[reg1], bit13 + 16, bit4 + 16, & GR[reg2]);
+  v850_bins (SD, GR[reg1], bit13 + 16, bit4 + 16, & GR[reg2]);
   TRACE_ALU_RESULT1 (GR[reg2]);
 }
 
@@ -3645,7 +3645,7 @@ rrrrr,111111,RRRRR+bbbb,B,0001011,BBB,0:IX:::bins_middle
 "bins r<reg1>, <bit13>, <bit4> - <bit13> + 17, r<reg2>"
 {
   TRACE_ALU_INPUT1 (GR[reg1]);
-  v850_bins (sd, GR[reg1], bit13, bit4 + 16, & GR[reg2]);
+  v850_bins (SD, GR[reg1], bit13, bit4 + 16, & GR[reg2]);
   TRACE_ALU_RESULT1 (GR[reg2]);
 }
 
@@ -3654,7 +3654,7 @@ rrrrr,111111,RRRRR+bbbb,B,0001101,BBB,0:IX:::bins_bottom
 "bins r<reg1>, <bit13>, <bit4> - <bit13> + 1, r<reg2>"
 {
   TRACE_ALU_INPUT1 (GR[reg1]);
-  v850_bins (sd, GR[reg1], bit13, bit4, & GR[reg2]);
+  v850_bins (SD, GR[reg1], bit13, bit4, & GR[reg2]);
   TRACE_ALU_RESULT1 (GR[reg2]);
 }
 
-- 
2.39.0

[PATCH 5/9] sim: m32r: fix iterator typo when setting up cpus

[Mike Frysinger]

This code loops over available cpus with "c", but then looks up the
cpu with "i".  Fix the typo so the code works correctly with smp.
---
 sim/m32r/sim-if.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c
index c8c04b38b68a..7fe6b42801e7 100644
--- a/sim/m32r/sim-if.c
+++ b/sim/m32r/sim-if.c
@@ -134,7 +134,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
     m32r_cgen_init_dis (cd);
   }
 
-  for (c = 0; c < MAX_NR_PROCESSORS; ++c)
+  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
     {
       /* Only needed for profiling, but the structure member is small.  */
       memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0,
-- 
2.39.0

[PATCH 6/9] sim: msp430: add basic SMP cpu init

[Mike Frysinger]

There's no need to assert there's only 1 CPU when setting them all
up here is trivial.
---
 sim/msp430/msp430-sim.c | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/sim/msp430/msp430-sim.c b/sim/msp430/msp430-sim.c
index d402be77eb40..e7b58bab1347 100644
--- a/sim/msp430/msp430-sim.c
+++ b/sim/msp430/msp430-sim.c
@@ -116,6 +116,7 @@ sim_open (SIM_OPEN_KIND kind,
   SIM_DESC sd = sim_state_alloc (kind, callback);
   struct msp430_cpu_state *msp430_cpu;
   char c;
+  int i;
 
   /* Initialise the simulator.  */
 
@@ -141,11 +142,6 @@ sim_open (SIM_OPEN_KIND kind,
       return 0;
     }
 
-  CPU_PC_FETCH (STATE_CPU (sd, 0)) = msp430_pc_fetch;
-  CPU_PC_STORE (STATE_CPU (sd, 0)) = msp430_pc_store;
-  CPU_REG_FETCH (STATE_CPU (sd, 0)) = msp430_reg_fetch;
-  CPU_REG_STORE (STATE_CPU (sd, 0)) = msp430_reg_store;
-
   /* Allocate memory if none specified by user.
      Note - these values match the memory regions in the libgloss/msp430/msp430[xl]-sim.ld scripts.  */
   if (sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, &c, 0x2, 1) == 0)
@@ -180,13 +176,21 @@ sim_open (SIM_OPEN_KIND kind,
     }
 
   /* CPU specific initialization.  */
-  assert (MAX_NR_PROCESSORS == 1);
-
-  msp430_cpu = MSP430_SIM_CPU (STATE_CPU (sd, 0));
-  msp430_cpu->cio_breakpoint = trace_sym_value (sd, "C$$IO$$");
-  msp430_cpu->cio_buffer = trace_sym_value (sd, "__CIOBUF__");
-  if (msp430_cpu->cio_buffer == -1)
-    msp430_cpu->cio_buffer = trace_sym_value (sd, "_CIOBUF_");
+  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+    {
+      SIM_CPU *cpu = STATE_CPU (sd, i);
+
+      CPU_PC_FETCH (cpu) = msp430_pc_fetch;
+      CPU_PC_STORE (cpu) = msp430_pc_store;
+      CPU_REG_FETCH (cpu) = msp430_reg_fetch;
+      CPU_REG_STORE (cpu) = msp430_reg_store;
+
+      msp430_cpu = MSP430_SIM_CPU (cpu);
+      msp430_cpu->cio_breakpoint = trace_sym_value (sd, "C$$IO$$");
+      msp430_cpu->cio_buffer = trace_sym_value (sd, "__CIOBUF__");
+      if (msp430_cpu->cio_buffer == -1)
+	msp430_cpu->cio_buffer = trace_sym_value (sd, "_CIOBUF_");
+    }
 
   return sd;
 }
-- 
2.39.0

[PATCH 7/9] sim: cpu: change default init to handle all cpus

[Mike Frysinger]

All the runtimes were only initializing a single CPU.  When SMP is
enabled, things quickly crash as none of the other CPU structs are
setup.  Change the default from 0 to the compile time value.
---
 sim/aarch64/interp.c         | 2 +-
 sim/arm/wrapper.c            | 2 +-
 sim/avr/interp.c             | 2 +-
 sim/bfin/interp.c            | 2 +-
 sim/bpf/sim-if.c             | 2 +-
 sim/common/sim-cpu.c         | 5 +++++
 sim/cr16/interp.c            | 2 +-
 sim/cris/sim-if.c            | 2 +-
 sim/d10v/interp.c            | 2 +-
 sim/example-synacor/interp.c | 2 +-
 sim/frv/sim-if.c             | 2 +-
 sim/ft32/interp.c            | 2 +-
 sim/h8300/compile.c          | 2 +-
 sim/iq2000/sim-if.c          | 2 +-
 sim/lm32/sim-if.c            | 2 +-
 sim/m32r/sim-if.c            | 2 +-
 sim/m68hc11/interp.c         | 2 +-
 sim/mcore/interp.c           | 2 +-
 sim/microblaze/interp.c      | 2 +-
 sim/mips/interp.c            | 2 +-
 sim/mn10300/interp.c         | 2 +-
 sim/moxie/interp.c           | 2 +-
 sim/msp430/msp430-sim.c      | 2 +-
 sim/or1k/sim-if.c            | 2 +-
 sim/pru/interp.c             | 2 +-
 sim/riscv/interp.c           | 2 +-
 sim/sh/interp.c              | 2 +-
 sim/v850/interp.c            | 2 +-
 28 files changed, 32 insertions(+), 27 deletions(-)

diff --git a/sim/aarch64/interp.c b/sim/aarch64/interp.c
index 234d978a7685..03efb42e6b5e 100644
--- a/sim/aarch64/interp.c
+++ b/sim/aarch64/interp.c
@@ -348,7 +348,7 @@ sim_open (SIM_OPEN_KIND                  kind,
   current_alignment = NONSTRICT_ALIGNMENT;
 
   /* Perform the initialization steps one by one.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct aarch64_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct aarch64_sim_cpu))
       != SIM_RC_OK
       || sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK
       || sim_parse_args (sd, argv) != SIM_RC_OK
diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c
index 5eb61df14378..4e8007804546 100644
--- a/sim/arm/wrapper.c
+++ b/sim/arm/wrapper.c
@@ -822,7 +822,7 @@ sim_open (SIM_OPEN_KIND kind,
   current_alignment = STRICT_ALIGNMENT;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+  if (sim_cpu_alloc_all (sd, 0) != SIM_RC_OK)
     {
       free_state (sd);
       return 0;
diff --git a/sim/avr/interp.c b/sim/avr/interp.c
index ddd9e1ff1eae..27834f15dbc3 100644
--- a/sim/avr/interp.c
+++ b/sim/avr/interp.c
@@ -1703,7 +1703,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
   current_target_byte_order = BFD_ENDIAN_LITTLE;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct avr_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct avr_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/bfin/interp.c b/sim/bfin/interp.c
index 04c1773eaf42..e904506bf228 100644
--- a/sim/bfin/interp.c
+++ b/sim/bfin/interp.c
@@ -675,7 +675,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
   current_target_byte_order = BFD_ENDIAN_LITTLE;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct bfin_cpu_state))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct bfin_cpu_state))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/bpf/sim-if.c b/sim/bpf/sim-if.c
index b29300f03287..4c9aa83232aa 100644
--- a/sim/bpf/sim-if.c
+++ b/sim/bpf/sim-if.c
@@ -132,7 +132,7 @@ sim_open (SIM_OPEN_KIND kind,
   STATE_MACHS (sd) = bpf_sim_machs;
   STATE_MODEL_NAME (sd) = "bpf-def";
 
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct bpf_sim_cpu)) != SIM_RC_OK)
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct bpf_sim_cpu)) != SIM_RC_OK)
     goto error;
 
   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
diff --git a/sim/common/sim-cpu.c b/sim/common/sim-cpu.c
index 024bd050ab3d..9f64d9d06e8d 100644
--- a/sim/common/sim-cpu.c
+++ b/sim/common/sim-cpu.c
@@ -35,8 +35,13 @@ sim_cpu_alloc_all_extra (SIM_DESC sd, int ncpus, size_t extra_bytes)
 {
   int c;
 
+  /* TODO: This should be a command line option for users to control.  */
+  if (ncpus == 0)
+    ncpus = MAX_NR_PROCESSORS;
+
   for (c = 0; c < ncpus; ++c)
     STATE_CPU (sd, c) = sim_cpu_alloc_extra (sd, extra_bytes);
+
   return SIM_RC_OK;
 }
 
diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c
index 1830e348a060..fe1e24bed68b 100644
--- a/sim/cr16/interp.c
+++ b/sim/cr16/interp.c
@@ -407,7 +407,7 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb,
   cb->syscall_map = cb_cr16_syscall_map;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+  if (sim_cpu_alloc_all (sd, 0) != SIM_RC_OK)
     {
       free_state (sd);
       return 0;
diff --git a/sim/cris/sim-if.c b/sim/cris/sim-if.c
index 47862edf4f5a..d939854e32d1 100644
--- a/sim/cris/sim-if.c
+++ b/sim/cris/sim-if.c
@@ -670,7 +670,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
   current_target_byte_order = BFD_ENDIAN_LITTLE;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct cris_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct cris_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c
index 9beedf8f445e..aebd98ab6ac6 100644
--- a/sim/d10v/interp.c
+++ b/sim/d10v/interp.c
@@ -765,7 +765,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
   cb->syscall_map = cb_d10v_syscall_map;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+  if (sim_cpu_alloc_all (sd, 0) != SIM_RC_OK)
     {
       free_state (sd);
       return 0;
diff --git a/sim/example-synacor/interp.c b/sim/example-synacor/interp.c
index 20ae057d43a1..25e519d9f2ab 100644
--- a/sim/example-synacor/interp.c
+++ b/sim/example-synacor/interp.c
@@ -90,7 +90,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
   current_target_byte_order = BFD_ENDIAN_LITTLE;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct example_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct example_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/frv/sim-if.c b/sim/frv/sim-if.c
index 6e0f1bbaba64..ad94423f40b6 100644
--- a/sim/frv/sim-if.c
+++ b/sim/frv/sim-if.c
@@ -65,7 +65,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, bfd *abfd,
   current_target_byte_order = BFD_ENDIAN_BIG;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct frv_sim_cpu)) != SIM_RC_OK)
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct frv_sim_cpu)) != SIM_RC_OK)
     {
       free_state (sd);
       return 0;
diff --git a/sim/ft32/interp.c b/sim/ft32/interp.c
index dfea4720c220..1eda9a7a2869 100644
--- a/sim/ft32/interp.c
+++ b/sim/ft32/interp.c
@@ -823,7 +823,7 @@ sim_open (SIM_OPEN_KIND kind,
   current_target_byte_order = BFD_ENDIAN_LITTLE;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct ft32_cpu_state))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct ft32_cpu_state))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index cc8b52c5d654..467eeafde610 100644
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -4631,7 +4631,7 @@ sim_open (SIM_OPEN_KIND kind,
   current_target_byte_order = BFD_ENDIAN_BIG;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct h8300_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct h8300_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/iq2000/sim-if.c b/sim/iq2000/sim-if.c
index e9b66b6a7ef9..e02a413103e2 100644
--- a/sim/iq2000/sim-if.c
+++ b/sim/iq2000/sim-if.c
@@ -70,7 +70,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
   current_target_byte_order = BFD_ENDIAN_BIG;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct iq2000_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct iq2000_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/lm32/sim-if.c b/sim/lm32/sim-if.c
index 82f2e117671e..b51028055124 100644
--- a/sim/lm32/sim-if.c
+++ b/sim/lm32/sim-if.c
@@ -101,7 +101,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
   current_target_byte_order = BFD_ENDIAN_BIG;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct lm32_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct lm32_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c
index 7fe6b42801e7..1305ea6d1021 100644
--- a/sim/m32r/sim-if.c
+++ b/sim/m32r/sim-if.c
@@ -68,7 +68,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
   current_target_byte_order = BFD_ENDIAN_BIG;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct m32r_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct m32r_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c
index b80f5cb82bb0..82155213330a 100644
--- a/sim/m68hc11/interp.c
+++ b/sim/m68hc11/interp.c
@@ -422,7 +422,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
   current_target_byte_order = BFD_ENDIAN_BIG;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct m68hc11_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct m68hc11_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c
index 84b243f07059..ae554c77d31c 100644
--- a/sim/mcore/interp.c
+++ b/sim/mcore/interp.c
@@ -1370,7 +1370,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
   cb->syscall_map = cb_mcore_syscall_map;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct mcore_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct mcore_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/microblaze/interp.c b/sim/microblaze/interp.c
index 8a8cb9f2b832..df7f41fcff56 100644
--- a/sim/microblaze/interp.c
+++ b/sim/microblaze/interp.c
@@ -410,7 +410,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct microblaze_regset))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct microblaze_regset))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index fa192d36f2e9..d44c474ae1d6 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -351,7 +351,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct mips_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct mips_sim_cpu))
       != SIM_RC_OK)
     return 0;
 
diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c
index 8467070addb6..2915551253f3 100644
--- a/sim/mn10300/interp.c
+++ b/sim/mn10300/interp.c
@@ -97,7 +97,7 @@ sim_open (SIM_OPEN_KIND kind,
   current_target_byte_order = BFD_ENDIAN_LITTLE;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+  if (sim_cpu_alloc_all (sd, 0) != SIM_RC_OK)
     return 0;
 
   /* for compatibility */
diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index 144d83cbe8e7..2bc241db6f56 100644
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -1202,7 +1202,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
   current_target_byte_order = BFD_ENDIAN_BIG;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct moxie_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct moxie_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/msp430/msp430-sim.c b/sim/msp430/msp430-sim.c
index e7b58bab1347..c02e7ca4b6f5 100644
--- a/sim/msp430/msp430-sim.c
+++ b/sim/msp430/msp430-sim.c
@@ -123,7 +123,7 @@ sim_open (SIM_OPEN_KIND kind,
   /* Set default options before parsing user options.  */
   current_target_byte_order = BFD_ENDIAN_LITTLE;
 
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct msp430_cpu_state))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct msp430_cpu_state))
       != SIM_RC_OK)
     {
       sim_state_free (sd);
diff --git a/sim/or1k/sim-if.c b/sim/or1k/sim-if.c
index 799812bb741e..3bbf4f05738f 100644
--- a/sim/or1k/sim-if.c
+++ b/sim/or1k/sim-if.c
@@ -168,7 +168,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
   current_target_byte_order = BFD_ENDIAN_BIG;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct or1k_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct or1k_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/pru/interp.c b/sim/pru/interp.c
index 250a32a889a5..0e1874c11805 100644
--- a/sim/pru/interp.c
+++ b/sim/pru/interp.c
@@ -774,7 +774,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
   current_target_byte_order = BFD_ENDIAN_LITTLE;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct pru_regset)) != SIM_RC_OK)
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct pru_regset)) != SIM_RC_OK)
     {
       free_state (sd);
       return 0;
diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index a49ad0476c45..601753e02916 100644
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -77,7 +77,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
   callback->syscall_map = cb_riscv_syscall_map;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct riscv_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct riscv_sim_cpu))
       != SIM_RC_OK)
     {
       free_state (sd);
diff --git a/sim/sh/interp.c b/sim/sh/interp.c
index b2d30e386c1a..5a90cd2cf74c 100644
--- a/sim/sh/interp.c
+++ b/sim/sh/interp.c
@@ -2350,7 +2350,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
   cb->syscall_map = cb_sh_syscall_map;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
+  if (sim_cpu_alloc_all (sd, 0) != SIM_RC_OK)
     {
       free_state (sd);
       return 0;
diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index efe35c606ffb..948b7245c3f0 100644
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -206,7 +206,7 @@ sim_open (SIM_OPEN_KIND    kind,
   cb->syscall_map = cb_v850_syscall_map;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct v850_sim_cpu))
+  if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct v850_sim_cpu))
       != SIM_RC_OK)
     return 0;
 
-- 
2.39.0

[PATCH 8/9] sim: smp: make option available again

[Mike Frysinger]

At some point we want this to work, but it's not easy to test if
the configure option isn't available.  Restore it, but keep the
default off.
---
 sim/Makefile.in             |  1 +
 sim/aclocal.m4              |  1 +
 sim/config.h.in             |  3 +++
 sim/configure               | 32 ++++++++++++++++++++++++++++++--
 sim/configure.ac            |  1 +
 sim/m4/sim_ac_option_smp.m4 | 18 ++++++++++++------
 6 files changed, 48 insertions(+), 8 deletions(-)

diff --git a/sim/configure.ac b/sim/configure.ac
index bfcd9e59d10e..af7e6e752ca1 100644
--- a/sim/configure.ac
+++ b/sim/configure.ac
@@ -180,6 +180,7 @@ SIM_AC_OPTION_INLINE
 SIM_AC_OPTION_PROFILE
 SIM_AC_OPTION_RESERVED_BITS
 SIM_AC_OPTION_SCACHE
+SIM_AC_OPTION_SMP
 SIM_AC_OPTION_STDIO
 SIM_AC_OPTION_TRACE
 SIM_AC_OPTION_WARNINGS
diff --git a/sim/m4/sim_ac_option_smp.m4 b/sim/m4/sim_ac_option_smp.m4
index b59d7e6e7600..5c2b35f9d846 100644
--- a/sim/m4/sim_ac_option_smp.m4
+++ b/sim/m4/sim_ac_option_smp.m4
@@ -12,20 +12,26 @@ dnl GNU General Public License for more details.
 dnl
 dnl You should have received a copy of the GNU General Public License
 dnl along with this program.  If not, see <http://www.gnu.org/licenses/>.
-AC_DEFUN([SIM_AC_OPTION_SMP],
-[
+AC_DEFUN([SIM_AC_OPTION_SMP], [dnl
 AC_MSG_CHECKING([number of sim cpus to support])
-default_sim_smp="ifelse([$1],,5,[$1])"
-sim_smp="$default_sim_smp""
+dnl TODO: We should increase the default to use smp at some point.  When we do,
+dnl the ppc/configure sim-smp option should be merged.  See the WITH_SMP check
+dnl below for more cleanups too.
+default_sim_smp="0"
+sim_smp="$default_sim_smp"
 AC_ARG_ENABLE(sim-smp,
 [AS_HELP_STRING([--enable-sim-smp=n],
-		[Specify number of processors to configure for (default ${default_sim_smp})])],
+		[Specify number of processors to configure for (default 1)])],
 [case "${enableval}" in
   yes)	sim_smp="5";;
   no)	sim_smp="0";;
   *)	sim_smp="$enableval";;
 esac])dnl
 sim_igen_smp="-N ${sim_smp}"
-AC_DEFINE_UNQUOTED([WITH_SMP], [$sim_smp], [Sim SMP settings])
+dnl NB: The ppc code uses a diff default because its smp works.  That is why
+dnl we don't unconditionally enable WITH_SMP here.  Once we unify ppc, we can
+dnl make this unconditional.
+AS_VAR_IF([sim_smp], [0], [], [dnl
+  AC_DEFINE_UNQUOTED([WITH_SMP], [$sim_smp], [Sim SMP settings])])
 AC_MSG_RESULT($sim_smp)
 ])
-- 
2.39.0

[PATCH 9/9] sim: smp: plumb igen flag down to all users

[Mike Frysinger]

While mips has respected sim_igen_smp at configure time (which was
always empty since it defaulted smp to off), no other igen port did.
Move this to a makefile variable and plumb it through the common
IGEN_RUN variable instead so everyone gets it by default.  We also
clean up some redundant -N0 setting with multirun mips.
---
 sim/Makefile.in             |  3 ++-
 sim/arch-subdir.mk.in       |  3 +++
 sim/common/Make-common.in   |  2 +-
 sim/configure               | 16 +++++++++-------
 sim/igen/local.mk           |  2 +-
 sim/m4/sim_ac_option_smp.m4 |  3 ++-
 sim/mips/Makefile.in        |  2 --
 sim/mips/acinclude.m4       |  8 ++++----
 8 files changed, 22 insertions(+), 17 deletions(-)

diff --git a/sim/arch-subdir.mk.in b/sim/arch-subdir.mk.in
index cfde3f3fb785..e6c779a20d57 100644
--- a/sim/arch-subdir.mk.in
+++ b/sim/arch-subdir.mk.in
@@ -73,3 +73,6 @@ SIM_INLINE = @SIM_INLINE@
 SIM_HW_CFLAGS = @SIM_HW_CFLAGS@
 SIM_HW_OBJS = $(SIM_HW_DEVICES:%=dv-%.o)
 @SIM_ENABLE_HW_FALSE@SIM_HW_OBJS =
+
+# TODO: Delete this once mips/Makefile.in igen moves to mips/local.mk.
+IGEN_FLAGS_SMP = @IGEN_FLAGS_SMP@
diff --git a/sim/common/Make-common.in b/sim/common/Make-common.in
index 52cc3c926f7f..7b1caa0781f1 100644
--- a/sim/common/Make-common.in
+++ b/sim/common/Make-common.in
@@ -82,7 +82,7 @@ POSTCOMPILE = @true
 # igen leaks memory, and therefore makes AddressSanitizer unhappy.  Disable
 # leak detection while running it.
 IGEN = ../igen/igen$(EXEEXT)
-IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(IGEN)
+IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(IGEN) $(IGEN_FLAGS_SMP)
 
 # Each simulator's Makefile.in defines one or more of these variables
 # to override our settings as necessary.  There is no need to define these
diff --git a/sim/igen/local.mk b/sim/igen/local.mk
index bf984db5edfc..5d552952b990 100644
--- a/sim/igen/local.mk
+++ b/sim/igen/local.mk
@@ -22,7 +22,7 @@
 # igen leaks memory, and therefore makes AddressSanitizer unhappy.  Disable
 # leak detection while running it.
 IGEN = %D%/igen$(EXEEXT)
-IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(IGEN)
+IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(IGEN) $(IGEN_FLAGS_SMP)
 
 ## This makes sure igen is available before building the arch-subdirs which
 ## need to run the igen tool.
diff --git a/sim/m4/sim_ac_option_smp.m4 b/sim/m4/sim_ac_option_smp.m4
index 5c2b35f9d846..47ddabd05f4a 100644
--- a/sim/m4/sim_ac_option_smp.m4
+++ b/sim/m4/sim_ac_option_smp.m4
@@ -27,7 +27,8 @@ AC_ARG_ENABLE(sim-smp,
   no)	sim_smp="0";;
   *)	sim_smp="$enableval";;
 esac])dnl
-sim_igen_smp="-N ${sim_smp}"
+IGEN_FLAGS_SMP="-N ${sim_smp}"
+AC_SUBST(IGEN_FLAGS_SMP)
 dnl NB: The ppc code uses a diff default because its smp works.  That is why
 dnl we don't unconditionally enable WITH_SMP here.  Once we unify ppc, we can
 dnl make this unconditional.
diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in
index c287a632ae73..8493f8780dc3 100644
--- a/sim/mips/Makefile.in
+++ b/sim/mips/Makefile.in
@@ -422,7 +422,6 @@ tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLUDE)
 		-I $(srcdir) \
 		-Werror \
 		-Wnodiscard \
-		-N 0 \
 		-M $${m} \
 		-G gen-direct-access \
 		-G gen-zero-r0 \
@@ -451,7 +450,6 @@ tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) $(IGEN) $(IGEN_INCLUDE)
 		-Werror \
 		-Wnodiscard \
 		-Wnowidth \
-		-N 0 \
 		$(SIM_MIPS_MULTI_FLAGS) \
 		-G gen-direct-access \
 		-G gen-zero-r0 \
diff --git a/sim/mips/acinclude.m4 b/sim/mips/acinclude.m4
index 0a8bf97ba854..ae5cc294a031 100644
--- a/sim/mips/acinclude.m4
+++ b/sim/mips/acinclude.m4
@@ -322,10 +322,10 @@ __EOF__
   dnl For clean-extra target.
   SIM_MIPS_MULTI_SRC=doesnt-exist.c
 ])
-SIM_MIPS_IGEN_FLAGS="-F ${sim_mips_igen_filter} ${sim_mips_igen_machine} ${sim_igen_smp}"
-SIM_MIPS_M16_FLAGS="-F ${sim_mips_m16_filter} ${sim_mips_m16_machine} ${sim_igen_smp}"
-SIM_MIPS_MICROMIPS16_FLAGS="-F ${sim_mips_micromips16_filter} ${sim_mips_micromips16_machine} ${sim_igen_smp}"
-SIM_MIPS_MICROMIPS_FLAGS="-F ${sim_mips_micromips_filter} ${sim_mips_micromips_machine} ${sim_igen_smp}"
+SIM_MIPS_IGEN_FLAGS="-F ${sim_mips_igen_filter} ${sim_mips_igen_machine}"
+SIM_MIPS_M16_FLAGS="-F ${sim_mips_m16_filter} ${sim_mips_m16_machine}"
+SIM_MIPS_MICROMIPS16_FLAGS="-F ${sim_mips_micromips16_filter} ${sim_mips_micromips16_machine}"
+SIM_MIPS_MICROMIPS_FLAGS="-F ${sim_mips_micromips_filter} ${sim_mips_micromips_machine}"
 AC_SUBST(SIM_MIPS_IGEN_FLAGS)
 AC_SUBST(SIM_MIPS_M16_FLAGS)
 AC_SUBST(SIM_MIPS_MICROMIPS_FLAGS)
-- 
2.39.0