From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 07/17] sim: frv: fix -Wunused-but-set-variable warnings
Date: Wed, 6 Dec 2023 20:59:27 -0700 [thread overview]
Message-ID: <20231207035937.14920-7-vapier@gentoo.org> (raw)
In-Reply-To: <20231207035937.14920-1-vapier@gentoo.org>
---
sim/frv/cache.c | 2 --
sim/frv/profile-fr400.c | 11 -----------
sim/frv/profile-fr500.c | 2 --
3 files changed, 15 deletions(-)
diff --git a/sim/frv/cache.c b/sim/frv/cache.c
index 76f762fe5ee7..b4f33f1252d5 100644
--- a/sim/frv/cache.c
+++ b/sim/frv/cache.c
@@ -362,7 +362,6 @@ read_data_from_memory (SIM_CPU *current_cpu, SI address, char *buffer,
static void
fill_line_from_memory (FRV_CACHE *cache, FRV_CACHE_TAG *tag, SI address)
{
- PCADDR pc;
int line_alignment;
SI read_address;
SIM_CPU *current_cpu = cache->cpu;
@@ -382,7 +381,6 @@ fill_line_from_memory (FRV_CACHE *cache, FRV_CACHE_TAG *tag, SI address)
tag->line = cache->data_storage + (line_index * cache->line_size);
}
- pc = CPU_PC_GET (current_cpu);
line_alignment = cache->line_size - 1;
read_address = address & ~line_alignment;
read_data_from_memory (current_cpu, read_address, tag->line,
diff --git a/sim/frv/profile-fr400.c b/sim/frv/profile-fr400.c
index 58ad8c86c4b1..31e25178a4d4 100644
--- a/sim/frv/profile-fr400.c
+++ b/sim/frv/profile-fr400.c
@@ -632,7 +632,6 @@ frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
{
int cycles;
FRV_PROFILE_STATE *ps;
- const CGEN_INSN *insn;
int busy_adjustment[] = {0, 0};
int *fr;
@@ -643,7 +642,6 @@ frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
cycles = idesc->timing->units[unit_num].done;
ps = CPU_PROFILE_STATE (cpu);
- insn = idesc->idata;
/* The latency of the registers may be less than previously recorded,
depending on how they were used previously.
@@ -1673,9 +1671,7 @@ frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
{
int cycles;
FRV_PROFILE_STATE *ps;
- const CGEN_INSN *insn;
int busy_adjustment[] = {0};
- int *fr;
if (model_insn == FRV_INSN_MODEL_PASS_1)
return 0;
@@ -1684,7 +1680,6 @@ frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
cycles = idesc->timing->units[unit_num].done;
ps = CPU_PROFILE_STATE (cpu);
- insn = idesc->idata;
/* The latency of the registers may be less than previously recorded,
depending on how they were used previously.
@@ -1709,7 +1704,6 @@ frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
post_wait_for_FR (cpu, out_FRk);
/* Restore the busy cycles of the registers we used. */
- fr = ps->fr_busy;
/* The latency of the output register will be at least the latency of the
other inputs. Once initiated, post-processing will take 1 cycle. */
@@ -1751,7 +1745,6 @@ frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
{
int cycles;
FRV_PROFILE_STATE *ps;
- const CGEN_INSN *insn;
INT ACC40Si_1;
INT FRk_1;
@@ -1765,8 +1758,6 @@ frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
ACC40Si_1 = DUAL_REG (in_ACC40Si);
FRk_1 = DUAL_REG (out_FRk);
- insn = idesc->idata;
-
/* The post processing must wait if there is a dependency on a FR
which is not ready yet. */
ps->post_wait = cycles;
@@ -1802,7 +1793,6 @@ frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
{
int cycles;
FRV_PROFILE_STATE *ps;
- const CGEN_INSN *insn;
int busy_adjustment[] = {0};
int *fr;
@@ -1813,7 +1803,6 @@ frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
cycles = idesc->timing->units[unit_num].done;
ps = CPU_PROFILE_STATE (cpu);
- insn = idesc->idata;
/* The latency of the registers may be less than previously recorded,
depending on how they were used previously.
diff --git a/sim/frv/profile-fr500.c b/sim/frv/profile-fr500.c
index 9d268ce7bcec..0593aefd0dfb 100644
--- a/sim/frv/profile-fr500.c
+++ b/sim/frv/profile-fr500.c
@@ -2043,7 +2043,6 @@ frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc,
{
int cycles;
FRV_PROFILE_STATE *ps;
- const CGEN_INSN *insn;
int is_media_s1;
int is_media_s2;
int busy_adjustment[] = {0, 0, 0};
@@ -2057,7 +2056,6 @@ frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc,
cycles = idesc->timing->units[unit_num].done;
ps = CPU_PROFILE_STATE (cpu);
- insn = idesc->idata;
/* If the previous use of the registers was a media op,
then their latency will be less than previously recorded.
--
2.43.0
next prev parent reply other threads:[~2023-12-07 3:59 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-07 3:59 [PATCH 01/17] sim: arm: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 02/17] sim: bfin: gui: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 03/17] sim: bfin: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 04/17] sim: cris: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 05/17] sim: d10v: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 06/17] sim: erc32: " Mike Frysinger
2023-12-07 3:59 ` Mike Frysinger [this message]
2023-12-07 3:59 ` [PATCH 08/17] sim: ft32: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 09/17] sim: h8300: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 10/17] sim: m68hc11: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 11/17] sim: mcore: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 12/17] sim: mips: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 13/17] sim: mn10300: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 14/17] sim: msp430: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 15/17] sim: sh: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 16/17] sim: v850: " Mike Frysinger
2023-12-07 3:59 ` [PATCH 17/17] sim: warnings: enable -Wunused-but-set-variable Mike Frysinger
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