From: <jaydeep.patil@imgtec.com>
To: <gdb-patches@sourceware.org>
Cc: <aburgess@redhat.com>, <vapier@gentoo.org>,
<joseph.faulls@imgtec.com>, <bhushan.attarde@imgtec.com>,
<jaydeep.patil@imgtec.com>
Subject: [PATCH v4 1/2] [sim/riscv] Fix crash during instruction decoding
Date: Thu, 21 Dec 2023 11:11:38 +0000 [thread overview]
Message-ID: <20231221111139.26341-2-jaydeep.patil@imgtec.com> (raw)
In-Reply-To: <20231221111139.26341-1-jaydeep.patil@imgtec.com>
From: Jaydeep Patil <jaydeep.patil@imgtec.com>
The match_never() function has been removed and thus step_once() crashes
during instruction decoding. Fixed it by checking for null pointer before
invoking function attached to match_func member of riscv_opcode structure.
---
opcodes/riscv-dis.c | 2 +-
sim/riscv/sim-main.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 68674380797..a89ebdd32ac 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -818,7 +818,7 @@ riscv_disassemble_insn (bfd_vma memaddr,
if (op->pinfo == INSN_MACRO)
continue;
/* Does the opcode match? */
- if (! (op->match_func) (op, word))
+ if (! op->match_func || ! (op->match_func) (op, word))
continue;
/* Is this a pseudo-instruction and may we print it as such? */
if (no_aliases && (op->pinfo & INSN_ALIAS))
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index afdfcf50656..8a23d2aa1f9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1041,7 +1041,7 @@ void step_once (SIM_CPU *cpu)
for (; op->name; op++)
{
/* Does the opcode match? */
- if (! op->match_func (op, iw))
+ if (! op->match_func || ! op->match_func (op, iw))
continue;
/* Is this a pseudo-instruction and may we print it as such? */
if (op->pinfo & INSN_ALIAS)
--
2.25.1
next prev parent reply other threads:[~2023-12-21 11:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-21 11:11 [PATCH v4 0/2] sim: riscv: Compressed instruction simulation jaydeep.patil
2023-12-21 11:11 ` jaydeep.patil [this message]
2023-12-21 12:48 ` [PATCH v4 1/2] [sim/riscv] Fix crash during instruction decoding Mike Frysinger
2023-12-21 11:13 ` [PATCH v4 2/2] [sim/riscv] Add support for compressed integer instructions jaydeep.patil
2023-12-21 15:07 ` Mike Frysinger
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