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From: Mike Frysinger <vapier@gentoo.org>
To: jaydeep.patil@imgtec.com
Cc: gdb-patches@sourceware.org, aburgess@redhat.com,
	joseph.faulls@imgtec.com, bhushan.attarde@imgtec.com
Subject: Re: [PATCH v4 2/2] [sim/riscv] Add support for compressed integer instructions
Date: Thu, 21 Dec 2023 10:07:14 -0500	[thread overview]
Message-ID: <ZYRUoiAPhj4JMPeN@vapier> (raw)
In-Reply-To: <20231221111337.26415-1-jaydeep.patil@imgtec.com>

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On 21 Dec 2023 11:13, jaydeep.patil@imgtec.com wrote:
> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
>
> +    case INSN_CLASS_C:
> +      /* Check whether model with C extension is selected.  */
> +      if ((riscv_cpu->csr.misa & 4) != 4)

can simplify to:
	if (riscv_cpu->csr.misa & 4) 

> --- a/sim/testsuite/riscv/allinsn.exp
> +++ b/sim/testsuite/riscv/allinsn.exp
> @@ -5,10 +5,29 @@ sim_init
>  # all machines
>  set all_machs "riscv"
>  
> +# Detect model based on -dumpmachine option of the compiler
> +set result [target_compile $srcdir/lib/compilercheck.c \
> +		$objdir/compilercheck.x "preprocess" \
> +		"additional_flags=-dumpmachine"]
> +if { [string match "riscv32-*" $result] } {
> +  set model "RV32IC"
> +} {
> +  set model "RV64IC"
> +}
> +
>  foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
>      # If we're only testing specific files and this isn't one of them, skip it.
>      if ![runtest_file_p $runtests $src] {
>  	continue
>      }
> +
> +    # The c-ext.s needs a model with C extension
> +    global SIMFLAGS_FOR_TARGET
> +    set SIMFLAGS_FOR_TARGET ""
> +    set fname [file tail $src]
> +    if {$fname == "c-ext.s"} {
> +	set SIMFLAGS_FOR_TARGET "--model $model"
> +    }

tests normally declare their requirements, and the exp file processes those
rather than the exp file hardcoding things directly.

try doing:
* change allinsn.exp to do:
  set all_machs "riscv32 riscv64"
* change "mach: riscv" in all testsuite/riscv/*.s files to "mach: all"
* add to c-ext.s:
  # sim(riscv32): --model RV32IC
  # sim(riscv64): --model RV64IC

then i think you can omit the rest of this logic in riscv/allinsn.exp.

this will set us up better for being able to support & test RV32 & RV64 in
the same binary.

> --- /dev/null
> +++ b/sim/testsuite/riscv/c-ext.s
> @@ -0,0 +1,110 @@
> +# Basic load store tests.
> +# mach: riscv
> +
> +.include "testutils.inc"
> +
> +	.data
> +	.align 4
> +_data:
> +	.word	1234
> +	.word	0
> +
> +	start
> +	la	a0, _data
> +
> +	# Test load-store instructions.
> +	.option push
> +	.option	arch, +c

instead of pushing gas arguments, use # directives at the top of the file:
# as: <assembler options>
-mike

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      reply	other threads:[~2023-12-21 15:07 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-21 11:11 [PATCH v4 0/2] sim: riscv: Compressed instruction simulation jaydeep.patil
2023-12-21 11:11 ` [PATCH v4 1/2] [sim/riscv] Fix crash during instruction decoding jaydeep.patil
2023-12-21 12:48   ` Mike Frysinger
2023-12-21 11:13 ` [PATCH v4 2/2] [sim/riscv] Add support for compressed integer instructions jaydeep.patil
2023-12-21 15:07   ` Mike Frysinger [this message]

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