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From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 02/15] sim: arm: fix -Wshadow=local warnings
Date: Thu, 21 Dec 2023 20:23:42 -0500	[thread overview]
Message-ID: <20231222012355.7504-2-vapier@gentoo.org> (raw)
In-Reply-To: <20231222012355.7504-1-vapier@gentoo.org>

Remove duplicate nested variable declarations, rename some to avoid
confusion when the type is different or the original value should be
retained, and fix some weirdness with nested enums in structs.
---
 sim/arm/armemu.c   | 38 +++++++++++++++++---------------------
 sim/arm/thumbemu.c | 22 ++++++----------------
 sim/arm/wrapper.c  | 16 +++++++---------
 3 files changed, 30 insertions(+), 46 deletions(-)

diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index 2b8ae007cb56..cafaabbf637c 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -1023,7 +1023,7 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
 	Rn = BITS (0, 3);
 	if (Rn != 0xF)
 	  {
-	    ARMword val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb)));
+	    val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb)));
 	    state->Reg[Rd] |= val << lsb;
 	  }
 	return 1;
@@ -1434,8 +1434,6 @@ ARMul_Emulate26 (ARMul_State * state)
 	    {
 	      if (BITS (25, 27) == 5) /* BLX(1) */
 		{
-		  ARMword dest;
-
 		  state->Reg[14] = pc + 4;
 
 		  /* Force entry into Thumb mode.  */
@@ -1568,10 +1566,10 @@ check_PMUintr:
 
 		  if (do_int && (cp14r0 & ARMul_CP14_R0_INTEN2))
 		    {
-		      ARMword temp;
+		      ARMword cp;
 
-		      if (state->CPRead[13] (state, 8, & temp)
-			  && (temp & ARMul_CP13_R8_PMUS))
+		      if (state->CPRead[13] (state, 8, & cp)
+			  && (cp & ARMul_CP13_R8_PMUS))
 		        ARMul_Abort (state, ARMul_FIQV);
 		      else
 		        ARMul_Abort (state, ARMul_IRQV);
@@ -1604,8 +1602,8 @@ check_PMUintr:
 		  if (BITS (4, 7) == 0xD)
 		    {
 		      /* XScale Load Consecutive insn.  */
-		      ARMword temp = GetLS7RHS (state, instr);
-		      ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
+		      ARMword temp1 = GetLS7RHS (state, instr);
+		      ARMword temp2 = BIT (23) ? LHS + temp1 : LHS - temp1;
 		      ARMword addr = BIT (24) ? temp2 : LHS;
 
 		      if (BIT (12))
@@ -1630,8 +1628,8 @@ check_PMUintr:
 		  else if (BITS (4, 7) == 0xF)
 		    {
 		      /* XScale Store Consecutive insn.  */
-		      ARMword temp = GetLS7RHS (state, instr);
-		      ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
+		      ARMword temp1 = GetLS7RHS (state, instr);
+		      ARMword temp2 = BIT (23) ? LHS + temp1 : LHS - temp1;
 		      ARMword addr = BIT (24) ? temp2 : LHS;
 
 		      if (BIT (12))
@@ -2313,15 +2311,13 @@ check_PMUintr:
 		  if (BITS (4, 7) == 3)
 		    {
 		      /* BLX(2) */
-		      ARMword temp;
-
 		      if (TFLAG)
-			temp = (pc + 2) | 1;
+			dest = (pc + 2) | 1;
 		      else
-			temp = pc + 4;
+			dest = pc + 4;
 
 		      WriteR15Branch (state, state->Reg[RHSReg]);
-		      state->Reg[14] = temp;
+		      state->Reg[14] = dest;
 		      break;
 		    }
 		}
@@ -2487,7 +2483,7 @@ check_PMUintr:
 		      /* ElSegundo SMLALxy insn.  */
 		      ARMdword op1 = state->Reg[BITS (0, 3)];
 		      ARMdword op2 = state->Reg[BITS (8, 11)];
-		      ARMdword dest;
+		      ARMdword result;
 
 		      if (BIT (5))
 			op1 >>= 16;
@@ -2500,11 +2496,11 @@ check_PMUintr:
 		      if (op2 & 0x8000)
 			op2 -= 65536;
 
-		      dest = (ARMdword) state->Reg[BITS (16, 19)] << 32;
-		      dest |= state->Reg[BITS (12, 15)];
-		      dest += op1 * op2;
-		      state->Reg[BITS (12, 15)] = dest;
-		      state->Reg[BITS (16, 19)] = dest >> 32;
+		      result = (ARMdword) state->Reg[BITS (16, 19)] << 32;
+		      result |= state->Reg[BITS (12, 15)];
+		      result += op1 * op2;
+		      state->Reg[BITS (12, 15)] = result;
+		      state->Reg[BITS (16, 19)] = result >> 32;
 		      break;
 		    }
 
diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c
index 99f51ef34691..58a9c85ce2b9 100644
--- a/sim/arm/thumbemu.c
+++ b/sim/arm/thumbemu.c
@@ -2131,14 +2131,11 @@ ARMul_ThumbDecode (ARMul_State * state,
       if ((tinstr & (1 << 10)) == 0)
 	{
 	  /* Format 4 */
-	  struct
-	  {
+	  struct insn_format {
 	    ARMword opcode;
-	    enum
-	    { t_norm, t_shift, t_neg, t_mul }
-	    otype;
-	  }
-	  subset[16] =
+	    enum { t_norm, t_shift, t_neg, t_mul } otype;
+	  };
+	  struct insn_format subset[16] =
 	  {
 	    { 0xE0100000, t_norm},			/* ANDS Rd,Rd,Rs     */
 	    { 0xE0300000, t_norm},			/* EORS Rd,Rd,Rs     */
@@ -2161,14 +2158,7 @@ ARMul_ThumbDecode (ARMul_State * state,
 
 	  if (in_IT_block ())
 	    {
-	      struct
-	      {
-		ARMword opcode;
-		enum
-		  { t_norm, t_shift, t_neg, t_mul }
-		  otype;
-	      }
-	      subset[16] =
+	      struct insn_format it_subset[16] =
 		{
 		  { 0xE0000000, t_norm},	/* AND  Rd,Rd,Rs     */
 		  { 0xE0200000, t_norm},	/* EOR  Rd,Rd,Rs     */
@@ -2187,7 +2177,7 @@ ARMul_ThumbDecode (ARMul_State * state,
 		  { 0xE1C00000, t_norm},	/* BIC  Rd,Rd,Rs     */
 		  { 0xE1E00000, t_norm}		/* MVN  Rd,Rs        */
 		};
-	      *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode;	/* base */
+	      *ainstr = it_subset[(tinstr & 0x03C0) >> 6].opcode;	/* base */
 	    }
 
 	  switch (subset[(tinstr & 0x03C0) >> 6].otype)
diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c
index 8d928a6f79f9..06512754725b 100644
--- a/sim/arm/wrapper.c
+++ b/sim/arm/wrapper.c
@@ -746,14 +746,14 @@ sim_target_parse_command_line (int argc, char ** argv)
 
       while (* ptr)
 	{
-	  int i;
+	  int o;
 
-	  for (i = ARRAY_SIZE (options); i--;)
-	    if (strncmp (ptr, options[i].swi_option,
-			 strlen (options[i].swi_option)) == 0)
+	  for (o = ARRAY_SIZE (options); o--;)
+	    if (strncmp (ptr, options[o].swi_option,
+			 strlen (options[o].swi_option)) == 0)
 	      {
-		swi_mask |= options[i].swi_mask;
-		ptr += strlen (options[i].swi_option);
+		swi_mask |= options[o].swi_mask;
+		ptr += strlen (options[o].swi_option);
 
 		if (* ptr == ',')
 		  ++ ptr;
@@ -761,7 +761,7 @@ sim_target_parse_command_line (int argc, char ** argv)
 		break;
 	      }
 
-	  if (i < 0)
+	  if (o < 0)
 	    break;
 	}
 
@@ -884,8 +884,6 @@ sim_open (SIM_OPEN_KIND kind,
 
   if (argv_copy[1] != NULL)
     {
-      int i;
-
       /* Scan for memory-size switches.  */
       for (i = 0; (argv_copy[i] != NULL) && (argv_copy[i][0] != 0); i++)
 	if (argv_copy[i][0] == '-' && argv_copy[i][1] == 'm')
-- 
2.43.0


  reply	other threads:[~2023-12-22  1:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-22  1:23 [PATCH 01/15] sim: aarch64: " Mike Frysinger
2023-12-22  1:23 ` Mike Frysinger [this message]
2023-12-22  1:23 ` [PATCH 03/15] sim: bfin: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 04/15] sim: common: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 05/15] sim: cris: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 06/15] sim: erc32: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 07/15] sim: frv: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 08/15] sim: h8300: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 09/15] sim: iq2000: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 10/15] sim: m68hc11: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 11/15] sim: mips: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 12/15] sim: ppc: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 13/15] sim: riscv: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 14/15] sim: sh: " Mike Frysinger
2023-12-22  1:23 ` [PATCH 15/15] sim: warnings: enable -Wshadow=local Mike Frysinger
2023-12-22 15:26   ` Tom Tromey
2023-12-23  4:28 ` [PATCH] sim: m32c: fix -Wshadow=local warnings Mike Frysinger
2023-12-23  4:28 ` [PATCH] sim: cris: disable -Wshadow=local in generated mloop files Mike Frysinger

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