* [PATCH] sim: cris: add error fallbacks when decoding condition & swap codes
@ 2023-12-24 10:17 Mike Frysinger
0 siblings, 0 replies; only message in thread
From: Mike Frysinger @ 2023-12-24 10:17 UTC (permalink / raw)
To: gdb-patches; +Cc: hp
The condition & swap code decoder only checks known bits and sets
based on that. If the variable is out of range, it ends up returning
uninitialized data. Turn that case into a hard error.
This fixes build warnings like:
sim/cris/semcrisv10f-switch.c:13115:11: error:
variable 'tmp_condres' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized]
---
cpu/cris.cpu | 6 ++++--
sim/cris/semcrisv10f-switch.c | 12 ++++++++++++
sim/cris/semcrisv32f-switch.c | 12 ++++++++++++
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/cpu/cris.cpu b/cpu/cris.cpu
index 2fcd04e8e361..5d50307e65bf 100644
--- a/cpu/cris.cpu
+++ b/cpu/cris.cpu
@@ -550,7 +550,8 @@
(condn condc)
((eq tmpcond condn) (set condres (.sym condc -condition))))
(.iota 16)
- cris-condition-codes)))
+ cris-condition-codes))
+ (else (error "Unknown condition code")))
condres)
)
@@ -3710,7 +3711,8 @@
((eq tmpcode x-swapcode)
(set tmpres ((.sym swap- x-swap) tmpval))))
(.iota 16)
- (.splice _ (.unsplice cris-swap-codes)))))
+ (.splice _ (.unsplice cris-swap-codes))))
+ (else (error "Unknown swapcode")))
tmpres)
)
diff --git a/sim/cris/semcrisv10f-switch.c b/sim/cris/semcrisv10f-switch.c
index a803809ddc6e..d3967435b20c 100644
--- a/sim/cris/semcrisv10f-switch.c
+++ b/sim/cris/semcrisv10f-switch.c
@@ -11090,6 +11090,9 @@ SET_H_VBIT_MOVE (0);
; ORSI (ANDSI (SLLSI (tmp_tmpw, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpw, 16), 65535)); });
; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else {
+cgen_rtx_error (current_cpu, "Unknown swapcode");
}
; tmp_tmpres; });
{
@@ -12109,6 +12112,9 @@ if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
}
else if (EQSI (tmp_tmpcond, 15)) {
tmp_condres = CPU (h_pbit);
+}
+ else {
+cgen_rtx_error (current_cpu, "Unknown condition code");
}
; tmp_condres; });
crisv10f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
@@ -12241,6 +12247,9 @@ if (tmp_truthval) {
}
else if (EQSI (tmp_tmpcond, 15)) {
tmp_condres = CPU (h_pbit);
+}
+ else {
+cgen_rtx_error (current_cpu, "Unknown condition code");
}
; tmp_condres; });
crisv10f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
@@ -13114,6 +13123,9 @@ SET_H_VBIT_MOVE (0);
}
else if (EQSI (tmp_tmpcond, 15)) {
tmp_condres = CPU (h_pbit);
+}
+ else {
+cgen_rtx_error (current_cpu, "Unknown condition code");
}
; tmp_condres; });
{
diff --git a/sim/cris/semcrisv32f-switch.c b/sim/cris/semcrisv32f-switch.c
index aa22ea24fd2b..6a23bd76fa51 100644
--- a/sim/cris/semcrisv32f-switch.c
+++ b/sim/cris/semcrisv32f-switch.c
@@ -11360,6 +11360,9 @@ SET_H_VBIT_MOVE (0);
; ORSI (ANDSI (SLLSI (tmp_tmpw, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpw, 16), 65535)); });
; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else {
+cgen_rtx_error (current_cpu, "Unknown swapcode");
}
; tmp_tmpres; });
{
@@ -12509,6 +12512,9 @@ crisv32f_rfg_handler (current_cpu, pc);
}
else if (EQSI (tmp_tmpcond, 15)) {
tmp_condres = CPU (h_pbit);
+}
+ else {
+cgen_rtx_error (current_cpu, "Unknown condition code");
}
; tmp_condres; });
crisv32f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
@@ -12641,6 +12647,9 @@ if (tmp_truthval) {
}
else if (EQSI (tmp_tmpcond, 15)) {
tmp_condres = CPU (h_pbit);
+}
+ else {
+cgen_rtx_error (current_cpu, "Unknown condition code");
}
; tmp_condres; });
crisv32f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
@@ -13429,6 +13438,9 @@ SET_H_VBIT_MOVE (0);
}
else if (EQSI (tmp_tmpcond, 15)) {
tmp_condres = CPU (h_pbit);
+}
+ else {
+cgen_rtx_error (current_cpu, "Unknown condition code");
}
; tmp_condres; });
{
--
2.43.0
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2023-12-24 10:17 [PATCH] sim: cris: add error fallbacks when decoding condition & swap codes Mike Frysinger
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