From: <jaydeep.patil@imgtec.com>
To: <gdb-patches@sourceware.org>
Cc: <aburgess@redhat.com>, <vapier@gentoo.org>,
<joseph.faulls@imgtec.com>, <bhushan.attarde@imgtec.com>,
<jaydeep.patil@imgtec.com>
Subject: [PATCH v6 0/2] sim: riscv: Compressed instruction simulation
Date: Thu, 11 Jan 2024 05:28:20 +0000 [thread overview]
Message-ID: <20240111052822.1576345-1-jaydeep.patil@imgtec.com> (raw)
From: Jaydeep Patil <jaydeep.patil@imgtec.com>
Hi Mike, Andrew,
Addressed review comments.
- Restored opcodes/riscv-dis.c
- Commit message changed to "sim: riscv:"
Jaydeep Patil (2):
sim: riscv: Fix crash during instruction decoding
sim: riscv: Add support for compressed integer instructions
sim/riscv/model_list.def | 9 +
sim/riscv/sim-main.c | 339 ++++++++++++++++++++++++++++++--
sim/testsuite/riscv/allinsn.exp | 2 +-
sim/testsuite/riscv/c-ext.s | 95 +++++++++
sim/testsuite/riscv/jalr.s | 2 +-
sim/testsuite/riscv/m-ext.s | 2 +-
sim/testsuite/riscv/pass.s | 2 +-
7 files changed, 436 insertions(+), 15 deletions(-)
create mode 100644 sim/testsuite/riscv/c-ext.s
--
2.25.1
next reply other threads:[~2024-01-11 5:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-11 5:28 jaydeep.patil [this message]
2024-01-11 5:28 ` [PATCH v6 1/2] sim: riscv: Fix crash during instruction decoding jaydeep.patil
2024-01-22 10:18 ` Andrew Burgess
2024-01-23 1:18 ` Mike Frysinger
2024-01-11 5:28 ` [PATCH v6 2/2] sim: riscv: Add support for compressed integer instructions jaydeep.patil
2024-01-22 10:24 ` Andrew Burgess
2024-01-23 5:35 ` [EXTERNAL] " Jaydeep Patil
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