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From: <jaydeep.patil@imgtec.com>
To: <gdb-patches@sourceware.org>
Cc: <aburgess@redhat.com>, <vapier@gentoo.org>,
	<joseph.faulls@imgtec.com>, <bhushan.attarde@imgtec.com>,
	<jaydeep.patil@imgtec.com>
Subject: [PATCH v6 1/2] sim: riscv: Fix crash during instruction decoding
Date: Thu, 11 Jan 2024 05:28:21 +0000	[thread overview]
Message-ID: <20240111052822.1576345-2-jaydeep.patil@imgtec.com> (raw)
In-Reply-To: <20240111052822.1576345-1-jaydeep.patil@imgtec.com>

From: Jaydeep Patil <jaydeep.patil@imgtec.com>

The match_never() function has been removed and thus step_once() crashes
during instruction decoding. Fixed it by checking for null pointer before
invoking function attached to match_func member of riscv_opcode structure
---
 sim/riscv/sim-main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index b04d12c0de1..25dc9b41412 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1040,7 +1040,7 @@ void step_once (SIM_CPU *cpu)
   for (; op->name; op++)
     {
       /* Does the opcode match?  */
-      if (! op->match_func (op, iw))
+      if (! op->match_func || ! op->match_func (op, iw))
 	continue;
       /* Is this a pseudo-instruction and may we print it as such?  */
       if (op->pinfo & INSN_ALIAS)
-- 
2.25.1


  reply	other threads:[~2024-01-11  5:28 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-11  5:28 [PATCH v6 0/2] sim: riscv: Compressed instruction simulation jaydeep.patil
2024-01-11  5:28 ` jaydeep.patil [this message]
2024-01-22 10:18   ` [PATCH v6 1/2] sim: riscv: Fix crash during instruction decoding Andrew Burgess
2024-01-23  1:18   ` Mike Frysinger
2024-01-11  5:28 ` [PATCH v6 2/2] sim: riscv: Add support for compressed integer instructions jaydeep.patil
2024-01-22 10:24   ` Andrew Burgess
2024-01-23  5:35     ` [EXTERNAL] " Jaydeep Patil

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