From: "H.J. Lu" <hjl.tools@gmail.com>
To: gdb-patches@sourceware.org
Cc: felix.willgerodt@intel.com
Subject: [PATCH v2] gdb: Add XMM16-XMM31 and K0-K1 DWARF register number mapping
Date: Wed, 14 Feb 2024 07:40:12 -0800 [thread overview]
Message-ID: <20240214154012.32319-1-hjl.tools@gmail.com> (raw)
Changes in v2:
1. Remove UTF-8 encoding.
---
Add XMM16-XMM31 and K0-K1 DWARF register number mapping to
amd64_dwarf_regmap.
---
gdb/amd64-tdep.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c
index a8ff9246b8a..b6ff1c67a86 100644
--- a/gdb/amd64-tdep.c
+++ b/gdb/amd64-tdep.c
@@ -235,7 +235,28 @@ static int amd64_dwarf_regmap[] =
/* Floating Point Control Registers. */
AMD64_MXCSR_REGNUM,
AMD64_FCTRL_REGNUM,
- AMD64_FSTAT_REGNUM
+ AMD64_FSTAT_REGNUM,
+
+ /* XMM16-XMM31. */
+ AMD64_XMM16_REGNUM + 0, AMD64_XMM16_REGNUM + 1,
+ AMD64_XMM16_REGNUM + 2, AMD64_XMM16_REGNUM + 3,
+ AMD64_XMM16_REGNUM + 4, AMD64_XMM16_REGNUM + 5,
+ AMD64_XMM16_REGNUM + 6, AMD64_XMM16_REGNUM + 7,
+ AMD64_XMM16_REGNUM + 8, AMD64_XMM16_REGNUM + 9,
+ AMD64_XMM16_REGNUM + 10, AMD64_XMM16_REGNUM + 11,
+ AMD64_XMM16_REGNUM + 12, AMD64_XMM16_REGNUM + 13,
+ AMD64_XMM16_REGNUM + 14, AMD64_XMM16_REGNUM + 15,
+
+ /* Reserved. */
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+
+ /* Mask Registers. */
+ AMD64_K0_REGNUM + 0, AMD64_K0_REGNUM + 1,
+ AMD64_K0_REGNUM + 2, AMD64_K0_REGNUM + 3,
+ AMD64_K0_REGNUM + 4, AMD64_K0_REGNUM + 5,
+ AMD64_K0_REGNUM + 6, AMD64_K0_REGNUM + 7
};
static const int amd64_dwarf_regmap_len =
--
2.43.0
next reply other threads:[~2024-02-14 15:40 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-14 15:40 H.J. Lu [this message]
2024-02-21 8:33 ` Willgerodt, Felix
2024-02-21 21:21 ` H.J. Lu
2024-02-22 10:53 ` Willgerodt, Felix
2024-02-22 14:45 ` PING: " H.J. Lu
2024-02-23 0:36 ` John Baldwin
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