* [PATCH 01/11] sim: riscv: Add single precision floating-point load-store, move, compare and classify instructions
2024-02-26 14:22 [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions bhushan.attarde
@ 2024-02-26 14:22 ` bhushan.attarde
2024-02-26 14:22 ` [PATCH 02/11] sim: riscv: Add single precision floating-point sign injection, min and max instructions bhushan.attarde
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: bhushan.attarde @ 2024-02-26 14:22 UTC (permalink / raw)
To: gdb-patches; +Cc: aburgess, vapier, Jaydeep.Patil, Bhushan Attarde
From: Bhushan Attarde <bhushan.attarde@imgtec.com>
Added simulation of following single precision floating-point instructions
flw, fsw, fmv.x.w, fmv.w.x, fsgnj.s, feq.s, flt.s, fle.s and fclass.s.
Added test files s-fp-compare.s, s-fp-load-store.s and s-fp-sign-inject.s in
sim/testsuite/riscv/ to test these instructions.
---
sim/riscv/model_list.def | 4 +
sim/riscv/sim-main.c | 214 +++++++++++++++++++++++++
sim/testsuite/riscv/s-fp-compare.s | 75 +++++++++
sim/testsuite/riscv/s-fp-load-store.s | 62 +++++++
sim/testsuite/riscv/s-fp-sign-inject.s | 52 ++++++
5 files changed, 407 insertions(+)
create mode 100644 sim/testsuite/riscv/s-fp-compare.s
create mode 100644 sim/testsuite/riscv/s-fp-load-store.s
create mode 100644 sim/testsuite/riscv/s-fp-sign-inject.s
diff --git a/sim/riscv/model_list.def b/sim/riscv/model_list.def
index b83557e5539..265b1714faf 100644
--- a/sim/riscv/model_list.def
+++ b/sim/riscv/model_list.def
@@ -5,6 +5,8 @@ M(IMA)
M(IA)
M(GC)
M(IC)
+M(IF)
+M(ID)
M(IMC)
M(IMAC)
M(IAC)
@@ -13,6 +15,8 @@ M(EM)
M(EMA)
M(EA)
M(EC)
+M(EF)
+M(ED)
M(EMC)
M(EMAC)
M(EAC)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index adff99921c6..d3a07585944 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -24,6 +24,7 @@
/* This must come before any other includes. */
#include "defs.h"
+#include <math.h>
#include <inttypes.h>
#include <time.h>
@@ -64,6 +65,17 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
} \
} while (0)
+#define FCSR_NX 0x1 /* Inexact. */
+#define FCSR_UF 0x2 /* Underflow. */
+#define FCSR_OF 0x4 /* Overflow. */
+#define FCSR_DZ 0x8 /* Divide by zero. */
+#define FCSR_NV 0x10 /* Invalid Operation. */
+
+#define FEQ 1
+#define FLT 2
+#define FLE 3
+#define FCLASS 4
+
static INLINE void
store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
{
@@ -76,6 +88,16 @@ store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
}
}
+/* Store a value into floating point register. */
+static INLINE void
+store_fp (SIM_CPU *cpu, int rd, unsigned_word val)
+{
+ struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+
+ riscv_cpu->fpregs[rd] = val;
+ TRACE_REG (cpu, rd);
+}
+
static INLINE unsigned_word
fetch_csr (SIM_CPU *cpu, const char *name, int csr, unsigned_word *reg)
{
@@ -682,6 +704,195 @@ mulhsu (int64_t a, uint64_t b)
return negate ? ~res + (a * b == 0) : res;
}
+/* Handle single precision floating point compare instructions. */
+static void
+float32_compare (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
+{
+ struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+ float a, b = .0f;
+ uint32_t result = 0, exception = 0, sign = 0, bit_pos;
+ uint32_t rs1_bits, rs2_bits;
+ const char *rd_name = riscv_gpr_names_abi[rd];
+ const char *frs1_name = riscv_fpr_names_abi[rs1];
+ const char *frs2_name = riscv_fpr_names_abi[rs2];
+
+ rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1];
+ memcpy (&a, &rs1_bits, sizeof (a));
+
+ if (flags != FCLASS)
+ {
+ rs2_bits = (uint32_t) riscv_cpu->fpregs[rs2];
+ memcpy (&b, &rs2_bits, sizeof (b));
+ }
+
+ switch (flags)
+ {
+ case FEQ:
+ TRACE_INSN (cpu, "feq.s %s, %s, %s;", rd_name, frs1_name, frs2_name);
+ if (__isnanf (a) || __isnanf (b))
+ {
+ result = 0;
+ if (__issignalingf (a) || __issignalingf (b))
+ exception = 1;
+ }
+ else
+ result = (a == b);
+ break;
+ case FLT:
+ TRACE_INSN (cpu, "flt.s %s, %s, %s;", rd_name, frs1_name, frs2_name);
+ if (__isnanf (a) || __isnanf (b))
+ {
+ result = 0;
+ exception = 1;
+ }
+ else
+ result = (a < b);
+ break;
+ case FLE:
+ TRACE_INSN (cpu, "fle.s %s, %s, %s;", rd_name, frs1_name, frs2_name);
+ if (__isnanf (a) || __isnanf (b))
+ {
+ result = 0;
+ exception = 1;
+ }
+ else
+ result = (a <= b);
+ break;
+ case FCLASS:
+ TRACE_INSN (cpu, "fclass.s %s, %s;", rd_name, frs1_name);
+ bit_pos = 0;
+ exception = 0;
+ result = riscv_cpu->regs[rd];
+ sign = __signbitf (a);
+ if (__isinff (a))
+ {
+ if (sign)
+ bit_pos = 0; /* -INF. */
+ else
+ bit_pos = 7; /* +INF. */
+ }
+ else if (fpclassify (a) == FP_SUBNORMAL)
+ {
+ if (sign)
+ bit_pos = 2; /* -SUBNORMAL. */
+ else
+ bit_pos = 5; /* +SUBNORMAL. */
+ }
+ else if (fpclassify (a) == FP_ZERO)
+ {
+ if (sign)
+ bit_pos = 3; /* -ZERO. */
+ else
+ bit_pos = 4; /* +ZERO. */
+ }
+ else if (__issignalingf (a))
+ bit_pos = 8; /* signaling NaN. */
+ else if (__isnanf (a))
+ bit_pos = 9; /* quiet NaN. */
+ else
+ {
+ if (sign)
+ bit_pos = 1; /* -NORMAL. */
+ else
+ bit_pos = 6; /* +NORMAL. */
+ }
+ result |= (1 << bit_pos);
+ break;
+ }
+
+ store_rd (cpu, rd, result);
+
+ if (exception)
+ {
+ riscv_cpu->csr.fcsr |= FCSR_NV;
+ riscv_cpu->csr.fflags |= FCSR_NV;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr |= NV");
+ }
+}
+
+/* Simulate single precision floating point instructions. */
+static sim_cia
+execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
+{
+ struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+ SIM_DESC sd = CPU_STATE (cpu);
+ int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+ int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
+ int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
+ const char *frd_name = riscv_fpr_names_abi[rd];
+ const char *rd_name = riscv_gpr_names_abi[rd];
+ const char *frs1_name = riscv_fpr_names_abi[rs1];
+ const char *frs2_name = riscv_fpr_names_abi[rs2];
+ const char *rs1_name = riscv_gpr_names_abi[rs1];
+ signed_word i_imm = EXTRACT_ITYPE_IMM (iw);
+ signed_word s_imm = EXTRACT_STYPE_IMM (iw);
+ int is_32bit = (RISCV_XLEN (cpu) == 32);
+
+ sim_cia pc = riscv_cpu->pc + 4;
+
+ switch (op->match)
+ {
+ case MATCH_FLW:
+ TRACE_INSN (cpu, "flw %s, %" PRIiTW "(%s);",
+ frd_name, i_imm, rs1_name);
+ store_fp (cpu, rd, sim_core_read_unaligned_4 (cpu, riscv_cpu->pc,
+ read_map, riscv_cpu->regs[rs1] + i_imm));
+ break;
+ case MATCH_FSW:
+ TRACE_INSN (cpu, "fsw %s, %" PRIiTW "(%s);",
+ frs2_name, s_imm, rs1_name);
+ sim_core_write_unaligned_4 (cpu, riscv_cpu->pc, write_map,
+ riscv_cpu->regs[rs1] + s_imm,
+ riscv_cpu->fpregs[rs2]);
+ break;
+ case MATCH_FMV_X_S:
+ TRACE_INSN (cpu, "fmv.x.w %s, %s;", rd_name, frs1_name);
+ if (is_32bit)
+ store_rd (cpu, rd, riscv_cpu->fpregs[rs1]);
+ else
+ {
+ uint64_t f64bits;
+ f64bits = (uint64_t) ((uint32_t) riscv_cpu->fpregs[rs1]);
+ if (f64bits & 0x80000000)
+ f64bits = (uint64_t) (0xffffffff00000000ull | (uint32_t) f64bits);
+ store_rd (cpu, rd, f64bits);
+ }
+ break;
+ case MATCH_FMV_S_X:
+ TRACE_INSN (cpu, "fmv.w.x %s, %s;", frd_name, rs1_name);
+ store_fp (cpu, rd, riscv_cpu->regs[rs1]);
+ break;
+ case MATCH_FSGNJ_S:
+ {
+ uint32_t rs1_bits, rs2_bits;
+ TRACE_INSN (cpu, "fsgnj.s %s, %s, %s;",
+ frd_name, frs1_name, frs2_name);
+ rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1];
+ rs2_bits = (uint32_t) riscv_cpu->fpregs[rs2];
+ rs1_bits = (rs2_bits & 0x80000000) | (rs1_bits & 0x7fffffff);
+ store_fp (cpu, rd, rs1_bits);
+ break;
+ }
+ case MATCH_FEQ_S:
+ float32_compare (cpu, rd, rs1, rs2, FEQ);
+ break;
+ case MATCH_FLT_S:
+ float32_compare (cpu, rd, rs1, rs2, FLT);
+ break;
+ case MATCH_FLE_S:
+ float32_compare (cpu, rd, rs1, rs2, FLE);
+ break;
+ case MATCH_FCLASS_S:
+ float32_compare (cpu, rd, rs1, 0, FCLASS);
+ break;
+ default:
+ TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
+ }
+
+ return pc;
+}
+
static sim_cia
execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
{
@@ -1313,6 +1524,9 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
SIM_SIGILL);
}
+ case INSN_CLASS_F:
+ case INSN_CLASS_F_INX:
+ return execute_f (cpu, iw, op);
case INSN_CLASS_I:
return execute_i (cpu, iw, op);
case INSN_CLASS_M:
diff --git a/sim/testsuite/riscv/s-fp-compare.s b/sim/testsuite/riscv/s-fp-compare.s
new file mode 100644
index 00000000000..d5b98b30233
--- /dev/null
+++ b/sim/testsuite/riscv/s-fp-compare.s
@@ -0,0 +1,75 @@
+# Single precision compare and classify tests.
+# mach: riscv32 riscv64
+# sim(riscv32): --model RV32IF
+# sim(riscv64): --model RV64ID
+# ld(riscv32): -m elf32lriscv
+# ld(riscv64): -m elf64lriscv
+# as(riscv32): -march=rv32if
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+ .section .data
+ .align 2
+
+_arg1:
+ .float 0.5
+ .float 1.1
+ .word 0xff800000 # -INF
+ .word 0x7faaaaaa # sNAN
+ .word 0x7feaaaaa # qNAN
+
+_arg2:
+ .float 0.5
+ .float 2.2
+
+ start
+ .option push
+ .option norelax
+ la a0,_arg1
+ la a1,_arg2
+ li a3,1
+ .option pop
+
+ # Test feq instruction.
+ flw fa0,0(a0)
+ flw fa1,0(a1)
+ feq.s a4,fa0,fa1
+ bne a4,a3,test_fail
+
+ # Test flt instruction.
+ flw fa0,4(a0)
+ flw fa1,4(a1)
+ mv a4,x0
+ flt.s a4,fa0,fa1
+ bne a4,a3,test_fail
+
+ # Test fle instruction.
+ flw fa0,4(a0)
+ flw fa1,4(a1)
+ mv a4,x0
+ fle.s a4,fa0,fa1
+ bne a4,a3,test_fail
+
+ # Test fclass instruction.
+ flw fa0,8(a0)
+ mv a4,x0
+ li a3,0x1 # 1 << 0
+ fclass.s a4,fa0
+ bne a3,a4,test_fail
+ flw fa0,12(a0)
+ mv a4,x0
+ li a3,0x100 # 1 << 8
+ fclass.s a4,fa0
+ bne a3,a4,test_fail
+ flw fa0,16(a0)
+ mv a4,x0
+ li a3,0x200 # 1 << 9
+ fclass.s a4,fa0
+ bne a3,a4,test_fail
+
+test_pass:
+ pass
+
+test_fail:
+ fail
diff --git a/sim/testsuite/riscv/s-fp-load-store.s b/sim/testsuite/riscv/s-fp-load-store.s
new file mode 100644
index 00000000000..0a979d10e70
--- /dev/null
+++ b/sim/testsuite/riscv/s-fp-load-store.s
@@ -0,0 +1,62 @@
+# Single precision load-store and move tests.
+# mach: riscv32 riscv64
+# sim(riscv32): --model RV32IF
+# sim(riscv64): --model RV64ID
+# ld(riscv32): -m elf32lriscv
+# ld(riscv64): -m elf64lriscv
+# as(riscv32): -march=rv32if
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+ .section .data
+ .align 2
+
+_src:
+ .float 0.5
+
+_dst:
+ .float 0.5
+ .float 0
+ .word 0x3f000000 # 0.5
+
+ start
+ .option push
+ .option norelax
+ la a0,_src
+ la a1,_dst
+ li a3,1
+ .option pop
+
+ # Test load instruction.
+ flw fa0,0(a0)
+ flw fa1,0(a1)
+ feq.s a4,fa0,fa1
+ bne a4,a3,test_fail
+
+ # Test store instruction.
+ flw fa0,0(a0)
+ fsw fa0,4(a1)
+ flw fa1,4(a1)
+ feq.s a4,fa0,fa1
+ bne a4,a3,test_fail
+
+ # Test convert float value to integer encoding instruction.
+ flw fa0,0(a0) # load float value.
+ lw a4,8(a1) # load expected result.
+ fmv.x.w a2,fa0 # convert bit pattern into integer register.
+ bne a4,a2,test_fail # compare result with expected.
+
+ # Test convert integer encoding to float value instruction.
+ lw a4,8(a1) # load integer encoding.
+ fmv.w.x fa1,a4 # convert encoding into float value.
+ flw fa0,0(a0) # load expected float value.
+ feq.s a5,fa0,fa1 # compare result with expected.
+ bne a5,a3,test_fail
+
+
+test_pass:
+ pass
+
+test_fail:
+ fail
diff --git a/sim/testsuite/riscv/s-fp-sign-inject.s b/sim/testsuite/riscv/s-fp-sign-inject.s
new file mode 100644
index 00000000000..733756a2197
--- /dev/null
+++ b/sim/testsuite/riscv/s-fp-sign-inject.s
@@ -0,0 +1,52 @@
+# Single precision sign-injection instructions.
+# mach: riscv32 riscv64
+# sim(riscv32): --model RV32IF
+# sim(riscv64): --model RV64ID
+# ld(riscv32): -m elf32lriscv
+# ld(riscv64): -m elf64lriscv
+# as(riscv32): -march=rv32if
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+ .section .data
+ .align 2
+
+_arg1:
+ .float 2.0
+
+_arg2:
+ .float 1.0
+ .float -1.0
+
+_expected:
+ .float 2.0
+ .float -2.0
+
+ start
+ .option push
+ .option norelax
+ la a0,_arg1
+ la a1,_arg2
+ la a2,_expected
+ li a3,1
+ .option pop
+
+ # Test fsgnj.s instruction.
+ flw fa0,0(a0)
+ flw fa1,0(a1)
+ flw fa2,0(a2)
+ fsgnj.s fa3,fa0,fa1
+ feq.s a4,fa3,fa2
+ bne a4,a3,test_fail
+ flw fa1,4(a1)
+ flw fa2,4(a2)
+ fsgnj.s fa3,fa0,fa1
+ feq.s a4,fa3,fa2
+ bne a4,a3,test_fail
+
+test_pass:
+ pass
+
+test_fail:
+ fail
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 02/11] sim: riscv: Add single precision floating-point sign injection, min and max instructions
2024-02-26 14:22 [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions bhushan.attarde
2024-02-26 14:22 ` [PATCH 01/11] sim: riscv: Add single precision floating-point load-store, move, compare and classify instructions bhushan.attarde
@ 2024-02-26 14:22 ` bhushan.attarde
2024-02-26 14:22 ` [PATCH 03/11] sim: riscv: Add floating-point CSR instructions bhushan.attarde
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: bhushan.attarde @ 2024-02-26 14:22 UTC (permalink / raw)
To: gdb-patches; +Cc: aburgess, vapier, Jaydeep.Patil, Bhushan Attarde
From: Bhushan Attarde <bhushan.attarde@imgtec.com>
Added simulation of following single precision floating-point instructions
sgnjn.s (fneg.s), fsgnjx.s (fabs.s), fmin.s and fmax.s.
Updated test files s-fp-compare.s and s-fp-sign-inject.s in
sim/testsuite/riscv/ to test these instructions
---
sim/riscv/sim-main.c | 64 ++++++++++++++++++++++++++
sim/testsuite/riscv/s-fp-compare.s | 22 +++++++++
sim/testsuite/riscv/s-fp-sign-inject.s | 38 +++++++++++++++
3 files changed, 124 insertions(+)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index d3a07585944..9c132d9a448 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -75,6 +75,8 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
#define FLT 2
#define FLE 3
#define FCLASS 4
+#define FMIN 5
+#define FMAX 6
static INLINE void
store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
@@ -810,6 +812,39 @@ float32_compare (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
}
}
+/* Handle single precision floating point math instructions. */
+static void
+float32_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
+{
+ struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+ float a, b, result = 0;
+ uint32_t rs1_bits, rs2_bits, rd_bits;
+ const char *frd_name = riscv_fpr_names_abi[rd];
+ const char *frs1_name = riscv_fpr_names_abi[rs1];
+ const char *frs2_name = riscv_fpr_names_abi[rs2];
+
+ rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1];
+ memcpy (&a, &rs1_bits, sizeof (a));
+ rs2_bits = (uint32_t) riscv_cpu->fpregs[rs2];
+ memcpy (&b, &rs2_bits, sizeof (b));
+
+ switch (flags)
+ {
+ case FMAX:
+ TRACE_INSN (cpu, "fmax.s %s, %s, %s;", frd_name, frs1_name, frs2_name);
+ result = fmaxf (a, b);
+ break;
+ case FMIN:
+ TRACE_INSN (cpu, "fmin.s %s, %s, %s;", frd_name, frs1_name, frs2_name);
+ result = fminf (a, b);
+ break;
+ }
+
+ /* Store result. */
+ memcpy (&rd_bits, &result, sizeof (result));
+ store_fp (cpu, rd, rd_bits);
+}
+
/* Simulate single precision floating point instructions. */
static sim_cia
execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
@@ -885,6 +920,35 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
case MATCH_FCLASS_S:
float32_compare (cpu, rd, rs1, 0, FCLASS);
break;
+ case MATCH_FSGNJN_S:
+ {
+ uint32_t rs1_bits, rs2_bits;
+ TRACE_INSN (cpu, "fsgnjn.s %s, %s, %s;", frd_name, frs1_name,
+ frs2_name);
+ rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1];
+ rs2_bits = ~((uint32_t) riscv_cpu->fpregs[rs2]);
+ rs1_bits = (rs2_bits & 0x80000000) | (rs1_bits & 0x7fffffff);
+ store_fp (cpu, rd, rs1_bits);
+ break;
+ }
+ case MATCH_FSGNJX_S:
+ {
+ uint32_t rs1_bits, rs2_bits;
+ TRACE_INSN (cpu, "fsgnjx.s %s, %s, %s;", frd_name, frs1_name,
+ frs2_name);
+ rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1];
+ rs2_bits = (uint32_t) riscv_cpu->fpregs[rs2];
+ rs1_bits = ((rs1_bits & 0x80000000) ^ (rs2_bits & 0x80000000))
+ | (rs1_bits & 0x7fffffff);
+ store_fp (cpu, rd, rs1_bits);
+ break;
+ }
+ case MATCH_FMIN_S:
+ float32_math (cpu, rd, rs1, rs2, FMIN);
+ break;
+ case MATCH_FMAX_S:
+ float32_math (cpu, rd, rs1, rs2, FMAX);
+ break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
diff --git a/sim/testsuite/riscv/s-fp-compare.s b/sim/testsuite/riscv/s-fp-compare.s
index d5b98b30233..7aef3ce51c2 100644
--- a/sim/testsuite/riscv/s-fp-compare.s
+++ b/sim/testsuite/riscv/s-fp-compare.s
@@ -23,11 +23,16 @@ _arg2:
.float 0.5
.float 2.2
+_expected:
+ .float 0.5
+ .float 2.2
+
start
.option push
.option norelax
la a0,_arg1
la a1,_arg2
+ la a2,_expected
li a3,1
.option pop
@@ -68,6 +73,23 @@ _arg2:
fclass.s a4,fa0
bne a3,a4,test_fail
+ # Test fmin.s instruction.
+ flw fa0,0(a0)
+ flw fa1,4(a1)
+ flw fa2,0(a2)
+ fmin.s fa3,fa0,fa1
+ feq.s a4,fa3,fa2
+ li a3,1
+ bne a4,a3,test_fail
+
+ # Test fmax.s instruction.
+ flw fa0,0(a0)
+ flw fa1,4(a1)
+ flw fa2,4(a2)
+ fmax.s fa3,fa0,fa1
+ feq.s a4,fa3,fa2
+ bne a4,a3,test_fail
+
test_pass:
pass
diff --git a/sim/testsuite/riscv/s-fp-sign-inject.s b/sim/testsuite/riscv/s-fp-sign-inject.s
index 733756a2197..e4efbaaf29e 100644
--- a/sim/testsuite/riscv/s-fp-sign-inject.s
+++ b/sim/testsuite/riscv/s-fp-sign-inject.s
@@ -14,6 +14,7 @@
_arg1:
.float 2.0
+ .float -2.0
_arg2:
.float 1.0
@@ -45,6 +46,43 @@ _expected:
feq.s a4,fa3,fa2
bne a4,a3,test_fail
+ # Test fsgnjn.s (fneg.s) instruction.
+ flw fa0,0(a0)
+ flw fa1,0(a1)
+ flw fa2,4(a2)
+ fsgnjn.s fa3,fa0,fa1
+ feq.s a4,fa3,fa2
+ bne a4,a3,test_fail
+ flw fa1,4(a1)
+ flw fa2,0(a2)
+ fsgnjn.s fa3,fa0,fa1
+ feq.s a4,fa3,fa2
+ bne a4,a3,test_fail
+ flw fa0,0(a0)
+ flw fa2,4(a2)
+ fneg.s fa3,fa0
+ feq.s a4,fa3,fa2
+ bne a4,a3,test_fail
+
+ # Test fsgnjx.s (fabs.s) instruction.
+ flw fa0,0(a0)
+ flw fa1,4(a1)
+ flw fa2,4(a2)
+ fsgnjx.s fa3,fa0,fa1
+ feq.s a4,fa3,fa2
+ bne a4,a3,test_fail
+ flw fa0,4(a0)
+ flw fa1,4(a1)
+ flw fa2,0(a2)
+ fsgnjx.s fa3,fa0,fa1
+ feq.s a4,fa3,fa2
+ bne a4,a3,test_fail
+ flw fa0,4(a0)
+ flw fa2,0(a2)
+ fabs.s fa3,fa0
+ feq.s a4,fa3,fa2
+ bne a4,a3,test_fail
+
test_pass:
pass
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 03/11] sim: riscv: Add floating-point CSR instructions
2024-02-26 14:22 [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions bhushan.attarde
2024-02-26 14:22 ` [PATCH 01/11] sim: riscv: Add single precision floating-point load-store, move, compare and classify instructions bhushan.attarde
2024-02-26 14:22 ` [PATCH 02/11] sim: riscv: Add single precision floating-point sign injection, min and max instructions bhushan.attarde
@ 2024-02-26 14:22 ` bhushan.attarde
2024-03-06 11:07 ` [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions Bhushan Attarde
2024-03-06 13:24 ` Andrew Burgess
4 siblings, 0 replies; 6+ messages in thread
From: bhushan.attarde @ 2024-02-26 14:22 UTC (permalink / raw)
To: gdb-patches; +Cc: aburgess, vapier, Jaydeep.Patil, Bhushan Attarde
From: Bhushan Attarde <bhushan.attarde@imgtec.com>
Added simulation of following single precision floating-point instructions
frcsr, fscsr, frrm, fsrm, fsrmi, frflags, fsflags and fsflagsi.
Added test file sim/testsuite/riscv/f-csr.s to test these instructions.
---
sim/riscv/sim-main.c | 64 +++++++++++++++++++++++++++++++++++++
sim/testsuite/riscv/f-csr.s | 56 ++++++++++++++++++++++++++++++++
2 files changed, 120 insertions(+)
create mode 100644 sim/testsuite/riscv/f-csr.s
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 9c132d9a448..0e873895f76 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -599,6 +599,21 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
riscv_cpu->regs[rs1]); \
break;
#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+ }
+ break;
+ case MATCH_CSRRWI:
+ TRACE_INSN (cpu, "csrrwi");
+ switch (csr)
+ {
+#define DECLARE_CSR(name, num, ...) \
+ case num: \
+ store_rd (cpu, rd, \
+ fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \
+ store_csr (cpu, #name, num, &riscv_cpu->csr.name, \
+ rs1); \
+ break;
+#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
break;
@@ -949,6 +964,54 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
case MATCH_FMAX_S:
float32_math (cpu, rd, rs1, rs2, FMAX);
break;
+ case MATCH_FRCSR:
+ TRACE_INSN (cpu, "frcsr %s;", rd_name);
+ store_rd (cpu, rd, riscv_cpu->csr.fcsr);
+ break;
+ case MATCH_FSCSR:
+ TRACE_INSN (cpu, "fscsr %s, %s;", rd_name, rs1_name);
+ store_rd (cpu, rd, riscv_cpu->csr.fcsr);
+ riscv_cpu->csr.fcsr = riscv_cpu->regs[rs1] & 0xff;
+ riscv_cpu->csr.frm = (riscv_cpu->regs[rs1] >> 5) & 0x7;
+ riscv_cpu->csr.fflags = riscv_cpu->regs[rs1] & 0x1f;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->regs[rs1]);
+ break;
+ case MATCH_FRRM:
+ TRACE_INSN (cpu, "frrm %s;", rd_name);
+ store_rd (cpu, rd, riscv_cpu->csr.frm);
+ break;
+ case MATCH_FSRM:
+ TRACE_INSN (cpu, "fsrm %s, %s;", rd_name, rs1_name);
+ store_rd (cpu, rd, riscv_cpu->csr.frm);
+ riscv_cpu->csr.frm = riscv_cpu->regs[rs1] & 0x7;
+ riscv_cpu->csr.fcsr |= (riscv_cpu->regs[rs1] & 0x7) << 5;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->csr.fcsr);
+ break;
+ case MATCH_FSRMI:
+ TRACE_INSN (cpu, "fsrmi %s, %x;", rd_name, rs1);
+ store_rd (cpu, rd, riscv_cpu->csr.frm);
+ riscv_cpu->csr.frm = rs1 & 0x7;
+ riscv_cpu->csr.fcsr |= (rs1 & 0x7) << 5;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->csr.fcsr);
+ break;
+ case MATCH_FRFLAGS:
+ TRACE_INSN (cpu, "frflags %s;", rd_name);
+ store_rd (cpu, rd, riscv_cpu->csr.fflags);
+ break;
+ case MATCH_FSFLAGS:
+ TRACE_INSN (cpu, "fsflags %s, %s;", rd_name, rs1_name);
+ store_rd (cpu, rd, riscv_cpu->csr.fflags);
+ riscv_cpu->csr.fflags = riscv_cpu->regs[rs1] & 0x1f;
+ riscv_cpu->csr.fcsr |= riscv_cpu->regs[rs1] & 0x1f;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->csr.fcsr);
+ break;
+ case MATCH_FSFLAGSI:
+ TRACE_INSN (cpu, "fsflagsi %s, %x;", rd_name, rs1);
+ store_rd (cpu, rd, riscv_cpu->csr.fflags);
+ riscv_cpu->csr.fflags = rs1 & 0x1f;
+ riscv_cpu->csr.fcsr |= rs1 & 0x1f;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->csr.fcsr);
+ break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
@@ -1592,6 +1655,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
case INSN_CLASS_F_INX:
return execute_f (cpu, iw, op);
case INSN_CLASS_I:
+ case INSN_CLASS_ZICSR:
return execute_i (cpu, iw, op);
case INSN_CLASS_M:
case INSN_CLASS_ZMMUL:
diff --git a/sim/testsuite/riscv/f-csr.s b/sim/testsuite/riscv/f-csr.s
new file mode 100644
index 00000000000..c8f930b0d86
--- /dev/null
+++ b/sim/testsuite/riscv/f-csr.s
@@ -0,0 +1,56 @@
+# Floating-point CSR instructions tests
+# mach: riscv32 riscv64
+# sim(riscv32): --model RV32IF
+# sim(riscv64): --model RV64ID
+# ld(riscv32): -m elf32lriscv
+# ld(riscv64): -m elf64lriscv
+# as(riscv32): -march=rv32if
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+ start
+ # Test fscsr and frcsr instruction.
+ li a4,0x44 # mode:RDN, exception flags:OF
+ fscsr a5,a4
+ frcsr a6
+ bne a4,a6,test_fail
+
+ # Test rounding mode and flags read instruction.
+ li a4,0x2 # mode:RDN
+ frrm a5
+ bne a4,a5,test_fail
+ frflags a5
+ li a6,0x4 # exception flags:OF
+ bne a6,a5,test_fail
+
+ # Test swap rounding mode instruction.
+ li a6,0x7 # mode:Dynamic
+ fsrm a5,a6
+ bne a4,a5,test_fail # earlier mode should be RDN
+ frrm a5
+ bne a6,a5,test_fail # new mode should be Dynamic
+
+ # Test swap rounding mode with immediate value instruction.
+ fsrmi a5,0x2 # set new mode RDN (0x2)
+ frrm a5 # read the mode
+ li a6,0x2
+ bne a6,a5,test_fail # should be RDN (0x2)
+
+ # Test swap exception flags instruction.
+ li a6,0x8 # flag:Divide by zero
+ fsflags a5,a6
+ frflags a5
+ bne a5,a6,test_fail
+
+ # Test swap exception flags with immediate value instruction.
+ fsflagsi a5,0x2 # set new flag to underflow (0x2)
+ frflags a5 # read the flag
+ li a6,0x2
+ bne a5,a6,test_fail # should be underflow (0x2)
+
+test_pass:
+ pass
+
+test_fail:
+ fail
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread* RE: [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions
2024-02-26 14:22 [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions bhushan.attarde
` (2 preceding siblings ...)
2024-02-26 14:22 ` [PATCH 03/11] sim: riscv: Add floating-point CSR instructions bhushan.attarde
@ 2024-03-06 11:07 ` Bhushan Attarde
2024-03-06 13:24 ` Andrew Burgess
4 siblings, 0 replies; 6+ messages in thread
From: Bhushan Attarde @ 2024-03-06 11:07 UTC (permalink / raw)
To: gdb-patches; +Cc: aburgess, vapier, Jaydeep Patil
Hi Andrew/Mike,
Could you please find some time to review this patch?
Thank you,
Bhushan
-----Original Message-----
From: Bhushan Attarde <Bhushan.Attarde@imgtec.com>
Sent: Monday, February 26, 2024 7:52 PM
To: gdb-patches@sourceware.org
Cc: aburgess@redhat.com; vapier@gentoo.org; Jaydeep Patil <Jaydeep.Patil@imgtec.com>; Bhushan Attarde <Bhushan.Attarde@imgtec.com>
Subject: [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions
*** NOTE: This is an internal email from Imagination Technologies ***
From: Bhushan Attarde <bhushan.attarde@imgtec.com>
Hi All,
This patch series (total 11 patches) adds simulation of riscv single and double precision floating point instructions. This includes load-store, move, compare, classify, sign injection, min, max, MAC, conversion and basic arithmetic instructions. Each patch also includes tests for the corresponding instructions.
The tool-chain sources used are from:
https://github.com/riscv-collab/riscv-gnu-toolchain.git
And gdb sources are replaced with latest upstream sources from:
https://sourceware.org/git/binutils-gdb.git
GDB is configured with --target=riscv64-unknown-elf option.
Contributions from:
Bhushan Attarde (Bhushan.Attarde@imgtec.com)
Jaydeep Patil (Jaydeep.Patil@imgtec.com)
Bhushan Attarde (11):
sim: riscv: Add single precision floating-point load-store, move,
compare and classify instructions
sim: riscv: Add single precision floating-point sign injection, min
and max instructions
sim: riscv: Add floating-point CSR instructions
sim: riscv: Add single precision floating-point MAC instructions
sim: riscv: Add single precision floating-point basic arithmetic
instructions
sim: riscv: Add single-precision floating-point conversion
instructions
sim: riscv: Add double precision floating-point load-store, move,
compare and classify instructions
sim: riscv: Add double precision floating-point sign-injection, min
and max instructions
sim: riscv: Add double precision floating-point MAC instructions
sim: riscv: Add double precision floating-point basic arithmetic
instructions
sim: riscv: Add double precision floating-point conversion
instructions
sim/riscv/model_list.def | 4 +
sim/riscv/sim-main.c | 1544 ++++++++++++++++++++++++
sim/testsuite/riscv/d-basic-arith.s | 128 ++
sim/testsuite/riscv/d-conversion.s | 111 ++
sim/testsuite/riscv/d-fp-compare.s | 94 ++
sim/testsuite/riscv/d-fp-load-store.s | 58 +
sim/testsuite/riscv/d-fp-sign-inject.s | 87 ++
sim/testsuite/riscv/f-csr.s | 56 +
sim/testsuite/riscv/s-basic-arith.s | 131 ++
sim/testsuite/riscv/s-conversion-l.s | 60 +
sim/testsuite/riscv/s-conversion.s | 61 +
sim/testsuite/riscv/s-fp-compare.s | 97 ++
sim/testsuite/riscv/s-fp-load-store.s | 62 +
sim/testsuite/riscv/s-fp-sign-inject.s | 90 ++
14 files changed, 2583 insertions(+)
create mode 100644 sim/testsuite/riscv/d-basic-arith.s
create mode 100755 sim/testsuite/riscv/d-conversion.s
create mode 100755 sim/testsuite/riscv/d-fp-compare.s
create mode 100755 sim/testsuite/riscv/d-fp-load-store.s
create mode 100644 sim/testsuite/riscv/d-fp-sign-inject.s
create mode 100644 sim/testsuite/riscv/f-csr.s create mode 100644 sim/testsuite/riscv/s-basic-arith.s
create mode 100644 sim/testsuite/riscv/s-conversion-l.s
create mode 100644 sim/testsuite/riscv/s-conversion.s
create mode 100644 sim/testsuite/riscv/s-fp-compare.s
create mode 100644 sim/testsuite/riscv/s-fp-load-store.s
create mode 100644 sim/testsuite/riscv/s-fp-sign-inject.s
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions
2024-02-26 14:22 [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions bhushan.attarde
` (3 preceding siblings ...)
2024-03-06 11:07 ` [PATCH 00/11] sim: riscv: simulation of single and double precision floating point instructions Bhushan Attarde
@ 2024-03-06 13:24 ` Andrew Burgess
4 siblings, 0 replies; 6+ messages in thread
From: Andrew Burgess @ 2024-03-06 13:24 UTC (permalink / raw)
To: bhushan.attarde, gdb-patches; +Cc: vapier, Jaydeep.Patil, Bhushan Attarde
<bhushan.attarde@imgtec.com> writes:
> From: Bhushan Attarde <bhushan.attarde@imgtec.com>
>
> Hi All,
>
> This patch series (total 11 patches) adds simulation of riscv single
> and double
I think something went wrong with the threading when you sent these
emails, patches 1->3 are threaded together, then the other emails are
split into two separate thread blocks:
https://inbox.sourceware.org/gdb-patches/20240226142234.1628932-1-bhushan.attarde@imgtec.com/
https://inbox.sourceware.org/gdb-patches/20240226142628.1629048-1-bhushan.attarde@imgtec.com/
https://inbox.sourceware.org/gdb-patches/20240226142845.1629113-1-bhushan.attarde@imgtec.com/
Could you repost them please with the threading fixed, this makes it far
easier to apply the complete series, plus keeps all the reviews within a
single thread.
Thanks,
Andrew
> precision floating point instructions. This includes load-store, move, compare,
> classify, sign injection, min, max, MAC, conversion and basic arithmetic
> instructions. Each patch also includes tests for the corresponding instructions.
>
> The tool-chain sources used are from:
> https://github.com/riscv-collab/riscv-gnu-toolchain.git
>
> And gdb sources are replaced with latest upstream sources from:
> https://sourceware.org/git/binutils-gdb.git
>
> GDB is configured with --target=riscv64-unknown-elf option.
>
> Contributions from:
> Bhushan Attarde (Bhushan.Attarde@imgtec.com)
> Jaydeep Patil (Jaydeep.Patil@imgtec.com)
>
> Bhushan Attarde (11):
> sim: riscv: Add single precision floating-point load-store, move,
> compare and classify instructions
> sim: riscv: Add single precision floating-point sign injection, min
> and max instructions
> sim: riscv: Add floating-point CSR instructions
> sim: riscv: Add single precision floating-point MAC instructions
> sim: riscv: Add single precision floating-point basic arithmetic
> instructions
> sim: riscv: Add single-precision floating-point conversion
> instructions
> sim: riscv: Add double precision floating-point load-store, move,
> compare and classify instructions
> sim: riscv: Add double precision floating-point sign-injection, min
> and max instructions
> sim: riscv: Add double precision floating-point MAC instructions
> sim: riscv: Add double precision floating-point basic arithmetic
> instructions
> sim: riscv: Add double precision floating-point conversion
> instructions
>
> sim/riscv/model_list.def | 4 +
> sim/riscv/sim-main.c | 1544 ++++++++++++++++++++++++
> sim/testsuite/riscv/d-basic-arith.s | 128 ++
> sim/testsuite/riscv/d-conversion.s | 111 ++
> sim/testsuite/riscv/d-fp-compare.s | 94 ++
> sim/testsuite/riscv/d-fp-load-store.s | 58 +
> sim/testsuite/riscv/d-fp-sign-inject.s | 87 ++
> sim/testsuite/riscv/f-csr.s | 56 +
> sim/testsuite/riscv/s-basic-arith.s | 131 ++
> sim/testsuite/riscv/s-conversion-l.s | 60 +
> sim/testsuite/riscv/s-conversion.s | 61 +
> sim/testsuite/riscv/s-fp-compare.s | 97 ++
> sim/testsuite/riscv/s-fp-load-store.s | 62 +
> sim/testsuite/riscv/s-fp-sign-inject.s | 90 ++
> 14 files changed, 2583 insertions(+)
> create mode 100644 sim/testsuite/riscv/d-basic-arith.s
> create mode 100755 sim/testsuite/riscv/d-conversion.s
> create mode 100755 sim/testsuite/riscv/d-fp-compare.s
> create mode 100755 sim/testsuite/riscv/d-fp-load-store.s
> create mode 100644 sim/testsuite/riscv/d-fp-sign-inject.s
> create mode 100644 sim/testsuite/riscv/f-csr.s
> create mode 100644 sim/testsuite/riscv/s-basic-arith.s
> create mode 100644 sim/testsuite/riscv/s-conversion-l.s
> create mode 100644 sim/testsuite/riscv/s-conversion.s
> create mode 100644 sim/testsuite/riscv/s-fp-compare.s
> create mode 100644 sim/testsuite/riscv/s-fp-load-store.s
> create mode 100644 sim/testsuite/riscv/s-fp-sign-inject.s
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread