From: <bhushan.attarde@imgtec.com>
To: <gdb-patches@sourceware.org>
Cc: <aburgess@redhat.com>, <vapier@gentoo.org>,
<Jaydeep.Patil@imgtec.com>,
Bhushan Attarde <bhushan.attarde@imgtec.com>
Subject: [PATCH 09/11] sim: riscv: Add double precision floating-point MAC instructions
Date: Mon, 26 Feb 2024 14:28:43 +0000 [thread overview]
Message-ID: <20240226142845.1629113-1-bhushan.attarde@imgtec.com> (raw)
From: Bhushan Attarde <bhushan.attarde@imgtec.com>
Added simulation of following single precision floating-point instructions
fmadd.d, fnmadd.d, fmsub.d and fnmsub.d.
Added test file sim/testsuite/riscv/d-basic-arith.s to test these instructions.
---
sim/riscv/sim-main.c | 117 ++++++++++++++++++++++++++--
sim/testsuite/riscv/d-basic-arith.s | 78 +++++++++++++++++++
2 files changed, 190 insertions(+), 5 deletions(-)
create mode 100644 sim/testsuite/riscv/d-basic-arith.s
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 4f347fbfc5e..4a102df74e0 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1361,20 +1361,36 @@ float64_compare (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
/* Handle double precision floating point math instructions. */
static void
-float64_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
+float64_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int rs3, int rm,
+ int flags)
{
struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
- double a, b, result = 0;
- uint64_t rs1_bits, rs2_bits, rd_bits;
+ double a, b, c, result = 0;
+ int old_rm, old_except, new_except;
+ uint64_t rs1_bits, rs2_bits, rs3_bits, rd_bits;
const char *frd_name = riscv_fpr_names_abi[rd];
const char *frs1_name = riscv_fpr_names_abi[rs1];
const char *frs2_name = riscv_fpr_names_abi[rs2];
+ const char *frs3_name = riscv_fpr_names_abi[rs3];
+
+ if (rm == DYN)
+ rm = riscv_cpu->csr.frm;
+
+ old_rm = set_riscv_rounding_mode (rm);
+ old_except = fetestexcept (FE_ALL_EXCEPT);
rs1_bits = (uint64_t) riscv_cpu->fpregs[rs1];
memcpy (&a, &rs1_bits, sizeof (a));
rs2_bits = (uint64_t) riscv_cpu->fpregs[rs2];
memcpy (&b, &rs2_bits, sizeof (b));
+ if (flags == FMADD || flags == FNMADD
+ || flags == FMSUB || flags == FNMSUB)
+ {
+ rs3_bits = (uint64_t) riscv_cpu->fpregs[rs3];
+ memcpy (&c, &rs3_bits, sizeof (c));
+ }
+
switch (flags)
{
case FMAX:
@@ -1385,12 +1401,85 @@ float64_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
TRACE_INSN (cpu, "fmin.d %s, %s, %s;", frd_name, frs1_name, frs2_name);
result = fmin (a, b);
break;
+ case FMADD:
+ TRACE_INSN (cpu, "fmadd.d %s, %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, frs3_name, rm);
+ result = (a * b) + c;
+ break;
+ case FNMADD:
+ TRACE_INSN (cpu, "fnmadd.d %s, %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, frs3_name, rm);
+ result = -((a * b) - c);
+ break;
+ case FMSUB:
+ TRACE_INSN (cpu, "fmsub.d %s, %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, frs3_name, rm);
+ result = (a * b) - c;
+ break;
+ case FNMSUB:
+ TRACE_INSN (cpu, "fnmsub.d %s, %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, frs3_name, rm);
+ result = -((a * b) + c);
+ break;
+ }
+
+ if (rm == RMM)
+ {
+ if (is_float_halfway (result))
+ {
+ if (result > 0)
+ result = nextafterf (result, INFINITY);
+ else
+ result = nextafterf (result, -INFINITY);
+ }
}
/* Store result. */
memcpy (&rd_bits, &result, sizeof (result));
store_fp (cpu, rd, rd_bits);
+ /* Restore rounding mode. */
+ fesetround (old_rm);
+
+ /* Set exception. */
+ new_except = fetestexcept (FE_ALL_EXCEPT);
+
+ if (old_except != new_except)
+ {
+ if (new_except & FE_OVERFLOW)
+ {
+ riscv_cpu->csr.fcsr |= FCSR_OF;
+ riscv_cpu->csr.fflags |= FCSR_OF;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr |= OF");
+ }
+ else if (new_except & FE_UNDERFLOW)
+ {
+ riscv_cpu->csr.fcsr |= FCSR_UF;
+ riscv_cpu->csr.fflags |= FCSR_UF;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr |= UF");
+ }
+ else if (new_except & FE_INEXACT)
+ {
+ riscv_cpu->csr.fcsr |= FCSR_NX;
+ riscv_cpu->csr.fflags |= FCSR_NX;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr |= NX");
+ }
+ else if (new_except & FE_DIVBYZERO)
+ {
+ riscv_cpu->csr.fcsr |= FCSR_DZ;
+ riscv_cpu->csr.fflags |= FCSR_DZ;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr |= DZ");
+ }
+ else if (new_except & FE_INVALID)
+ {
+ riscv_cpu->csr.fcsr |= FCSR_NV;
+ riscv_cpu->csr.fflags |= FCSR_NV;
+ TRACE_REGISTER (cpu, "wrote CSR fcsr |= NV");
+ }
+
+ feclearexcept (FE_ALL_EXCEPT);
+ feraiseexcept (old_except);
+ }
}
/* Simulate single precision floating point instructions. */
@@ -1644,6 +1733,8 @@ execute_d (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
+ int rs3 = (iw >> OP_SH_RS3) & OP_MASK_RS3;
+ int rm = (iw >> OP_SH_RM) & OP_MASK_RM;
const char *frd_name = riscv_fpr_names_abi[rd];
const char *rd_name = riscv_gpr_names_abi[rd];
const char *frs1_name = riscv_fpr_names_abi[rs1];
@@ -1728,10 +1819,26 @@ execute_d (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
break;
}
case MATCH_FMIN_D:
- float64_math (cpu, rd, rs1, rs2, FMIN);
+ float64_math (cpu, rd, rs1, rs2, 0, -1, FMIN);
break;
case MATCH_FMAX_D:
- float64_math (cpu, rd, rs1, rs2, FMAX);
+ float64_math (cpu, rd, rs1, rs2, 0, -1, FMAX);
+ break;
+ case MATCH_FMADD_D:
+ case MATCH_FMADD_D | MASK_RM:
+ float64_math (cpu, rd, rs1, rs2, rs3, rm, FMADD);
+ break;
+ case MATCH_FNMADD_D:
+ case MATCH_FNMADD_D | MASK_RM:
+ float64_math (cpu, rd, rs1, rs2, rs3, rm, FNMADD);
+ break;
+ case MATCH_FMSUB_D:
+ case MATCH_FMSUB_D | MASK_RM:
+ float64_math (cpu, rd, rs1, rs2, rs3, rm, FMSUB);
+ break;
+ case MATCH_FNMSUB_D:
+ case MATCH_FNMSUB_D | MASK_RM:
+ float64_math (cpu, rd, rs1, rs2, rs3, rm, FNMSUB);
break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
diff --git a/sim/testsuite/riscv/d-basic-arith.s b/sim/testsuite/riscv/d-basic-arith.s
new file mode 100644
index 00000000000..996f603e91d
--- /dev/null
+++ b/sim/testsuite/riscv/d-basic-arith.s
@@ -0,0 +1,78 @@
+# Double precision basic arithmetic tests.
+# mach: riscv64
+# sim(riscv64): --model RV64ID
+# ld(riscv64): -m elf64lriscv
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+ .section .data
+ .align 3
+
+_arg1:
+ .double -12.5
+
+_arg2:
+ .double 2.5
+
+_arg3:
+ .double 7.45
+
+_result:
+ .double -23.799999
+ .double 38.7000008
+ .double -38.7000008
+ .double 23.7999992
+
+ start
+ .option push
+ .option norelax
+ la a0,_arg1
+ la a1,_arg2
+ la a2,_arg3
+ la a3,_result
+ li a4,1
+ .option pop
+
+ # Test fmadd instruction.
+ fld fa0,0(a0)
+ fld fa1,0(a1)
+ fld fa2,0(a2)
+ fld fa3,0(a3)
+ fmadd.d fa4,fa0,fa1,fa0,rne
+ feq.d a5,fa4,fa4
+ bne a5,a4,test_fail
+
+ # Test fnmadd instruction.
+ fld fa0,0(a0)
+ fld fa1,0(a1)
+ fld fa2,0(a2)
+ fld fa3,8(a3)
+ fnmadd.d fa4,fa0,fa1,fa0,rne
+ feq.d a5,fa4,fa4
+ bne a5,a4,test_fail
+
+ # Test fmsub instruction.
+ fld fa0,0(a0)
+ fld fa1,0(a1)
+ fld fa2,0(a2)
+ fld fa3,16(a3)
+ fmsub.d fa4,fa0,fa1,fa0,rne
+ feq.d a5,fa4,fa4
+ bne a5,a4,test_fail
+
+ # Test fnmsub instruction.
+ fld fa0,0(a0)
+ fld fa1,0(a1)
+ fld fa2,0(a2)
+ fld fa3,24(a3)
+ fmsub.d fa4,fa0,fa1,fa0,rne
+ feq.d a5,fa4,fa4
+ bne a5,a4,test_fail
+
+
+test_pass:
+ pass
+
+test_fail:
+ fail
--
2.25.1
next reply other threads:[~2024-02-26 14:29 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-26 14:28 bhushan.attarde [this message]
2024-02-26 14:28 ` [PATCH 10/11] sim: riscv: Add double precision floating-point basic arithmetic instructions bhushan.attarde
2024-02-26 14:28 ` [PATCH 11/11] sim: riscv: Add double precision floating-point conversion instructions bhushan.attarde
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