From: <bhushan.attarde@imgtec.com>
To: <gdb-patches@sourceware.org>
Cc: <aburgess@redhat.com>, <vapier@gentoo.org>,
<Jaydeep.Patil@imgtec.com>,
Bhushan Attarde <bhushan.attarde@imgtec.com>
Subject: [PATCH 10/11] sim: riscv: Add double precision floating-point basic arithmetic instructions
Date: Mon, 26 Feb 2024 14:28:44 +0000 [thread overview]
Message-ID: <20240226142845.1629113-2-bhushan.attarde@imgtec.com> (raw)
In-Reply-To: <20240226142845.1629113-1-bhushan.attarde@imgtec.com>
From: Bhushan Attarde <bhushan.attarde@imgtec.com>
Added simulation of following single precision floating-point instructions
fadd.d, fsub.d, fmul.d, fdiv.d and fsqrt.d.
Update test file sim/testsuite/riscv/d-basic-arith.s to test these instructions.
---
sim/riscv/sim-main.c | 45 ++++++++++++++++++++++++++
sim/testsuite/riscv/d-basic-arith.s | 50 +++++++++++++++++++++++++++++
2 files changed, 95 insertions(+)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 4a102df74e0..e715ca2501e 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1421,6 +1421,31 @@ float64_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int rs3, int rm,
frd_name, frs1_name, frs2_name, frs3_name, rm);
result = -((a * b) + c);
break;
+ case FADD:
+ TRACE_INSN (cpu, "fadd.d %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, rm);
+ result = a + b;
+ break;
+ case FSUB:
+ TRACE_INSN (cpu, "fsub.d %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, rm);
+ result = a - b;
+ break;
+ case FMUL:
+ TRACE_INSN (cpu, "fmul.d %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, rm);
+ result = a * b;
+ break;
+ case FDIV:
+ TRACE_INSN (cpu, "fdiv.d %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, rm);
+ result = a / b;
+ break;
+ case FSQRT:
+ TRACE_INSN (cpu, "fsqrt.d %s, %s, rm=%d;",
+ frd_name, frs1_name, rm);
+ result = sqrtf (a);
+ break;
}
if (rm == RMM)
@@ -1840,6 +1865,26 @@ execute_d (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
case MATCH_FNMSUB_D | MASK_RM:
float64_math (cpu, rd, rs1, rs2, rs3, rm, FNMSUB);
break;
+ case MATCH_FADD_D:
+ case MATCH_FADD_D | MASK_RM:
+ float64_math (cpu, rd, rs1, rs2, 0, rm, FADD);
+ break;
+ case MATCH_FSUB_D:
+ case MATCH_FSUB_D | MASK_RM:
+ float64_math (cpu, rd, rs1, rs2, 0, rm, FSUB);
+ break;
+ case MATCH_FMUL_D:
+ case MATCH_FMUL_D | MASK_RM:
+ float64_math (cpu, rd, rs1, rs2, 0, rm, FMUL);
+ break;
+ case MATCH_FDIV_D:
+ case MATCH_FDIV_D | MASK_RM:
+ float64_math (cpu, rd, rs1, rs2, 0, rm, FDIV);
+ break;
+ case MATCH_FSQRT_D:
+ case MATCH_FSQRT_D | MASK_RM:
+ float64_math (cpu, rd, rs1, rs2, 0, rm, FSQRT);
+ break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
diff --git a/sim/testsuite/riscv/d-basic-arith.s b/sim/testsuite/riscv/d-basic-arith.s
index 996f603e91d..2f529c68f47 100644
--- a/sim/testsuite/riscv/d-basic-arith.s
+++ b/sim/testsuite/riscv/d-basic-arith.s
@@ -11,9 +11,16 @@
_arg1:
.double -12.5
+ .double 1.5
+ .double 2.2
+ .double 18.5
+ .double 5.0
_arg2:
.double 2.5
+ .double 0.5
+ .double 1.1
+ .double 0.1
_arg3:
.double 7.45
@@ -23,6 +30,11 @@ _result:
.double 38.7000008
.double -38.7000008
.double 23.7999992
+ .double 2.0
+ .double 1.1
+ .double 1.85
+ .double 185
+ .double 2.2360680103302002
start
.option push
@@ -70,6 +82,44 @@ _result:
feq.d a5,fa4,fa4
bne a5,a4,test_fail
+ # Test fadd instruction.
+ fld fa0,8(a0)
+ fld fa1,8(a1)
+ fld fa2,32(a3)
+ fadd.d fa4,fa0,fa1,rne
+ feq.d a5,fa4,fa2
+ bne a5,a4,test_fail
+
+ # Test fsub instruction.
+ fld fa0,16(a0)
+ fld fa1,16(a1)
+ fld fa2,40(a3)
+ fsub.d fa4,fa0,fa1,rne
+ feq.d a5,fa4,fa2
+ bne a5,a4,test_fail
+
+ # Test fmul instruction.
+ fld fa0,24(a0)
+ fld fa1,24(a1)
+ fld fa2,48(a3)
+ fmul.d fa4,fa0,fa1,rne
+ feq.d a5,fa4,fa2
+ bne a5,a4,test_fail
+
+ # Test fdiv instruction.
+ fld fa0,24(a0) # Use same input values as of fmul
+ fld fa1,24(a1)
+ fld fa2,56(a3)
+ fdiv.d fa4,fa0,fa1,rne
+ feq.d a5,fa4,fa2
+ bne a5,a4,test_fail
+
+ # Test fsqrt instruction.
+ fld fa0,32(a0)
+ fld fa2,64(a3)
+ fsqrt.d fa4,fa0,rne
+ feq.d a5,fa4,fa2
+ bne a5,a4,test_fail
test_pass:
pass
--
2.25.1
next prev parent reply other threads:[~2024-02-26 14:29 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-26 14:28 [PATCH 09/11] sim: riscv: Add double precision floating-point MAC instructions bhushan.attarde
2024-02-26 14:28 ` bhushan.attarde [this message]
2024-02-26 14:28 ` [PATCH 11/11] sim: riscv: Add double precision floating-point conversion instructions bhushan.attarde
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