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From: Simon Marchi <simon.marchi@polymtl.ca>
To: Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com>,
	"gdb-patches@sourceware.org" <gdb-patches@sourceware.org>
Cc: Chao-ying Fu <cfu@wavecomp.com>,
	"Maciej W . Rozycki" <macro@orcam.me.uk>
Subject: Re: [PATCH^2] gdb: mips: Add MIPSR6 support
Date: Thu, 31 Aug 2023 13:56:50 -0400	[thread overview]
Message-ID: <6dc411fa-5e25-44a1-81b4-9454aa424507@polymtl.ca> (raw)
In-Reply-To: <VI1PR03MB42088BEA0E9B10CF8C75EA3AEF229@VI1PR03MB4208.eurprd03.prod.outlook.com>

Hi Dragan,

I can do a superficial review (formatting / coding style / general
feeling), but can't speak about the behavior.  Ideally Maciej would look
at it, but if he's not available, I would be fine approving the patch,
since it's isolated to the MIPS support.  The code looks nice and
well-organized.

Not absolutely necessary, but it would be nice to have tests
(arch-specific tests in assembly in gdb.arch) for stepping and putting
breakpoints on those instructions that you add support for.

See superficial comments below.

Simon

On 10/12/22 14:02, Dragan Mladjenovic wrote:
> @@ -1633,6 +1660,70 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch)
>    return 0;
>  }
>  
> +/* Return true if addition produces 32-bit overflow.  */
> +
> +static bool
> +is_add32bit_overflow (int32_t a, int32_t b)
> +{
> +  int32_t r = (uint32_t) a + (uint32_t) b;
> +  return (a < 0 && b < 0 && r >= 0) || (a >= 0 && b >= 0 && r < 0);
> +}
> +
> +/* Return true if addition produces 32-bit overflow or
> +   one of the inputs is not sign-extended 32-bit value.  */
> +
> +static bool
> +is_add64bit_overflow (int64_t a, int64_t b)
> +{
> +  if (a != (int32_t) a)
> +    return 1;
> +  if (b != (int32_t) b)
> +    return 1;

return true

> @@ -1704,7 +1801,119 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
>  	  else
>  	    pc += 8;        /* After the delay slot.  */
>  	}
> +      else if (is_mipsr6_isa (gdbarch))
> +	{
> +	  /* BOVC, BEQZALC, BEQC and BNVC, BNEZALC, BNEC */
> +	  if (op == 8 || op == 24)
> +	    {
> +	      int rs = rtype_rs (inst);
> +	      int rt = rtype_rt (inst);
> +	      LONGEST val_rs = regcache_raw_get_signed (regcache, rs);
> +	      LONGEST val_rt = regcache_raw_get_signed (regcache, rt);
> +	      bool taken = false;
> +	      /* BOVC (BNVC) */
> +	      if (rs >= rt)
> +		{
> +		  if (mips64bitreg)
> +		    taken = is_add64bit_overflow (val_rs, val_rt);
> +		  else
> +		    taken = is_add32bit_overflow (val_rs, val_rt);
> +		}
> +	      else if (rs < rt && rs == 0)
> +	      /* BEQZALC (BNEZALC) */
> +		taken = (val_rt == 0);

Because of the comment, you would need to add braces here.

Ref: https://sourceware.org/gdb/wiki/Internals%20GDB-C-Coding-Standards#Whitespaces

So we would typically write:

  else if (rs < rt && rs == 0)
    {
      /* BEQZALC (BNEZALC) */
      taken = (val_rt == 0);
    }

But I realize this may clash with the existing style used in the file,
which deviates a bit from the rest of GDB.  So I'm also fine with
leaving it like that on the account of following surrounding style.

> @@ -2448,6 +2659,72 @@ micromips_instruction_is_compact_branch (unsigned short insn)
>      }
>  }
>  
> +/* Return non-zero if the MIPS instruction INSN is a compact branch
> +   or jump.  A value of 1 indicates an unconditional compact branch
> +   and a value of 2 indicates a conditional compact branch.  */
> +
> +static int
> +mips32_instruction_is_compact_branch (struct gdbarch *gdbarch, ULONGEST insn)

Instead of hardcoded integer values, can you change this function to
make it return an enum?

Simon

  parent reply	other threads:[~2023-08-31 17:57 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-12 18:02 Dragan Mladjenovic
2023-08-01 12:12 ` Dragan Mladjenovic
2023-08-31  9:50   ` Dragan Mladjenovic
2023-08-31 17:56 ` Simon Marchi [this message]
2023-08-31 21:36   ` Maciej W. Rozycki
2023-09-01 15:14     ` Simon Marchi
2023-09-04 21:34       ` Maciej W. Rozycki

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