Re: Fwd: [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers

[Andrew Burgess <aburgess@redhat.com>]

Nelson Chu <nelson@rivosinc.com> writes:

> Forward to gdb mailing list and cc Andrew since it seems under the gdb folder.
>
> Thanks
> Nelson
>
> ---------- Forwarded message ---------
> From: Xiao Zeng <zengxiao@eswincomputing.com>
> Date: Tue, Dec 6, 2022 at 1:39 PM
> Subject: [PATCH] RISC-V: Correction of machine registers mapping to
> dwarf registers
> To: <binutils@sourceware.org>
> Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>,
> <nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com>
>
>
> According to the riscv psabi, the mapping relationship between the
> dwarf registers and the machine registers are as follows:
>
> DWARF Number | Register Name | Description
> 0 - 31       | x0 - x31      | Integer Registers
> 32 - 63      | f0 - f31      | Floating-point Registers
>
>         * gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping
>         boundary register.

Thanks for catching this.  I went ahead and merged this patch.

Thanks,
Andrew

> ---
>  gdb/riscv-tdep.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index 0a050b272ff..a298623b449 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch)
>  static int
>  riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
>  {
> -  if (reg < RISCV_DWARF_REGNUM_X31)
> +  if (reg <= RISCV_DWARF_REGNUM_X31)
>      return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0);
>
> -  else if (reg < RISCV_DWARF_REGNUM_F31)
> +  else if (reg <= RISCV_DWARF_REGNUM_F31)
>      return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
>
>    else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR)
> --
> 2.34.1