From: Andrew Burgess <aburgess@redhat.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: Tsukasa OI <research_trasio@irq.a4lg.com>, gdb-patches@sourceware.org
Subject: Re: [PATCH 2/2] RISC-V: Reflect actual range of vlen for hashing
Date: Fri, 11 Aug 2023 13:49:21 +0100 [thread overview]
Message-ID: <87sf8pd9ri.fsf@redhat.com> (raw)
In-Reply-To: <bd89cc22628f42b4bec9de41b266e636b5f4b989.1691745446.git.research_trasio@irq.a4lg.com>
Tsukasa OI <research_trasio@irq.a4lg.com> writes:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> Before actual xlen handling, it fixes the hashing function based on the
> actual valid range of xlen (xlen == 0 or 4 <= xlen <= 65536 / 8).
Please reword the commit message as:
Before actual vlen handling, fix the riscv_gdbarch_features hashing
function based on the actual valid range of vlen. In bytes, vlen is 0,
or 4 <= xlen <= 8192.
With that done, this commit (2/2) is:
Approved-By: Andrew Burgess <aburgess@redhat.com>
Thanks,
Andrew
> To reflect all those values, extra 2 bits should be hashed.
> ---
> gdb/arch/riscv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
> index d5ea1a55b214..e1965da69ebb 100644
> --- a/gdb/arch/riscv.h
> +++ b/gdb/arch/riscv.h
> @@ -90,7 +90,7 @@ struct riscv_gdbarch_features
> | (has_fcsr_reg ? 1 : 0) << 13
> | (xlen & 0x1f) << 5
> | (flen & 0x1f) << 0
> - | (vlen & 0xfff) << 14);
> + | (vlen & 0x3fff) << 14);
> return val;
> }
> };
> --
> 2.41.0
next prev parent reply other threads:[~2023-08-11 12:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-11 9:17 [PATCH 1/2] RISC-V: Add reference to Zve32* Tsukasa OI
2023-08-11 9:17 ` [PATCH 2/2] RISC-V: Reflect actual range of vlen for hashing Tsukasa OI
2023-08-11 12:49 ` Andrew Burgess [this message]
2023-08-11 13:34 ` Tsukasa OI
2023-08-11 12:40 ` [PATCH 1/2] RISC-V: Add reference to Zve32* Andrew Burgess
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