* sim regen
@ 2023-08-14 13:39 Alan Modra
2023-08-18 16:40 ` Tom Tromey
0 siblings, 1 reply; 5+ messages in thread
From: Alan Modra @ 2023-08-14 13:39 UTC (permalink / raw)
To: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 11137 bytes --]
The attached patch regenerates sim files.
Tested with the following tools from a recent binutils build in
sim-site-config.exp, plus a few cross compilers.
set AS_FOR_TARGET_AARCH64 "/home/alan/build/gas/aarch64-linux-gnu/gas/as-new"
set LD_FOR_TARGET_AARCH64 "/home/alan/build/gas/aarch64-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_AARCH64 "aarch64-linux-gnu-gcc"
set AS_FOR_TARGET_ARM "/home/alan/build/gas/arm-linux-gnueabi/gas/as-new"
set LD_FOR_TARGET_ARM "/home/alan/build/gas/arm-linux-gnueabi/ld/ld-new"
set CC_FOR_TARGET_ARM "arm-linux-gnueabi-gcc"
set AS_FOR_TARGET_AVR "/home/alan/build/gas/avr-elf/gas/as-new"
set LD_FOR_TARGET_AVR "/home/alan/build/gas/avr-elf/ld/ld-new"
set CC_FOR_TARGET_AVR ""
set AS_FOR_TARGET_BFIN "/home/alan/build/gas/bfin-elf/gas/as-new"
set LD_FOR_TARGET_BFIN "/home/alan/build/gas/bfin-elf/ld/ld-new"
set CC_FOR_TARGET_BFIN ""
set AS_FOR_TARGET_BPF "/home/alan/build/gas/bpf-none/gas/as-new"
set LD_FOR_TARGET_BPF "/home/alan/build/gas/bpf-none/ld/ld-new"
set CC_FOR_TARGET_BPF ""
set AS_FOR_TARGET_CR16 "/home/alan/build/gas/cr16-elf/gas/as-new"
set LD_FOR_TARGET_CR16 "/home/alan/build/gas/cr16-elf/ld/ld-new"
set CC_FOR_TARGET_CR16 ""
set AS_FOR_TARGET_CRIS "/home/alan/build/gas/cris-elf/gas/as-new"
set LD_FOR_TARGET_CRIS "/home/alan/build/gas/cris-elf/ld/ld-new"
set CC_FOR_TARGET_CRIS ""
set AS_FOR_TARGET_D10V "/home/alan/build/gas/d10v-elf/gas/as-new"
set LD_FOR_TARGET_D10V "/home/alan/build/gas/d10v-elf/ld/ld-new"
set CC_FOR_TARGET_D10V ""
set AS_FOR_TARGET_FRV "/home/alan/build/gas/frv-elf/gas/as-new"
set LD_FOR_TARGET_FRV "/home/alan/build/gas/frv-elf/ld/ld-new"
set CC_FOR_TARGET_FRV ""
set AS_FOR_TARGET_FT32 "/home/alan/build/gas/ft32-elf/gas/as-new"
set LD_FOR_TARGET_FT32 "/home/alan/build/gas/ft32-elf/ld/ld-new"
set CC_FOR_TARGET_FT32 ""
set AS_FOR_TARGET_H8300 "/home/alan/build/gas/h8300-elf/gas/as-new"
set LD_FOR_TARGET_H8300 "/home/alan/build/gas/h8300-elf/ld/ld-new"
set CC_FOR_TARGET_H8300 ""
set AS_FOR_TARGET_IQ2000 "/home/alan/build/gas/iq2000-elf/gas/as-new"
set LD_FOR_TARGET_IQ2000 "/home/alan/build/gas/iq2000-elf/ld/ld-new"
set CC_FOR_TARGET_IQ2000 ""
set AS_FOR_TARGET_LM32 "/home/alan/build/gas/lm32-linux-gnu/gas/as-new"
set LD_FOR_TARGET_LM32 "/home/alan/build/gas/lm32-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_LM32 ""
set AS_FOR_TARGET_M32C "/home/alan/build/gas/m32c-elf/gas/as-new"
set LD_FOR_TARGET_M32C "/home/alan/build/gas/m32c-elf/ld/ld-new"
set CC_FOR_TARGET_M32C ""
set AS_FOR_TARGET_M32R "/home/alan/build/gas/m32r-elf/gas/as-new"
set LD_FOR_TARGET_M32R "/home/alan/build/gas/m32r-elf/ld/ld-new"
set CC_FOR_TARGET_M32R ""
set AS_FOR_TARGET_M68HC11 "/home/alan/build/gas/m68hc11-elf/gas/as-new"
set LD_FOR_TARGET_M68HC11 "/home/alan/build/gas/m68hc11-elf/ld/ld-new"
set CC_FOR_TARGET_M68HC11 ""
set AS_FOR_TARGET_MCORE "/home/alan/build/gas/mcore-elf/gas/as-new"
set LD_FOR_TARGET_MCORE "/home/alan/build/gas/mcore-elf/ld/ld-new"
set CC_FOR_TARGET_MCORE ""
set AS_FOR_TARGET_MICROBLAZE "/home/alan/build/gas/microblaze-linux-gnu/gas/as-new"
set LD_FOR_TARGET_MICROBLAZE "/home/alan/build/gas/microblaze-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_MICROBLAZE "microblaze-linux-gnu-gcc"
set AS_FOR_TARGET_MIPS "/home/alan/build/gas/mips-linux-gnu/gas/as-new"
set LD_FOR_TARGET_MIPS "/home/alan/build/gas/mips-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_MIPS "mips-linux-gnu-gcc"
set AS_FOR_TARGET_MN10300 "/home/alan/build/gas/mn10300-elf/gas/as-new"
set LD_FOR_TARGET_MN10300 "/home/alan/build/gas/mn10300-elf/ld/ld-new"
set CC_FOR_TARGET_MN10300 ""
set AS_FOR_TARGET_MOXIE "/home/alan/build/gas/moxie-elf/gas/as-new"
set LD_FOR_TARGET_MOXIE "/home/alan/build/gas/moxie-elf/ld/ld-new"
set CC_FOR_TARGET_MOXIE ""
set AS_FOR_TARGET_MSP430 "/home/alan/build/gas/msp430-elf/gas/as-new"
set LD_FOR_TARGET_MSP430 "/home/alan/build/gas/msp430-elf/ld/ld-new"
set CC_FOR_TARGET_MSP430 ""
set AS_FOR_TARGET_OR1K "/home/alan/build/gas/or1k-linux-gnu/gas/as-new"
set LD_FOR_TARGET_OR1K "/home/alan/build/gas/or1k-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_OR1K ""
set AS_FOR_TARGET_PPC "/home/alan/build/gas/powerpc-linux-gnu/gas/as-new"
set LD_FOR_TARGET_PPC "/home/alan/build/gas/powerpc-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_PPC "powerpc-linux-gnu-gcc"
set AS_FOR_TARGET_PRU "/home/alan/build/gas/pru-elf/gas/as-new"
set LD_FOR_TARGET_PRU "/home/alan/build/gas/pru-elf/ld/ld-new"
set CC_FOR_TARGET_PRU ""
set AS_FOR_TARGET_RISCV "/home/alan/build/gas/riscv32-elf/gas/as-new"
set LD_FOR_TARGET_RISCV "/home/alan/build/gas/riscv32-elf/ld/ld-new"
set CC_FOR_TARGET_RISCV ""
set AS_FOR_TARGET_RL78 "/home/alan/build/gas/rl78-elf/gas/as-new"
set LD_FOR_TARGET_RL78 "/home/alan/build/gas/rl78-elf/ld/ld-new"
set CC_FOR_TARGET_RL78 ""
set AS_FOR_TARGET_RX "/home/alan/build/gas/rx-elf/gas/as-new"
set LD_FOR_TARGET_RX "/home/alan/build/gas/rx-elf/ld/ld-new"
set CC_FOR_TARGET_RX ""
set AS_FOR_TARGET_SH "/home/alan/build/gas/sh-rtems/gas/as-new"
set LD_FOR_TARGET_SH "/home/alan/build/gas/sh-rtems/ld/ld-new"
set CC_FOR_TARGET_SH ""
set AS_FOR_TARGET_ERC32 ""
set LD_FOR_TARGET_ERC32 ""
set CC_FOR_TARGET_ERC32 ""
set AS_FOR_TARGET_V850 "/home/alan/build/gas/v850-elf/gas/as-new"
set LD_FOR_TARGET_V850 "/home/alan/build/gas/v850-elf/ld/ld-new"
set CC_FOR_TARGET_V850 ""
Results both before and after were:
FAIL: crisv10 mem1.ms (execution)
FAIL: crisv10 mem2.ms (execution)
FAIL: crisv32 mem1.ms (execution)
FAIL: crisv32 mem2.ms (execution)
FAIL: frv cmcpxis.cgs (execution)
FAIL: fr500 cmcpxis.cgs (execution)
FAIL: fr400 cmcpxis.cgs (execution)
FAIL: fr405 cmcpxis.cgs (execution)
FAIL: fr450 cmcpxis.cgs (execution)
FAIL: frv cmcpxiu.cgs (execution)
FAIL: fr500 cmcpxiu.cgs (execution)
FAIL: fr400 cmcpxiu.cgs (execution)
FAIL: frv cmcpxrs.cgs (execution)
FAIL: fr500 cmcpxrs.cgs (execution)
FAIL: fr400 cmcpxrs.cgs (execution)
FAIL: fr405 cmcpxrs.cgs (execution)
FAIL: fr450 cmcpxrs.cgs (execution)
FAIL: frv cmcpxru.cgs (execution)
FAIL: fr500 cmcpxru.cgs (execution)
FAIL: fr400 cmcpxru.cgs (execution)
FAIL: frv cmmachs.cgs (execution)
FAIL: fr500 cmmachs.cgs (execution)
FAIL: fr400 cmmachs.cgs (execution)
FAIL: frv cmmachu.cgs (execution)
FAIL: fr500 cmmachu.cgs (execution)
FAIL: fr400 cmmachu.cgs (execution)
FAIL: frv cmmulhs.cgs (execution)
FAIL: fr500 cmmulhs.cgs (execution)
FAIL: fr400 cmmulhs.cgs (execution)
FAIL: fr405 cmmulhs.cgs (execution)
FAIL: fr450 cmmulhs.cgs (execution)
FAIL: frv cmmulhu.cgs (execution)
FAIL: fr500 cmmulhu.cgs (execution)
FAIL: fr400 cmmulhu.cgs (execution)
FAIL: fr405 cmmulhu.cgs (execution)
FAIL: fr450 cmmulhu.cgs (execution)
FAIL: frv cmqmachs.cgs (execution)
FAIL: fr500 cmqmachs.cgs (execution)
FAIL: fr400 cmqmachs.cgs (execution)
FAIL: frv cmqmachu.cgs (execution)
FAIL: fr500 cmqmachu.cgs (execution)
FAIL: fr400 cmqmachu.cgs (execution)
FAIL: frv cmqmulhs.cgs (execution)
FAIL: fr500 cmqmulhs.cgs (execution)
FAIL: fr400 cmqmulhs.cgs (execution)
FAIL: fr405 cmqmulhs.cgs (execution)
FAIL: fr450 cmqmulhs.cgs (execution)
FAIL: frv cmqmulhu.cgs (execution)
FAIL: fr500 cmqmulhu.cgs (execution)
FAIL: fr400 cmqmulhu.cgs (execution)
FAIL: fr405 cmqmulhu.cgs (execution)
FAIL: fr450 cmqmulhu.cgs (execution)
FAIL: frv mcpxis.cgs (execution)
FAIL: fr500 mcpxis.cgs (execution)
FAIL: fr400 mcpxis.cgs (execution)
FAIL: fr405 mcpxis.cgs (execution)
FAIL: fr450 mcpxis.cgs (execution)
FAIL: frv mcpxiu.cgs (execution)
FAIL: fr500 mcpxiu.cgs (execution)
FAIL: fr400 mcpxiu.cgs (execution)
FAIL: fr405 mcpxiu.cgs (execution)
FAIL: fr450 mcpxiu.cgs (execution)
FAIL: frv mcpxrs.cgs (execution)
FAIL: fr500 mcpxrs.cgs (execution)
FAIL: fr400 mcpxrs.cgs (execution)
FAIL: fr405 mcpxrs.cgs (execution)
FAIL: fr450 mcpxrs.cgs (execution)
FAIL: frv mcpxru.cgs (execution)
FAIL: fr500 mcpxru.cgs (execution)
FAIL: fr400 mcpxru.cgs (execution)
FAIL: fr405 mcpxru.cgs (execution)
FAIL: fr450 mcpxru.cgs (execution)
FAIL: fr400 mdaddaccs.cgs (execution)
FAIL: fr400 mdasaccs.cgs (execution)
FAIL: fr400 mdsubaccs.cgs (execution)
FAIL: frv mmachs.cgs (execution)
FAIL: fr500 mmachs.cgs (execution)
FAIL: fr400 mmachs.cgs (execution)
FAIL: frv mmachu.cgs (execution)
FAIL: fr500 mmachu.cgs (execution)
FAIL: fr400 mmachu.cgs (execution)
FAIL: frv mmrdhs.cgs (execution)
FAIL: fr500 mmrdhs.cgs (execution)
FAIL: fr400 mmrdhs.cgs (execution)
FAIL: frv mmrdhu.cgs (execution)
FAIL: fr500 mmrdhu.cgs (execution)
FAIL: fr400 mmrdhu.cgs (execution)
FAIL: frv mmulhs.cgs (execution)
FAIL: fr500 mmulhs.cgs (execution)
FAIL: fr400 mmulhs.cgs (execution)
FAIL: fr405 mmulhs.cgs (execution)
FAIL: fr450 mmulhs.cgs (execution)
FAIL: frv mmulhu.cgs (execution)
FAIL: fr500 mmulhu.cgs (execution)
FAIL: fr400 mmulhu.cgs (execution)
FAIL: fr405 mmulhu.cgs (execution)
FAIL: fr450 mmulhu.cgs (execution)
FAIL: frv mmulxhs.cgs (execution)
FAIL: fr500 mmulxhs.cgs (execution)
FAIL: fr400 mmulxhs.cgs (execution)
FAIL: fr405 mmulxhs.cgs (execution)
FAIL: fr450 mmulxhs.cgs (execution)
FAIL: frv mmulxhu.cgs (execution)
FAIL: fr500 mmulxhu.cgs (execution)
FAIL: fr400 mmulxhu.cgs (execution)
FAIL: fr405 mmulxhu.cgs (execution)
FAIL: fr450 mmulxhu.cgs (execution)
FAIL: frv mqcpxis.cgs (execution)
FAIL: fr500 mqcpxis.cgs (execution)
FAIL: fr400 mqcpxis.cgs (execution)
FAIL: fr405 mqcpxis.cgs (execution)
FAIL: fr450 mqcpxis.cgs (execution)
FAIL: frv mqcpxiu.cgs (execution)
FAIL: fr500 mqcpxiu.cgs (execution)
FAIL: fr400 mqcpxiu.cgs (execution)
FAIL: fr405 mqcpxiu.cgs (execution)
FAIL: fr450 mqcpxiu.cgs (execution)
FAIL: frv mqcpxrs.cgs (execution)
FAIL: fr500 mqcpxrs.cgs (execution)
FAIL: fr400 mqcpxrs.cgs (execution)
FAIL: fr405 mqcpxrs.cgs (execution)
FAIL: fr450 mqcpxrs.cgs (execution)
FAIL: frv mqcpxru.cgs (execution)
FAIL: fr500 mqcpxru.cgs (execution)
FAIL: fr400 mqcpxru.cgs (execution)
FAIL: fr405 mqcpxru.cgs (execution)
FAIL: fr450 mqcpxru.cgs (execution)
FAIL: frv mqmachs.cgs (execution)
FAIL: fr500 mqmachs.cgs (execution)
FAIL: fr400 mqmachs.cgs (execution)
FAIL: frv mqmachu.cgs (execution)
FAIL: fr500 mqmachu.cgs (execution)
FAIL: fr400 mqmachu.cgs (execution)
FAIL: fr400 mqmacxhs.cgs (execution)
FAIL: frv mqmulhs.cgs (execution)
FAIL: fr500 mqmulhs.cgs (execution)
FAIL: fr400 mqmulhs.cgs (execution)
FAIL: fr405 mqmulhs.cgs (execution)
FAIL: fr450 mqmulhs.cgs (execution)
FAIL: frv mqmulhu.cgs (execution)
FAIL: fr500 mqmulhu.cgs (execution)
FAIL: fr400 mqmulhu.cgs (execution)
FAIL: fr405 mqmulhu.cgs (execution)
FAIL: fr450 mqmulhu.cgs (execution)
FAIL: frv mqmulxhs.cgs (execution)
FAIL: fr500 mqmulxhs.cgs (execution)
FAIL: fr400 mqmulxhs.cgs (execution)
FAIL: fr405 mqmulxhs.cgs (execution)
FAIL: fr450 mqmulxhs.cgs (execution)
FAIL: frv mqmulxhu.cgs (execution)
FAIL: fr500 mqmulxhu.cgs (execution)
FAIL: fr400 mqmulxhu.cgs (execution)
FAIL: fr405 mqmulxhu.cgs (execution)
FAIL: fr450 mqmulxhu.cgs (execution)
FAIL: fr400 mqxmachs.cgs (execution)
FAIL: fr400 mqxmacxhs.cgs (execution)
FAIL: fr400 maddaccs.cgs (execution)
FAIL: fr400 masaccs.cgs (execution)
FAIL: fr400 msubaccs.cgs (execution)
FAIL: microblaze fail.s (execution)
FAIL: microblaze pass.s (execution)
expected passes 5133
unexpected failures 161
expected failures 3
untested testcases 373
unsupported tests 14
--
Alan Modra
Australia Development Lab, IBM
[-- Attachment #2: 0006-sim-regen.patch.xz --]
[-- Type: application/x-xz, Size: 18940 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: sim regen
2023-08-14 13:39 sim regen Alan Modra
@ 2023-08-18 16:40 ` Tom Tromey
2023-08-18 23:46 ` Alan Modra
0 siblings, 1 reply; 5+ messages in thread
From: Tom Tromey @ 2023-08-18 16:40 UTC (permalink / raw)
To: Alan Modra via Gdb-patches; +Cc: Alan Modra
>>>>> "Alan" == Alan Modra via Gdb-patches <gdb-patches@sourceware.org> writes:
Alan> The attached patch regenerates sim files.
Alan> Tested with the following tools from a recent binutils build in
Alan> sim-site-config.exp, plus a few cross compilers.
I didn't really look at the patch. I think regeneration like this
should be fine.
I'm curious how you did it. cgen does not run for me. I suspect maybe
you used an old version of Guile, but confirmation would be nice.
Tom
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: sim regen
2023-08-18 16:40 ` Tom Tromey
@ 2023-08-18 23:46 ` Alan Modra
2023-08-19 0:26 ` Tom Tromey
0 siblings, 1 reply; 5+ messages in thread
From: Alan Modra @ 2023-08-18 23:46 UTC (permalink / raw)
To: Tom Tromey; +Cc: Alan Modra via Gdb-patches
On Fri, Aug 18, 2023 at 10:40:38AM -0600, Tom Tromey wrote:
> >>>>> "Alan" == Alan Modra via Gdb-patches <gdb-patches@sourceware.org> writes:
>
> Alan> The attached patch regenerates sim files.
> Alan> Tested with the following tools from a recent binutils build in
> Alan> sim-site-config.exp, plus a few cross compilers.
>
> I didn't really look at the patch. I think regeneration like this
> should be fine.
>
> I'm curious how you did it. cgen does not run for me. I suspect maybe
> you used an old version of Guile, but confirmation would be nice.
I'm using guile 1.8.8, built from source five years ago. I can't
remember why I built it, possibly because the cgen README says "CGEN
has been tested with Guile 1.4.1, 1.6.8, and 1.8.5." and likely I also
found cgen didn't work with cgen 2 or later. cgen is current master
branch sourceware git/cgen.git.
Besides the "sim regen preparation" patch which you OK'd, I also have
"sim prune warnings"
https://sourceware.org/pipermail/gdb-patches/2023-August/201586.html
and "sim --enable-cgen-maint"
https://sourceware.org/pipermail/gdb-patches/2023-August/201494.html
in my tree.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: sim regen
2023-08-18 23:46 ` Alan Modra
@ 2023-08-19 0:26 ` Tom Tromey
0 siblings, 0 replies; 5+ messages in thread
From: Tom Tromey @ 2023-08-19 0:26 UTC (permalink / raw)
To: Alan Modra; +Cc: Tom Tromey, Alan Modra via Gdb-patches
Alan> Besides the "sim regen preparation" patch which you OK'd, I also have
Alan> "sim prune warnings"
Alan> https://sourceware.org/pipermail/gdb-patches/2023-August/201586.html
Alan> and "sim --enable-cgen-maint"
Alan> https://sourceware.org/pipermail/gdb-patches/2023-August/201494.html
Alan> in my tree.
These are both OK. Thank you.
Tom
^ permalink raw reply [flat|nested] 5+ messages in thread
* sim regen
@ 2023-08-14 11:59 Alan Modra
0 siblings, 0 replies; 5+ messages in thread
From: Alan Modra @ 2023-08-14 11:59 UTC (permalink / raw)
To: gdb-patches
This regenerates sim files.
Tested with the following tools from a recent binutils build in
sim-site-config.exp, plus a few cross compilers.
set AS_FOR_TARGET_AARCH64 "/home/alan/build/gas/aarch64-linux-gnu/gas/as-new"
set LD_FOR_TARGET_AARCH64 "/home/alan/build/gas/aarch64-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_AARCH64 "aarch64-linux-gnu-gcc"
set AS_FOR_TARGET_ARM "/home/alan/build/gas/arm-linux-gnueabi/gas/as-new"
set LD_FOR_TARGET_ARM "/home/alan/build/gas/arm-linux-gnueabi/ld/ld-new"
set CC_FOR_TARGET_ARM "arm-linux-gnueabi-gcc"
set AS_FOR_TARGET_AVR "/home/alan/build/gas/avr-elf/gas/as-new"
set LD_FOR_TARGET_AVR "/home/alan/build/gas/avr-elf/ld/ld-new"
set CC_FOR_TARGET_AVR ""
set AS_FOR_TARGET_BFIN "/home/alan/build/gas/bfin-elf/gas/as-new"
set LD_FOR_TARGET_BFIN "/home/alan/build/gas/bfin-elf/ld/ld-new"
set CC_FOR_TARGET_BFIN ""
set AS_FOR_TARGET_BPF "/home/alan/build/gas/bpf-none/gas/as-new"
set LD_FOR_TARGET_BPF "/home/alan/build/gas/bpf-none/ld/ld-new"
set CC_FOR_TARGET_BPF ""
set AS_FOR_TARGET_CR16 "/home/alan/build/gas/cr16-elf/gas/as-new"
set LD_FOR_TARGET_CR16 "/home/alan/build/gas/cr16-elf/ld/ld-new"
set CC_FOR_TARGET_CR16 ""
set AS_FOR_TARGET_CRIS "/home/alan/build/gas/cris-elf/gas/as-new"
set LD_FOR_TARGET_CRIS "/home/alan/build/gas/cris-elf/ld/ld-new"
set CC_FOR_TARGET_CRIS ""
set AS_FOR_TARGET_D10V "/home/alan/build/gas/d10v-elf/gas/as-new"
set LD_FOR_TARGET_D10V "/home/alan/build/gas/d10v-elf/ld/ld-new"
set CC_FOR_TARGET_D10V ""
set AS_FOR_TARGET_FRV "/home/alan/build/gas/frv-elf/gas/as-new"
set LD_FOR_TARGET_FRV "/home/alan/build/gas/frv-elf/ld/ld-new"
set CC_FOR_TARGET_FRV ""
set AS_FOR_TARGET_FT32 "/home/alan/build/gas/ft32-elf/gas/as-new"
set LD_FOR_TARGET_FT32 "/home/alan/build/gas/ft32-elf/ld/ld-new"
set CC_FOR_TARGET_FT32 ""
set AS_FOR_TARGET_H8300 "/home/alan/build/gas/h8300-elf/gas/as-new"
set LD_FOR_TARGET_H8300 "/home/alan/build/gas/h8300-elf/ld/ld-new"
set CC_FOR_TARGET_H8300 ""
set AS_FOR_TARGET_IQ2000 "/home/alan/build/gas/iq2000-elf/gas/as-new"
set LD_FOR_TARGET_IQ2000 "/home/alan/build/gas/iq2000-elf/ld/ld-new"
set CC_FOR_TARGET_IQ2000 ""
set AS_FOR_TARGET_LM32 "/home/alan/build/gas/lm32-linux-gnu/gas/as-new"
set LD_FOR_TARGET_LM32 "/home/alan/build/gas/lm32-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_LM32 ""
set AS_FOR_TARGET_M32C "/home/alan/build/gas/m32c-elf/gas/as-new"
set LD_FOR_TARGET_M32C "/home/alan/build/gas/m32c-elf/ld/ld-new"
set CC_FOR_TARGET_M32C ""
set AS_FOR_TARGET_M32R "/home/alan/build/gas/m32r-elf/gas/as-new"
set LD_FOR_TARGET_M32R "/home/alan/build/gas/m32r-elf/ld/ld-new"
set CC_FOR_TARGET_M32R ""
set AS_FOR_TARGET_M68HC11 "/home/alan/build/gas/m68hc11-elf/gas/as-new"
set LD_FOR_TARGET_M68HC11 "/home/alan/build/gas/m68hc11-elf/ld/ld-new"
set CC_FOR_TARGET_M68HC11 ""
set AS_FOR_TARGET_MCORE "/home/alan/build/gas/mcore-elf/gas/as-new"
set LD_FOR_TARGET_MCORE "/home/alan/build/gas/mcore-elf/ld/ld-new"
set CC_FOR_TARGET_MCORE ""
set AS_FOR_TARGET_MICROBLAZE "/home/alan/build/gas/microblaze-linux-gnu/gas/as-new"
set LD_FOR_TARGET_MICROBLAZE "/home/alan/build/gas/microblaze-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_MICROBLAZE "microblaze-linux-gnu-gcc"
set AS_FOR_TARGET_MIPS "/home/alan/build/gas/mips-linux-gnu/gas/as-new"
set LD_FOR_TARGET_MIPS "/home/alan/build/gas/mips-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_MIPS "mips-linux-gnu-gcc"
set AS_FOR_TARGET_MN10300 "/home/alan/build/gas/mn10300-elf/gas/as-new"
set LD_FOR_TARGET_MN10300 "/home/alan/build/gas/mn10300-elf/ld/ld-new"
set CC_FOR_TARGET_MN10300 ""
set AS_FOR_TARGET_MOXIE "/home/alan/build/gas/moxie-elf/gas/as-new"
set LD_FOR_TARGET_MOXIE "/home/alan/build/gas/moxie-elf/ld/ld-new"
set CC_FOR_TARGET_MOXIE ""
set AS_FOR_TARGET_MSP430 "/home/alan/build/gas/msp430-elf/gas/as-new"
set LD_FOR_TARGET_MSP430 "/home/alan/build/gas/msp430-elf/ld/ld-new"
set CC_FOR_TARGET_MSP430 ""
set AS_FOR_TARGET_OR1K "/home/alan/build/gas/or1k-linux-gnu/gas/as-new"
set LD_FOR_TARGET_OR1K "/home/alan/build/gas/or1k-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_OR1K ""
set AS_FOR_TARGET_PPC "/home/alan/build/gas/powerpc-linux-gnu/gas/as-new"
set LD_FOR_TARGET_PPC "/home/alan/build/gas/powerpc-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_PPC "powerpc-linux-gnu-gcc"
set AS_FOR_TARGET_PRU "/home/alan/build/gas/pru-elf/gas/as-new"
set LD_FOR_TARGET_PRU "/home/alan/build/gas/pru-elf/ld/ld-new"
set CC_FOR_TARGET_PRU ""
set AS_FOR_TARGET_RISCV "/home/alan/build/gas/riscv32-elf/gas/as-new"
set LD_FOR_TARGET_RISCV "/home/alan/build/gas/riscv32-elf/ld/ld-new"
set CC_FOR_TARGET_RISCV ""
set AS_FOR_TARGET_RL78 "/home/alan/build/gas/rl78-elf/gas/as-new"
set LD_FOR_TARGET_RL78 "/home/alan/build/gas/rl78-elf/ld/ld-new"
set CC_FOR_TARGET_RL78 ""
set AS_FOR_TARGET_RX "/home/alan/build/gas/rx-elf/gas/as-new"
set LD_FOR_TARGET_RX "/home/alan/build/gas/rx-elf/ld/ld-new"
set CC_FOR_TARGET_RX ""
set AS_FOR_TARGET_SH "/home/alan/build/gas/sh-rtems/gas/as-new"
set LD_FOR_TARGET_SH "/home/alan/build/gas/sh-rtems/ld/ld-new"
set CC_FOR_TARGET_SH ""
set AS_FOR_TARGET_ERC32 ""
set LD_FOR_TARGET_ERC32 ""
set CC_FOR_TARGET_ERC32 ""
set AS_FOR_TARGET_V850 "/home/alan/build/gas/v850-elf/gas/as-new"
set LD_FOR_TARGET_V850 "/home/alan/build/gas/v850-elf/ld/ld-new"
set CC_FOR_TARGET_V850 ""
Results both before and after were:
FAIL: crisv10 mem1.ms (execution)
FAIL: crisv10 mem2.ms (execution)
FAIL: crisv32 mem1.ms (execution)
FAIL: crisv32 mem2.ms (execution)
FAIL: frv cmcpxis.cgs (execution)
FAIL: fr500 cmcpxis.cgs (execution)
FAIL: fr400 cmcpxis.cgs (execution)
FAIL: fr405 cmcpxis.cgs (execution)
FAIL: fr450 cmcpxis.cgs (execution)
FAIL: frv cmcpxiu.cgs (execution)
FAIL: fr500 cmcpxiu.cgs (execution)
FAIL: fr400 cmcpxiu.cgs (execution)
FAIL: frv cmcpxrs.cgs (execution)
FAIL: fr500 cmcpxrs.cgs (execution)
FAIL: fr400 cmcpxrs.cgs (execution)
FAIL: fr405 cmcpxrs.cgs (execution)
FAIL: fr450 cmcpxrs.cgs (execution)
FAIL: frv cmcpxru.cgs (execution)
FAIL: fr500 cmcpxru.cgs (execution)
FAIL: fr400 cmcpxru.cgs (execution)
FAIL: frv cmmachs.cgs (execution)
FAIL: fr500 cmmachs.cgs (execution)
FAIL: fr400 cmmachs.cgs (execution)
FAIL: frv cmmachu.cgs (execution)
FAIL: fr500 cmmachu.cgs (execution)
FAIL: fr400 cmmachu.cgs (execution)
FAIL: frv cmmulhs.cgs (execution)
FAIL: fr500 cmmulhs.cgs (execution)
FAIL: fr400 cmmulhs.cgs (execution)
FAIL: fr405 cmmulhs.cgs (execution)
FAIL: fr450 cmmulhs.cgs (execution)
FAIL: frv cmmulhu.cgs (execution)
FAIL: fr500 cmmulhu.cgs (execution)
FAIL: fr400 cmmulhu.cgs (execution)
FAIL: fr405 cmmulhu.cgs (execution)
FAIL: fr450 cmmulhu.cgs (execution)
FAIL: frv cmqmachs.cgs (execution)
FAIL: fr500 cmqmachs.cgs (execution)
FAIL: fr400 cmqmachs.cgs (execution)
FAIL: frv cmqmachu.cgs (execution)
FAIL: fr500 cmqmachu.cgs (execution)
FAIL: fr400 cmqmachu.cgs (execution)
FAIL: frv cmqmulhs.cgs (execution)
FAIL: fr500 cmqmulhs.cgs (execution)
FAIL: fr400 cmqmulhs.cgs (execution)
FAIL: fr405 cmqmulhs.cgs (execution)
FAIL: fr450 cmqmulhs.cgs (execution)
FAIL: frv cmqmulhu.cgs (execution)
FAIL: fr500 cmqmulhu.cgs (execution)
FAIL: fr400 cmqmulhu.cgs (execution)
FAIL: fr405 cmqmulhu.cgs (execution)
FAIL: fr450 cmqmulhu.cgs (execution)
FAIL: frv mcpxis.cgs (execution)
FAIL: fr500 mcpxis.cgs (execution)
FAIL: fr400 mcpxis.cgs (execution)
FAIL: fr405 mcpxis.cgs (execution)
FAIL: fr450 mcpxis.cgs (execution)
FAIL: frv mcpxiu.cgs (execution)
FAIL: fr500 mcpxiu.cgs (execution)
FAIL: fr400 mcpxiu.cgs (execution)
FAIL: fr405 mcpxiu.cgs (execution)
FAIL: fr450 mcpxiu.cgs (execution)
FAIL: frv mcpxrs.cgs (execution)
FAIL: fr500 mcpxrs.cgs (execution)
FAIL: fr400 mcpxrs.cgs (execution)
FAIL: fr405 mcpxrs.cgs (execution)
FAIL: fr450 mcpxrs.cgs (execution)
FAIL: frv mcpxru.cgs (execution)
FAIL: fr500 mcpxru.cgs (execution)
FAIL: fr400 mcpxru.cgs (execution)
FAIL: fr405 mcpxru.cgs (execution)
FAIL: fr450 mcpxru.cgs (execution)
FAIL: fr400 mdaddaccs.cgs (execution)
FAIL: fr400 mdasaccs.cgs (execution)
FAIL: fr400 mdsubaccs.cgs (execution)
FAIL: frv mmachs.cgs (execution)
FAIL: fr500 mmachs.cgs (execution)
FAIL: fr400 mmachs.cgs (execution)
FAIL: frv mmachu.cgs (execution)
FAIL: fr500 mmachu.cgs (execution)
FAIL: fr400 mmachu.cgs (execution)
FAIL: frv mmrdhs.cgs (execution)
FAIL: fr500 mmrdhs.cgs (execution)
FAIL: fr400 mmrdhs.cgs (execution)
FAIL: frv mmrdhu.cgs (execution)
FAIL: fr500 mmrdhu.cgs (execution)
FAIL: fr400 mmrdhu.cgs (execution)
FAIL: frv mmulhs.cgs (execution)
FAIL: fr500 mmulhs.cgs (execution)
FAIL: fr400 mmulhs.cgs (execution)
FAIL: fr405 mmulhs.cgs (execution)
FAIL: fr450 mmulhs.cgs (execution)
FAIL: frv mmulhu.cgs (execution)
FAIL: fr500 mmulhu.cgs (execution)
FAIL: fr400 mmulhu.cgs (execution)
FAIL: fr405 mmulhu.cgs (execution)
FAIL: fr450 mmulhu.cgs (execution)
FAIL: frv mmulxhs.cgs (execution)
FAIL: fr500 mmulxhs.cgs (execution)
FAIL: fr400 mmulxhs.cgs (execution)
FAIL: fr405 mmulxhs.cgs (execution)
FAIL: fr450 mmulxhs.cgs (execution)
FAIL: frv mmulxhu.cgs (execution)
FAIL: fr500 mmulxhu.cgs (execution)
FAIL: fr400 mmulxhu.cgs (execution)
FAIL: fr405 mmulxhu.cgs (execution)
FAIL: fr450 mmulxhu.cgs (execution)
FAIL: frv mqcpxis.cgs (execution)
FAIL: fr500 mqcpxis.cgs (execution)
FAIL: fr400 mqcpxis.cgs (execution)
FAIL: fr405 mqcpxis.cgs (execution)
FAIL: fr450 mqcpxis.cgs (execution)
FAIL: frv mqcpxiu.cgs (execution)
FAIL: fr500 mqcpxiu.cgs (execution)
FAIL: fr400 mqcpxiu.cgs (execution)
FAIL: fr405 mqcpxiu.cgs (execution)
FAIL: fr450 mqcpxiu.cgs (execution)
FAIL: frv mqcpxrs.cgs (execution)
FAIL: fr500 mqcpxrs.cgs (execution)
FAIL: fr400 mqcpxrs.cgs (execution)
FAIL: fr405 mqcpxrs.cgs (execution)
FAIL: fr450 mqcpxrs.cgs (execution)
FAIL: frv mqcpxru.cgs (execution)
FAIL: fr500 mqcpxru.cgs (execution)
FAIL: fr400 mqcpxru.cgs (execution)
FAIL: fr405 mqcpxru.cgs (execution)
FAIL: fr450 mqcpxru.cgs (execution)
FAIL: frv mqmachs.cgs (execution)
FAIL: fr500 mqmachs.cgs (execution)
FAIL: fr400 mqmachs.cgs (execution)
FAIL: frv mqmachu.cgs (execution)
FAIL: fr500 mqmachu.cgs (execution)
FAIL: fr400 mqmachu.cgs (execution)
FAIL: fr400 mqmacxhs.cgs (execution)
FAIL: frv mqmulhs.cgs (execution)
FAIL: fr500 mqmulhs.cgs (execution)
FAIL: fr400 mqmulhs.cgs (execution)
FAIL: fr405 mqmulhs.cgs (execution)
FAIL: fr450 mqmulhs.cgs (execution)
FAIL: frv mqmulhu.cgs (execution)
FAIL: fr500 mqmulhu.cgs (execution)
FAIL: fr400 mqmulhu.cgs (execution)
FAIL: fr405 mqmulhu.cgs (execution)
FAIL: fr450 mqmulhu.cgs (execution)
FAIL: frv mqmulxhs.cgs (execution)
FAIL: fr500 mqmulxhs.cgs (execution)
FAIL: fr400 mqmulxhs.cgs (execution)
FAIL: fr405 mqmulxhs.cgs (execution)
FAIL: fr450 mqmulxhs.cgs (execution)
FAIL: frv mqmulxhu.cgs (execution)
FAIL: fr500 mqmulxhu.cgs (execution)
FAIL: fr400 mqmulxhu.cgs (execution)
FAIL: fr405 mqmulxhu.cgs (execution)
FAIL: fr450 mqmulxhu.cgs (execution)
FAIL: fr400 mqxmachs.cgs (execution)
FAIL: fr400 mqxmacxhs.cgs (execution)
FAIL: fr400 maddaccs.cgs (execution)
FAIL: fr400 masaccs.cgs (execution)
FAIL: fr400 msubaccs.cgs (execution)
FAIL: microblaze fail.s (execution)
FAIL: microblaze pass.s (execution)
expected passes 5133
unexpected failures 161
expected failures 3
untested testcases 373
unsupported tests 14
diff --git a/sim/cris/arch.c b/sim/cris/arch.c
index b7c7c06f68a..b251f0d9fed 100644
--- a/sim/cris/arch.c
+++ b/sim/cris/arch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/arch.h b/sim/cris/arch.h
index d672317c79b..f8dbc2cfa0a 100644
--- a/sim/cris/arch.h
+++ b/sim/cris/arch.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef CRIS_ARCH_H
#define CRIS_ARCH_H
+#define TARGET_BIG_ENDIAN 1
+
+#define WI SI
+#define UWI USI
+#define AI USI
+
+#define IAI USI
+
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_CRISV10, MODEL_CRISV32, MODEL_MAX
diff --git a/sim/cris/cpuall.h b/sim/cris/cpuall.h
index a395b1d216b..da4c184dc5d 100644
--- a/sim/cris/cpuall.h
+++ b/sim/cris/cpuall.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/cpuv10.c b/sim/cris/cpuv10.c
index a33187ec6cb..72001764581 100644
--- a/sim/cris/cpuv10.c
+++ b/sim/cris/cpuv10.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/cpuv10.h b/sim/cris/cpuv10.h
index 016d5f9d9d2..280b755548d 100644
--- a/sim/cris/cpuv10.h
+++ b/sim/cris/cpuv10.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/cpuv32.c b/sim/cris/cpuv32.c
index 2f059d0f620..0044c41edd9 100644
--- a/sim/cris/cpuv32.c
+++ b/sim/cris/cpuv32.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/cpuv32.h b/sim/cris/cpuv32.h
index 65d9ff0aa8f..cfe428d67fc 100644
--- a/sim/cris/cpuv32.h
+++ b/sim/cris/cpuv32.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/decodev10.c b/sim/cris/decodev10.c
index c04f88286b6..cce20bc4f53 100644
--- a/sim/cris/decodev10.c
+++ b/sim/cris/decodev10.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/decodev10.h b/sim/cris/decodev10.h
index 42db1cdbeb6..1a8e24ff8eb 100644
--- a/sim/cris/decodev10.h
+++ b/sim/cris/decodev10.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -30,7 +31,6 @@ extern const IDESC *crisv10f_decode (SIM_CPU *, IADDR,
extern void crisv10f_init_idesc_table (SIM_CPU *);
extern void crisv10f_sem_init_idesc_table (SIM_CPU *);
extern void crisv10f_semf_init_idesc_table (SIM_CPU *);
-extern void crisv10f_specific_init (SIM_CPU *);
/* Enum declaration for instructions in cpu family crisv10f. */
typedef enum crisv10f_insn_type {
diff --git a/sim/cris/decodev32.c b/sim/cris/decodev32.c
index 01e241d4264..6edf456650f 100644
--- a/sim/cris/decodev32.c
+++ b/sim/cris/decodev32.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/decodev32.h b/sim/cris/decodev32.h
index 75ba084cd71..fdd404f985d 100644
--- a/sim/cris/decodev32.h
+++ b/sim/cris/decodev32.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -30,7 +31,6 @@ extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
extern void crisv32f_init_idesc_table (SIM_CPU *);
extern void crisv32f_sem_init_idesc_table (SIM_CPU *);
extern void crisv32f_semf_init_idesc_table (SIM_CPU *);
-extern void crisv32f_specific_init (SIM_CPU *);
/* Enum declaration for instructions in cpu family crisv32f. */
typedef enum crisv32f_insn_type {
@@ -127,7 +127,6 @@ extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*
extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
-extern int crisv32f_model_crisv32_u_stall (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_jump (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Pd*/);
diff --git a/sim/cris/modelv10.c b/sim/cris/modelv10.c
index 6ef9888eb92..ba79786b32f 100644
--- a/sim/cris/modelv10.c
+++ b/sim/cris/modelv10.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/modelv32.c b/sim/cris/modelv32.c
index f173757c2f3..5ef81ffb6c3 100644
--- a/sim/cris/modelv32.c
+++ b/sim/cris/modelv32.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/semcrisv10f-switch.c b/sim/cris/semcrisv10f-switch.c
index b326bd828df..a2bf6f1a630 100644
--- a/sim/cris/semcrisv10f-switch.c
+++ b/sim/cris/semcrisv10f-switch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/cris/semcrisv32f-switch.c b/sim/cris/semcrisv32f-switch.c
index 6d2e04e2486..4f5f26706f7 100644
--- a/sim/cris/semcrisv32f-switch.c
+++ b/sim/cris/semcrisv32f-switch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/frv/arch.c b/sim/frv/arch.c
index 0ac34c0cf33..9fa4a258133 100644
--- a/sim/frv/arch.c
+++ b/sim/frv/arch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/frv/arch.h b/sim/frv/arch.h
index 2bd9869ff6e..0fb164477c9 100644
--- a/sim/frv/arch.h
+++ b/sim/frv/arch.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef FRV_ARCH_H
#define FRV_ARCH_H
+#define TARGET_BIG_ENDIAN 1
+
+#define WI SI
+#define UWI USI
+#define AI USI
+
+#define IAI USI
+
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_FRV, MODEL_FR550, MODEL_FR500, MODEL_TOMCAT
diff --git a/sim/frv/cpu.c b/sim/frv/cpu.c
index aa116ca586e..195c8a12e17 100644
--- a/sim/frv/cpu.c
+++ b/sim/frv/cpu.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h
index b129c147fb1..fbb6c571c33 100644
--- a/sim/frv/cpu.h
+++ b/sim/frv/cpu.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -2191,7 +2192,7 @@ struct scache {
f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
- f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc)); \
+ f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BNO_VARS \
UINT f_pack; \
@@ -2225,7 +2226,7 @@ struct scache {
f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
- f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc)); \
+ f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_FBRA_VARS \
UINT f_pack; \
@@ -2242,7 +2243,7 @@ struct scache {
f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
- f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc)); \
+ f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_FBNO_VARS \
UINT f_pack; \
@@ -2276,7 +2277,7 @@ struct scache {
f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
- f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc)); \
+ f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BCTRLR_VARS \
UINT f_pack; \
@@ -2595,7 +2596,7 @@ struct scache {
f_labelH6 = EXTRACT_LSB0_SINT (insn, 32, 30, 6); \
f_labelL18 = EXTRACT_LSB0_UINT (insn, 32, 17, 18); \
{\
- f_label24 = ((((((((f_labelH6) << (18))) | (f_labelL18))) << (2))) + (pc));\
+ f_label24 = ((((((((f_labelH6) * (((1) << (18))))) | (f_labelL18))) * (4))) + (pc));\
}\
#define EXTRACT_IFMT_RETT_VARS \
@@ -3584,7 +3585,7 @@ struct scache {
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6); \
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
{\
- f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\
+ f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));\
}\
#define EXTRACT_IFMT_MHSETHIS_VARS \
@@ -3605,7 +3606,7 @@ struct scache {
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6); \
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
{\
- f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\
+ f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));\
}\
#define EXTRACT_IFMT_MHDSETS_VARS \
@@ -3626,7 +3627,7 @@ struct scache {
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6); \
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
{\
- f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\
+ f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));\
}\
#define EXTRACT_IFMT_MHSETLOH_VARS \
diff --git a/sim/frv/cpuall.h b/sim/frv/cpuall.h
index 2210fb1dc0b..cee529fd810 100644
--- a/sim/frv/cpuall.h
+++ b/sim/frv/cpuall.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/frv/decode.c b/sim/frv/decode.c
index d6d2cdbfcc9..876dda24c20 100644
--- a/sim/frv/decode.c
+++ b/sim/frv/decode.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
@@ -7302,7 +7305,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_label16;
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
- f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
+ f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_hint) = f_hint;
@@ -7328,7 +7331,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_label16;
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
- f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
+ f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_hint) = f_hint;
@@ -7350,7 +7353,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
- f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
+ f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_ICCi_2) = f_ICCi_2;
@@ -7378,7 +7381,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_label16;
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
- f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
+ f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_hint) = f_hint;
@@ -7404,7 +7407,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_label16;
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
- f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
+ f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_hint) = f_hint;
@@ -7426,7 +7429,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
- f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
+ f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_FCCi_2) = f_FCCi_2;
@@ -7936,7 +7939,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_labelH6 = EXTRACT_LSB0_SINT (insn, 32, 30, 6);
f_labelL18 = EXTRACT_LSB0_UINT (insn, 32, 17, 18);
{
- f_label24 = ((((((((f_labelH6) << (18))) | (f_labelL18))) << (2))) + (pc));
+ f_label24 = ((((((((f_labelH6) * (((1) << (18))))) | (f_labelL18))) * (4))) + (pc));
}
/* Record the fields for the semantic handler. */
@@ -9919,7 +9922,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6);
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
{
- f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));
+ f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));
}
/* Record the fields for the semantic handler. */
@@ -9952,7 +9955,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6);
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
{
- f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));
+ f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));
}
/* Record the fields for the semantic handler. */
@@ -9985,7 +9988,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6);
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
{
- f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));
+ f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));
}
/* Record the fields for the semantic handler. */
diff --git a/sim/frv/decode.h b/sim/frv/decode.h
index 4b2be351b8d..cd7f7111ea5 100644
--- a/sim/frv/decode.h
+++ b/sim/frv/decode.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/frv/model.c b/sim/frv/model.c
index 8a67c82fcab..30a6baddb31 100644
--- a/sim/frv/model.c
+++ b/sim/frv/model.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/frv/sem.c b/sim/frv/sem.c
index d7e54d665c9..20ac47be764 100644
--- a/sim/frv/sem.c
+++ b/sim/frv/sem.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/iq2000/arch.c b/sim/iq2000/arch.c
index 841d0eafbaa..9328e644f63 100644
--- a/sim/iq2000/arch.c
+++ b/sim/iq2000/arch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/iq2000/arch.h b/sim/iq2000/arch.h
index ef4cd823c3e..6359118980c 100644
--- a/sim/iq2000/arch.h
+++ b/sim/iq2000/arch.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef IQ2000_ARCH_H
#define IQ2000_ARCH_H
+#define TARGET_BIG_ENDIAN 1
+
+#define WI SI
+#define UWI USI
+#define AI USI
+
+#define IAI USI
+
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_IQ2000, MODEL_MAX
diff --git a/sim/iq2000/cpu.c b/sim/iq2000/cpu.c
index a1ee945257a..d52be00d2da 100644
--- a/sim/iq2000/cpu.c
+++ b/sim/iq2000/cpu.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/iq2000/cpu.h b/sim/iq2000/cpu.h
index ef34033c84b..495e48fb3a7 100644
--- a/sim/iq2000/cpu.h
+++ b/sim/iq2000/cpu.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -277,7 +278,7 @@ struct scache {
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
- f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+ f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_BBV_VARS \
UINT f_opcode; \
@@ -290,7 +291,7 @@ struct scache {
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
- f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+ f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_BGEZ_VARS \
UINT f_opcode; \
@@ -303,7 +304,7 @@ struct scache {
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
- f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+ f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_JALR_VARS \
UINT f_opcode; \
@@ -436,7 +437,7 @@ struct scache {
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
- f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+ f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_CFC0_VARS \
UINT f_opcode; \
diff --git a/sim/iq2000/cpuall.h b/sim/iq2000/cpuall.h
index 4587a6dd70d..55cc6a1c285 100644
--- a/sim/iq2000/cpuall.h
+++ b/sim/iq2000/cpuall.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/iq2000/decode.c b/sim/iq2000/decode.c
index a2d7aec2aad..c9b89152813 100644
--- a/sim/iq2000/decode.c
+++ b/sim/iq2000/decode.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
@@ -105,7 +108,7 @@ static const struct insn_sem iq2000bf_insn_sem[] =
{ IQ2000_INSN_SH, IQ2000BF_INSN_SH, IQ2000BF_SFMT_SH },
{ IQ2000_INSN_SW, IQ2000BF_INSN_SW, IQ2000BF_SFMT_SW },
{ IQ2000_INSN_BREAK, IQ2000BF_INSN_BREAK, IQ2000BF_SFMT_BREAK },
- { IQ2000_INSN_SYSCALL, IQ2000BF_INSN_SYSCALL, IQ2000BF_SFMT_SYSCALL },
+ { IQ2000_INSN_SYSCALL, IQ2000BF_INSN_SYSCALL, IQ2000BF_SFMT_BREAK },
{ IQ2000_INSN_ANDOUI, IQ2000BF_INSN_ANDOUI, IQ2000BF_SFMT_ANDOUI },
{ IQ2000_INSN_ORUI, IQ2000BF_INSN_ORUI, IQ2000BF_SFMT_ANDOUI },
{ IQ2000_INSN_BGTZ, IQ2000BF_INSN_BGTZ, IQ2000BF_SFMT_BGEZ },
@@ -122,68 +125,68 @@ static const struct insn_sem iq2000bf_insn_sem[] =
{ IQ2000_INSN_BC0TL, IQ2000BF_INSN_BC0TL, IQ2000BF_SFMT_BCTXT },
{ IQ2000_INSN_BC3T, IQ2000BF_INSN_BC3T, IQ2000BF_SFMT_BCTXT },
{ IQ2000_INSN_BC3TL, IQ2000BF_INSN_BC3TL, IQ2000BF_SFMT_BCTXT },
- { IQ2000_INSN_CFC0, IQ2000BF_INSN_CFC0, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_CFC1, IQ2000BF_INSN_CFC1, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_CFC2, IQ2000BF_INSN_CFC2, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_CFC3, IQ2000BF_INSN_CFC3, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_CHKHDR, IQ2000BF_INSN_CHKHDR, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_CTC0, IQ2000BF_INSN_CTC0, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_CTC1, IQ2000BF_INSN_CTC1, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_CTC2, IQ2000BF_INSN_CTC2, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_CTC3, IQ2000BF_INSN_CTC3, IQ2000BF_SFMT_SYSCALL },
+ { IQ2000_INSN_CFC0, IQ2000BF_INSN_CFC0, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_CFC1, IQ2000BF_INSN_CFC1, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_CFC2, IQ2000BF_INSN_CFC2, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_CFC3, IQ2000BF_INSN_CFC3, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_CHKHDR, IQ2000BF_INSN_CHKHDR, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_CTC0, IQ2000BF_INSN_CTC0, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_CTC1, IQ2000BF_INSN_CTC1, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_CTC2, IQ2000BF_INSN_CTC2, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_CTC3, IQ2000BF_INSN_CTC3, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_JCR, IQ2000BF_INSN_JCR, IQ2000BF_SFMT_BCTXT },
- { IQ2000_INSN_LUC32, IQ2000BF_INSN_LUC32, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LUC32L, IQ2000BF_INSN_LUC32L, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LUC64, IQ2000BF_INSN_LUC64, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LUC64L, IQ2000BF_INSN_LUC64L, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LUK, IQ2000BF_INSN_LUK, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LULCK, IQ2000BF_INSN_LULCK, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LUM32, IQ2000BF_INSN_LUM32, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LUM32L, IQ2000BF_INSN_LUM32L, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LUM64, IQ2000BF_INSN_LUM64, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LUM64L, IQ2000BF_INSN_LUM64L, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LUR, IQ2000BF_INSN_LUR, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LURL, IQ2000BF_INSN_LURL, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_LUULCK, IQ2000BF_INSN_LUULCK, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_MFC0, IQ2000BF_INSN_MFC0, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_MFC1, IQ2000BF_INSN_MFC1, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_MFC2, IQ2000BF_INSN_MFC2, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_MFC3, IQ2000BF_INSN_MFC3, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_MTC0, IQ2000BF_INSN_MTC0, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_MTC1, IQ2000BF_INSN_MTC1, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_MTC2, IQ2000BF_INSN_MTC2, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_MTC3, IQ2000BF_INSN_MTC3, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_PKRL, IQ2000BF_INSN_PKRL, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_PKRLR1, IQ2000BF_INSN_PKRLR1, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_PKRLR30, IQ2000BF_INSN_PKRLR30, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_RB, IQ2000BF_INSN_RB, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_RBR1, IQ2000BF_INSN_RBR1, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_RBR30, IQ2000BF_INSN_RBR30, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_RFE, IQ2000BF_INSN_RFE, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_RX, IQ2000BF_INSN_RX, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_RXR1, IQ2000BF_INSN_RXR1, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_RXR30, IQ2000BF_INSN_RXR30, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_SLEEP, IQ2000BF_INSN_SLEEP, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_SRRD, IQ2000BF_INSN_SRRD, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_SRRDL, IQ2000BF_INSN_SRRDL, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_SRULCK, IQ2000BF_INSN_SRULCK, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_SRWR, IQ2000BF_INSN_SRWR, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_SRWRU, IQ2000BF_INSN_SRWRU, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_TRAPQFL, IQ2000BF_INSN_TRAPQFL, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_TRAPQNE, IQ2000BF_INSN_TRAPQNE, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_TRAPREL, IQ2000BF_INSN_TRAPREL, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WB, IQ2000BF_INSN_WB, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WBU, IQ2000BF_INSN_WBU, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WBR1, IQ2000BF_INSN_WBR1, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WBR1U, IQ2000BF_INSN_WBR1U, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WBR30, IQ2000BF_INSN_WBR30, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WBR30U, IQ2000BF_INSN_WBR30U, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WX, IQ2000BF_INSN_WX, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WXU, IQ2000BF_INSN_WXU, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WXR1, IQ2000BF_INSN_WXR1, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WXR1U, IQ2000BF_INSN_WXR1U, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WXR30, IQ2000BF_INSN_WXR30, IQ2000BF_SFMT_SYSCALL },
- { IQ2000_INSN_WXR30U, IQ2000BF_INSN_WXR30U, IQ2000BF_SFMT_SYSCALL },
+ { IQ2000_INSN_LUC32, IQ2000BF_INSN_LUC32, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LUC32L, IQ2000BF_INSN_LUC32L, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LUC64, IQ2000BF_INSN_LUC64, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LUC64L, IQ2000BF_INSN_LUC64L, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LUK, IQ2000BF_INSN_LUK, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LULCK, IQ2000BF_INSN_LULCK, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LUM32, IQ2000BF_INSN_LUM32, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LUM32L, IQ2000BF_INSN_LUM32L, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LUM64, IQ2000BF_INSN_LUM64, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LUM64L, IQ2000BF_INSN_LUM64L, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LUR, IQ2000BF_INSN_LUR, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LURL, IQ2000BF_INSN_LURL, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_LUULCK, IQ2000BF_INSN_LUULCK, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_MFC0, IQ2000BF_INSN_MFC0, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_MFC1, IQ2000BF_INSN_MFC1, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_MFC2, IQ2000BF_INSN_MFC2, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_MFC3, IQ2000BF_INSN_MFC3, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_MTC0, IQ2000BF_INSN_MTC0, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_MTC1, IQ2000BF_INSN_MTC1, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_MTC2, IQ2000BF_INSN_MTC2, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_MTC3, IQ2000BF_INSN_MTC3, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_PKRL, IQ2000BF_INSN_PKRL, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_PKRLR1, IQ2000BF_INSN_PKRLR1, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_PKRLR30, IQ2000BF_INSN_PKRLR30, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_RB, IQ2000BF_INSN_RB, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_RBR1, IQ2000BF_INSN_RBR1, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_RBR30, IQ2000BF_INSN_RBR30, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_RFE, IQ2000BF_INSN_RFE, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_RX, IQ2000BF_INSN_RX, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_RXR1, IQ2000BF_INSN_RXR1, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_RXR30, IQ2000BF_INSN_RXR30, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_SLEEP, IQ2000BF_INSN_SLEEP, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_SRRD, IQ2000BF_INSN_SRRD, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_SRRDL, IQ2000BF_INSN_SRRDL, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_SRULCK, IQ2000BF_INSN_SRULCK, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_SRWR, IQ2000BF_INSN_SRWR, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_SRWRU, IQ2000BF_INSN_SRWRU, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_TRAPQFL, IQ2000BF_INSN_TRAPQFL, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_TRAPQNE, IQ2000BF_INSN_TRAPQNE, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_TRAPREL, IQ2000BF_INSN_TRAPREL, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WB, IQ2000BF_INSN_WB, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WBU, IQ2000BF_INSN_WBU, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WBR1, IQ2000BF_INSN_WBR1, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WBR1U, IQ2000BF_INSN_WBR1U, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WBR30, IQ2000BF_INSN_WBR30, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WBR30U, IQ2000BF_INSN_WBR30U, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WX, IQ2000BF_INSN_WX, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WXU, IQ2000BF_INSN_WXU, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WXR1, IQ2000BF_INSN_WXR1, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WXR1U, IQ2000BF_INSN_WXR1U, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WXR30, IQ2000BF_INSN_WXR30, IQ2000BF_SFMT_CFC0 },
+ { IQ2000_INSN_WXR30U, IQ2000BF_INSN_WXR30U, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LDW, IQ2000BF_INSN_LDW, IQ2000BF_SFMT_LDW },
{ IQ2000_INSN_SDW, IQ2000BF_INSN_SDW, IQ2000BF_SFMT_SDW },
{ IQ2000_INSN_J, IQ2000BF_INSN_J, IQ2000BF_SFMT_J },
@@ -320,7 +323,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 12 :
if ((entire_insn & 0xfc00003f) == 0xc)
- { itype = IQ2000BF_INSN_SYSCALL; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_SYSCALL; goto extract_sfmt_break; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 13 :
if ((entire_insn & 0xffffffff) == 0xd)
@@ -328,7 +331,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 14 :
if ((entire_insn & 0xfc00003f) == 0xe)
- { itype = IQ2000BF_INSN_SLEEP; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_SLEEP; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 16 :
if ((entire_insn & 0xfc0007ff) == 0x20)
@@ -464,28 +467,28 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 4 : /* fall through */
case 6 :
if ((entire_insn & 0xffe007ff) == 0x40000000)
- { itype = IQ2000BF_INSN_MFC0; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_MFC0; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 8 : /* fall through */
case 10 : /* fall through */
case 12 : /* fall through */
case 14 :
if ((entire_insn & 0xffe007ff) == 0x40400000)
- { itype = IQ2000BF_INSN_CFC0; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_CFC0; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 16 : /* fall through */
case 18 : /* fall through */
case 20 : /* fall through */
case 22 :
if ((entire_insn & 0xffe007ff) == 0x40800000)
- { itype = IQ2000BF_INSN_MTC0; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_MTC0; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 24 : /* fall through */
case 26 : /* fall through */
case 28 : /* fall through */
case 30 :
if ((entire_insn & 0xffe007ff) == 0x40c00000)
- { itype = IQ2000BF_INSN_CTC0; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_CTC0; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 32 : /* fall through */
case 33 :
@@ -509,7 +512,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 65 :
if ((entire_insn & 0xffffffff) == 0x42000010)
- { itype = IQ2000BF_INSN_RFE; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_RFE; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -521,19 +524,19 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x44000000)
- { itype = IQ2000BF_INSN_MFC1; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_MFC1; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x44400000)
- { itype = IQ2000BF_INSN_CFC1; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_CFC1; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2 :
if ((entire_insn & 0xffe007ff) == 0x44800000)
- { itype = IQ2000BF_INSN_MTC1; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_MTC1; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 3 :
if ((entire_insn & 0xffe007ff) == 0x44c00000)
- { itype = IQ2000BF_INSN_CTC1; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_CTC1; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -550,86 +553,86 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x48000000)
- { itype = IQ2000BF_INSN_MFC2; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_MFC2; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x48800000)
- { itype = IQ2000BF_INSN_MTC2; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_MTC2; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
case 32 :
if ((entire_insn & 0xffe0ffff) == 0x48200000)
- { itype = IQ2000BF_INSN_LUULCK; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUULCK; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 33 :
if ((entire_insn & 0xffe007ff) == 0x48200001)
- { itype = IQ2000BF_INSN_LUR; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUR; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 34 :
if ((entire_insn & 0xffe007ff) == 0x48200002)
- { itype = IQ2000BF_INSN_LUM32; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUM32; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 35 :
if ((entire_insn & 0xffe007ff) == 0x48200003)
- { itype = IQ2000BF_INSN_LUC32; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUC32; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 36 :
if ((entire_insn & 0xffe0ffff) == 0x48200004)
- { itype = IQ2000BF_INSN_LULCK; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LULCK; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 37 :
if ((entire_insn & 0xffe007ff) == 0x48200005)
- { itype = IQ2000BF_INSN_LURL; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LURL; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 38 :
if ((entire_insn & 0xffe007ff) == 0x48200006)
- { itype = IQ2000BF_INSN_LUM32L; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUM32L; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 39 :
if ((entire_insn & 0xffe007ff) == 0x48200007)
- { itype = IQ2000BF_INSN_LUC32L; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUC32L; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 40 :
if ((entire_insn & 0xffe007ff) == 0x48200008)
- { itype = IQ2000BF_INSN_LUK; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUK; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 42 :
if ((entire_insn & 0xffe007ff) == 0x4820000a)
- { itype = IQ2000BF_INSN_LUM64; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUM64; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 43 :
if ((entire_insn & 0xffe007ff) == 0x4820000b)
- { itype = IQ2000BF_INSN_LUC64; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUC64; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 46 :
if ((entire_insn & 0xffe007ff) == 0x4820000e)
- { itype = IQ2000BF_INSN_LUM64L; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUM64L; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 47 :
if ((entire_insn & 0xffe007ff) == 0x4820000f)
- { itype = IQ2000BF_INSN_LUC64L; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_LUC64L; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 48 :
if ((entire_insn & 0xffe0ffff) == 0x48200010)
- { itype = IQ2000BF_INSN_SRRD; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_SRRD; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 49 :
if ((entire_insn & 0xffe007ff) == 0x48200011)
- { itype = IQ2000BF_INSN_SRWR; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_SRWR; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 52 :
if ((entire_insn & 0xffe0ffff) == 0x48200014)
- { itype = IQ2000BF_INSN_SRRDL; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_SRRDL; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 53 :
if ((entire_insn & 0xffe007ff) == 0x48200015)
- { itype = IQ2000BF_INSN_SRWRU; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_SRWRU; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 54 :
if ((entire_insn & 0xffe0ffff) == 0x48200016)
- { itype = IQ2000BF_INSN_SRULCK; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_SRULCK; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 64 :
{
@@ -638,11 +641,11 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x48400000)
- { itype = IQ2000BF_INSN_CFC2; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_CFC2; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x48c00000)
- { itype = IQ2000BF_INSN_CTC2; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_CTC2; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -657,7 +660,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x4c000000)
- { itype = IQ2000BF_INSN_MFC3; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_MFC3; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 4 :
{
@@ -666,15 +669,15 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x4c200000)
- { itype = IQ2000BF_INSN_WB; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_WB; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x4c200004)
- { itype = IQ2000BF_INSN_RB; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_RB; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2 :
if ((entire_insn & 0xffffffff) == 0x4c200008)
- { itype = IQ2000BF_INSN_TRAPQFL; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_TRAPQFL; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -686,11 +689,11 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x4c200001)
- { itype = IQ2000BF_INSN_WBU; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_WBU; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffffffff) == 0x4c200009)
- { itype = IQ2000BF_INSN_TRAPQNE; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_TRAPQNE; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -702,15 +705,15 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x4c200002)
- { itype = IQ2000BF_INSN_WX; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_WX; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x4c200006)
- { itype = IQ2000BF_INSN_RX; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_RX; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2 :
if ((entire_insn & 0xffe0ffff) == 0x4c20000a)
- { itype = IQ2000BF_INSN_TRAPREL; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_TRAPREL; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -722,26 +725,26 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x4c200003)
- { itype = IQ2000BF_INSN_WXU; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_WXU; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x4c200007)
- { itype = IQ2000BF_INSN_PKRL; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_PKRL; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
case 8 :
if ((entire_insn & 0xffe007ff) == 0x4c400000)
- { itype = IQ2000BF_INSN_CFC3; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_CFC3; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 16 :
if ((entire_insn & 0xffe007ff) == 0x4c800000)
- { itype = IQ2000BF_INSN_MTC3; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_MTC3; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 24 :
if ((entire_insn & 0xffe007ff) == 0x4cc00000)
- { itype = IQ2000BF_INSN_CTC3; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_CTC3; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 32 : /* fall through */
case 33 : /* fall through */
@@ -772,64 +775,64 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
}
case 36 :
if ((entire_insn & 0xffe007ff) == 0x4d200000)
- { itype = IQ2000BF_INSN_CHKHDR; goto extract_sfmt_syscall; }
+ { itype = IQ2000BF_INSN_CHKHDR; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 64 : /* fall through */
case 65 : /* fall through */
case 66 : /* fall through */
- case 67 : itype = IQ2000BF_INSN_WBR1; goto extract_sfmt_syscall;
+ case 67 : itype = IQ2000BF_INSN_WBR1; goto extract_sfmt_cfc0;
case 68 : /* fall through */
case 69 : /* fall through */
case 70 : /* fall through */
- case 71 : itype = IQ2000BF_INSN_WBR1U; goto extract_sfmt_syscall;
+ case 71 : itype = IQ2000BF_INSN_WBR1U; goto extract_sfmt_cfc0;
case 72 : /* fall through */
case 73 : /* fall through */
case 74 : /* fall through */
- case 75 : itype = IQ2000BF_INSN_WBR30; goto extract_sfmt_syscall;
+ case 75 : itype = IQ2000BF_INSN_WBR30; goto extract_sfmt_cfc0;
case 76 : /* fall through */
case 77 : /* fall through */
case 78 : /* fall through */
- case 79 : itype = IQ2000BF_INSN_WBR30U; goto extract_sfmt_syscall;
+ case 79 : itype = IQ2000BF_INSN_WBR30U; goto extract_sfmt_cfc0;
case 80 : /* fall through */
case 81 : /* fall through */
case 82 : /* fall through */
- case 83 : itype = IQ2000BF_INSN_WXR1; goto extract_sfmt_syscall;
+ case 83 : itype = IQ2000BF_INSN_WXR1; goto extract_sfmt_cfc0;
case 84 : /* fall through */
case 85 : /* fall through */
case 86 : /* fall through */
- case 87 : itype = IQ2000BF_INSN_WXR1U; goto extract_sfmt_syscall;
+ case 87 : itype = IQ2000BF_INSN_WXR1U; goto extract_sfmt_cfc0;
case 88 : /* fall through */
case 89 : /* fall through */
case 90 : /* fall through */
- case 91 : itype = IQ2000BF_INSN_WXR30; goto extract_sfmt_syscall;
+ case 91 : itype = IQ2000BF_INSN_WXR30; goto extract_sfmt_cfc0;
case 92 : /* fall through */
case 93 : /* fall through */
case 94 : /* fall through */
- case 95 : itype = IQ2000BF_INSN_WXR30U; goto extract_sfmt_syscall;
+ case 95 : itype = IQ2000BF_INSN_WXR30U; goto extract_sfmt_cfc0;
case 96 : /* fall through */
case 97 : /* fall through */
case 98 : /* fall through */
- case 99 : itype = IQ2000BF_INSN_RBR1; goto extract_sfmt_syscall;
+ case 99 : itype = IQ2000BF_INSN_RBR1; goto extract_sfmt_cfc0;
case 104 : /* fall through */
case 105 : /* fall through */
case 106 : /* fall through */
- case 107 : itype = IQ2000BF_INSN_RBR30; goto extract_sfmt_syscall;
+ case 107 : itype = IQ2000BF_INSN_RBR30; goto extract_sfmt_cfc0;
case 112 : /* fall through */
case 113 : /* fall through */
case 114 : /* fall through */
- case 115 : itype = IQ2000BF_INSN_RXR1; goto extract_sfmt_syscall;
+ case 115 : itype = IQ2000BF_INSN_RXR1; goto extract_sfmt_cfc0;
case 116 : /* fall through */
case 117 : /* fall through */
case 118 : /* fall through */
- case 119 : itype = IQ2000BF_INSN_PKRLR1; goto extract_sfmt_syscall;
+ case 119 : itype = IQ2000BF_INSN_PKRLR1; goto extract_sfmt_cfc0;
case 120 : /* fall through */
case 121 : /* fall through */
case 122 : /* fall through */
- case 123 : itype = IQ2000BF_INSN_RXR30; goto extract_sfmt_syscall;
+ case 123 : itype = IQ2000BF_INSN_RXR30; goto extract_sfmt_cfc0;
case 124 : /* fall through */
case 125 : /* fall through */
case 126 : /* fall through */
- case 127 : itype = IQ2000BF_INSN_PKRLR30; goto extract_sfmt_syscall;
+ case 127 : itype = IQ2000BF_INSN_PKRLR30; goto extract_sfmt_cfc0;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
@@ -1070,7 +1073,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
- f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4))));
+ f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4))));
/* Record the fields for the semantic handler. */
FLD (f_rt) = f_rt;
@@ -1099,7 +1102,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
- f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4))));
+ f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4))));
/* Record the fields for the semantic handler. */
FLD (f_rs) = f_rs;
@@ -1126,7 +1129,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_offset;
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
- f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4))));
+ f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4))));
/* Record the fields for the semantic handler. */
FLD (f_rs) = f_rs;
@@ -1152,7 +1155,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_offset;
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
- f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4))));
+ f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4))));
/* Record the fields for the semantic handler. */
FLD (f_rs) = f_rs;
@@ -1391,19 +1394,6 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
}
#endif
-#undef FLD
- return idesc;
- }
-
- extract_sfmt_syscall:
- {
- const IDESC *idesc = &iq2000bf_insn_data[itype];
-#define FLD(f) abuf->fields.sfmt_empty.f
-
-
- /* Record the fields for the semantic handler. */
- CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_syscall", (char *) 0));
-
#undef FLD
return idesc;
}
@@ -1466,6 +1456,19 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for the semantic handler. */
CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bctxt", (char *) 0));
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cfc0:
+ {
+ const IDESC *idesc = &iq2000bf_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfc0", (char *) 0));
+
#undef FLD
return idesc;
}
diff --git a/sim/iq2000/decode.h b/sim/iq2000/decode.h
index d6b848a629d..95ff05ec85b 100644
--- a/sim/iq2000/decode.h
+++ b/sim/iq2000/decode.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -80,8 +81,8 @@ typedef enum iq2000bf_sfmt_type {
, IQ2000BF_SFMT_BBI, IQ2000BF_SFMT_BBV, IQ2000BF_SFMT_BGEZ, IQ2000BF_SFMT_BGEZAL
, IQ2000BF_SFMT_JALR, IQ2000BF_SFMT_JR, IQ2000BF_SFMT_LB, IQ2000BF_SFMT_LH
, IQ2000BF_SFMT_LUI, IQ2000BF_SFMT_LW, IQ2000BF_SFMT_SB, IQ2000BF_SFMT_SH
- , IQ2000BF_SFMT_SW, IQ2000BF_SFMT_BREAK, IQ2000BF_SFMT_SYSCALL, IQ2000BF_SFMT_ANDOUI
- , IQ2000BF_SFMT_MRGB, IQ2000BF_SFMT_BCTXT, IQ2000BF_SFMT_LDW, IQ2000BF_SFMT_SDW
+ , IQ2000BF_SFMT_SW, IQ2000BF_SFMT_BREAK, IQ2000BF_SFMT_ANDOUI, IQ2000BF_SFMT_MRGB
+ , IQ2000BF_SFMT_BCTXT, IQ2000BF_SFMT_CFC0, IQ2000BF_SFMT_LDW, IQ2000BF_SFMT_SDW
, IQ2000BF_SFMT_J, IQ2000BF_SFMT_JAL
} IQ2000BF_SFMT_TYPE;
diff --git a/sim/iq2000/model.c b/sim/iq2000/model.c
index e637cee242e..bfac2f8d0a7 100644
--- a/sim/iq2000/model.c
+++ b/sim/iq2000/model.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/iq2000/sem-switch.c b/sim/iq2000/sem-switch.c
index 5d0ce7505fd..6e6cc9b970b 100644
--- a/sim/iq2000/sem-switch.c
+++ b/sim/iq2000/sem-switch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -1809,10 +1810,10 @@ do_break (current_cpu, pc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
- IADDR pc = abuf->addr;
+ IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
- do_syscall (current_cpu, pc);
+do_syscall (current_cpu, pc);
#undef FLD
}
diff --git a/sim/iq2000/sem.c b/sim/iq2000/sem.c
index c1ea01f46cb..d56e4511c39 100644
--- a/sim/iq2000/sem.c
+++ b/sim/iq2000/sem.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -1747,10 +1748,10 @@ SEM_FN_NAME (iq2000bf,syscall) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
- IADDR pc = abuf->addr;
+ IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
- do_syscall (current_cpu, pc);
+do_syscall (current_cpu, pc);
return vpc;
#undef FLD
diff --git a/sim/lm32/arch.c b/sim/lm32/arch.c
index 470075c4c26..a3baafa0d4a 100644
--- a/sim/lm32/arch.c
+++ b/sim/lm32/arch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/lm32/arch.h b/sim/lm32/arch.h
index e31c81ebd1e..65a9dcfcdf7 100644
--- a/sim/lm32/arch.h
+++ b/sim/lm32/arch.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef LM32_ARCH_H
#define LM32_ARCH_H
+#define TARGET_BIG_ENDIAN 1
+
+#define WI SI
+#define UWI USI
+#define AI USI
+
+#define IAI USI
+
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_LM32, MODEL_MAX
diff --git a/sim/lm32/cpu.c b/sim/lm32/cpu.c
index 29e46655247..26a568140a8 100644
--- a/sim/lm32/cpu.c
+++ b/sim/lm32/cpu.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/lm32/cpu.h b/sim/lm32/cpu.h
index 805f1eb7d30..01922213a90 100644
--- a/sim/lm32/cpu.h
+++ b/sim/lm32/cpu.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -247,7 +248,7 @@ struct scache {
#define EXTRACT_IFMT_BI_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
- f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4)))); \
+ f_call = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) & (67108863))) << (2))) ^ (134217728))) - (134217728)))); \
#define EXTRACT_IFMT_BE_VARS \
UINT f_opcode; \
@@ -260,7 +261,7 @@ struct scache {
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
- f_branch = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (16))) >> (14)))); \
+ f_branch = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) & (65535))) << (2))) ^ (131072))) - (131072)))); \
#define EXTRACT_IFMT_ORI_VARS \
UINT f_opcode; \
diff --git a/sim/lm32/cpuall.h b/sim/lm32/cpuall.h
index e6d5a19a15e..801c5cf75e8 100644
--- a/sim/lm32/cpuall.h
+++ b/sim/lm32/cpuall.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/lm32/decode.c b/sim/lm32/decode.c
index 8107074dadf..826fd586684 100644
--- a/sim/lm32/decode.c
+++ b/sim/lm32/decode.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
@@ -474,7 +477,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bi.f
SI f_call;
- f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4))));
+ f_call = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) & (67108863))) << (2))) ^ (134217728))) - (134217728))));
/* Record the fields for the semantic handler. */
FLD (i_call) = f_call;
@@ -495,7 +498,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
- f_branch = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (16))) >> (14))));
+ f_branch = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) & (65535))) << (2))) ^ (131072))) - (131072))));
/* Record the fields for the semantic handler. */
FLD (f_r0) = f_r0;
@@ -531,7 +534,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bi.f
SI f_call;
- f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4))));
+ f_call = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) & (67108863))) << (2))) ^ (134217728))) - (134217728))));
/* Record the fields for the semantic handler. */
FLD (i_call) = f_call;
diff --git a/sim/lm32/decode.h b/sim/lm32/decode.h
index e1de1961e96..139b03b6745 100644
--- a/sim/lm32/decode.h
+++ b/sim/lm32/decode.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/lm32/model.c b/sim/lm32/model.c
index 60d223aacfc..0bc1650dd49 100644
--- a/sim/lm32/model.c
+++ b/sim/lm32/model.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/lm32/sem-switch.c b/sim/lm32/sem-switch.c
index 8a13d04da05..972f7af8a7e 100644
--- a/sim/lm32/sem-switch.c
+++ b/sim/lm32/sem-switch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/lm32/sem.c b/sim/lm32/sem.c
index 02fc5f2c481..5b630c34054 100644
--- a/sim/lm32/sem.c
+++ b/sim/lm32/sem.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/arch.c b/sim/m32r/arch.c
index fbdea53d4aa..f228155942d 100644
--- a/sim/m32r/arch.c
+++ b/sim/m32r/arch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/arch.h b/sim/m32r/arch.h
index 4a739c16444..426e0134f2f 100644
--- a/sim/m32r/arch.h
+++ b/sim/m32r/arch.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef M32R_ARCH_H
#define M32R_ARCH_H
+#define TARGET_BIG_ENDIAN 1
+
+#define WI SI
+#define UWI USI
+#define AI USI
+
+#define IAI USI
+
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_M32R_D, MODEL_TEST, MODEL_M32RX, MODEL_M32R2
diff --git a/sim/m32r/cpu.c b/sim/m32r/cpu.c
index 4e47d617b96..17ce9a9bb86 100644
--- a/sim/m32r/cpu.c
+++ b/sim/m32r/cpu.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h
index 013ad227422..94ac62b8111 100644
--- a/sim/m32r/cpu.h
+++ b/sim/m32r/cpu.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -397,7 +398,7 @@ struct scache {
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); \
#define EXTRACT_IFMT_BC24_VARS \
UINT f_op1; \
@@ -408,7 +409,7 @@ struct scache {
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op1; \
@@ -423,7 +424,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQZ_VARS \
UINT f_op1; \
@@ -438,7 +439,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_CMP_VARS \
UINT f_op1; \
diff --git a/sim/m32r/cpu2.c b/sim/m32r/cpu2.c
index d117ab1aa38..b95aca91196 100644
--- a/sim/m32r/cpu2.c
+++ b/sim/m32r/cpu2.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/cpu2.h b/sim/m32r/cpu2.h
index 93481524009..612113ddce5 100644
--- a/sim/m32r/cpu2.h
+++ b/sim/m32r/cpu2.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -428,7 +429,7 @@ struct scache {
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); \
#define EXTRACT_IFMT_BC24_VARS \
UINT f_op1; \
@@ -439,7 +440,7 @@ struct scache {
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op1; \
@@ -454,7 +455,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQZ_VARS \
UINT f_op1; \
@@ -469,7 +470,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_CMP_VARS \
UINT f_op1; \
diff --git a/sim/m32r/cpuall.h b/sim/m32r/cpuall.h
index 5f747590557..3258ae44952 100644
--- a/sim/m32r/cpuall.h
+++ b/sim/m32r/cpuall.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/cpux.c b/sim/m32r/cpux.c
index 3650ec6fc72..f443965f8a7 100644
--- a/sim/m32r/cpux.c
+++ b/sim/m32r/cpux.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
index 7c13d77e4df..aabe433af59 100644
--- a/sim/m32r/cpux.h
+++ b/sim/m32r/cpux.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -428,7 +429,7 @@ struct scache {
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); \
#define EXTRACT_IFMT_BC24_VARS \
UINT f_op1; \
@@ -439,7 +440,7 @@ struct scache {
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op1; \
@@ -454,7 +455,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQZ_VARS \
UINT f_op1; \
@@ -469,7 +470,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_CMP_VARS \
UINT f_op1; \
diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
index e6c37844369..7d802a3fa07 100644
--- a/sim/m32r/decode.c
+++ b/sim/m32r/decode.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
@@ -844,7 +847,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -867,7 +870,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@@ -894,7 +897,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r1) = f_r1;
@@ -925,7 +928,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_disp16;
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
@@ -951,7 +954,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -975,7 +978,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@@ -999,7 +1002,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -1022,7 +1025,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h
index e70f5be59b7..238f10a74ab 100644
--- a/sim/m32r/decode.h
+++ b/sim/m32r/decode.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/decode2.c b/sim/m32r/decode2.c
index 4d759e962ad..60909af1887 100644
--- a/sim/m32r/decode2.c
+++ b/sim/m32r/decode2.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
/* Insn can't be executed in parallel.
Or is that "do NOt Pass to Air defense Radar"? :-) */
@@ -1033,7 +1036,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -1056,7 +1059,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@@ -1083,7 +1086,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r1) = f_r1;
@@ -1114,7 +1117,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_disp16;
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
@@ -1140,7 +1143,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -1164,7 +1167,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@@ -1188,7 +1191,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -1212,7 +1215,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@@ -1236,7 +1239,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -1259,7 +1262,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
diff --git a/sim/m32r/decode2.h b/sim/m32r/decode2.h
index 6e23766e992..47c94c91048 100644
--- a/sim/m32r/decode2.h
+++ b/sim/m32r/decode2.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
index 7f2496b89d7..ad2c3f01dac 100644
--- a/sim/m32r/decodex.c
+++ b/sim/m32r/decodex.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
/* Insn can't be executed in parallel.
Or is that "do NOt Pass to Air defense Radar"? :-) */
@@ -974,7 +977,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -997,7 +1000,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@@ -1024,7 +1027,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r1) = f_r1;
@@ -1055,7 +1058,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_disp16;
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
- f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
+ f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
@@ -1081,7 +1084,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -1105,7 +1108,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@@ -1129,7 +1132,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -1153,7 +1156,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@@ -1177,7 +1180,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
- f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+ f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@@ -1200,7 +1203,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
- f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
+ f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
diff --git a/sim/m32r/decodex.h b/sim/m32r/decodex.h
index 5bfddddd639..82be1297df6 100644
--- a/sim/m32r/decodex.h
+++ b/sim/m32r/decodex.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/model.c b/sim/m32r/model.c
index eda843677a7..1789720aa8c 100644
--- a/sim/m32r/model.c
+++ b/sim/m32r/model.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/model2.c b/sim/m32r/model2.c
index c616663f5db..ae0d1ac9bed 100644
--- a/sim/m32r/model2.c
+++ b/sim/m32r/model2.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/modelx.c b/sim/m32r/modelx.c
index 497804c6889..7e4ba5da7a7 100644
--- a/sim/m32r/modelx.c
+++ b/sim/m32r/modelx.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c
index 363017b6527..d35e9a46973 100644
--- a/sim/m32r/sem-switch.c
+++ b/sim/m32r/sem-switch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c
index b124e18b7d9..cbd596325ec 100644
--- a/sim/m32r/sem.c
+++ b/sim/m32r/sem.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/sem2-switch.c b/sim/m32r/sem2-switch.c
index 21351326915..3ef73540ec0 100644
--- a/sim/m32r/sem2-switch.c
+++ b/sim/m32r/sem2-switch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/m32r/semx-switch.c b/sim/m32r/semx-switch.c
index 6a1d6eab8e0..e22305a17eb 100644
--- a/sim/m32r/semx-switch.c
+++ b/sim/m32r/semx-switch.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2023 Free Software Foundation, Inc.
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
diff --git a/sim/or1k/cpu.h b/sim/or1k/cpu.h
index cbcd55e8ce3..a802c20f71c 100644
--- a/sim/or1k/cpu.h
+++ b/sim/or1k/cpu.h
@@ -4647,7 +4647,7 @@ struct scache {
#define EXTRACT_IFMT_L_J_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
- f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc)); \
+ f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) * (4))) + (pc)); \
#define EXTRACT_IFMT_L_ADRP_VARS \
UINT f_opcode; \
@@ -4658,7 +4658,7 @@ struct scache {
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
- f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) << (13)); \
+ f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) * (8192)); \
#define EXTRACT_IFMT_L_JR_VARS \
UINT f_opcode; \
diff --git a/sim/or1k/decode.c b/sim/or1k/decode.c
index 4388bfea8d8..c04afe5cb31 100644
--- a/sim/or1k/decode.c
+++ b/sim/or1k/decode.c
@@ -27,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
@@ -240,7 +242,7 @@ or1k32bf_init_idesc_table (SIM_CPU *cpu)
init_idesc (cpu, id, t);
/* Now fill in the values for the chosen cpu. */
- for (t = or1k32bf_insn_sem, tend = t + sizeof (or1k32bf_insn_sem) / sizeof (*t);
+ for (t = or1k32bf_insn_sem, tend = t + ARRAY_SIZE (or1k32bf_insn_sem);
t != tend; ++t)
{
init_idesc (cpu, & table[t->index], t);
@@ -1918,7 +1920,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_l_j.f
USI f_disp26;
- f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc));
+ f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp26) = f_disp26;
@@ -1937,7 +1939,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
USI f_disp21;
f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
- f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) << (13));
+ f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) * (8192));
/* Record the fields for the semantic handler. */
FLD (f_r1) = f_r1;
@@ -1955,7 +1957,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_l_j.f
USI f_disp26;
- f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc));
+ f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp26) = f_disp26;
@@ -2006,7 +2008,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_l_j.f
USI f_disp26;
- f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc));
+ f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp26) = f_disp26;
diff --git a/sim/or1k/sem-switch.c b/sim/or1k/sem-switch.c
index 753c2b4cdb2..b63add8817b 100644
--- a/sim/or1k/sem-switch.c
+++ b/sim/or1k/sem-switch.c
@@ -199,7 +199,7 @@ This file is part of the GNU simulators.
/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
off frills like tracing and profiling. */
-/* FIXME: A better way would be to have TRACE_RESULT check for something
+/* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something
that can cause it to be optimized out. Another way would be to emit
special handlers into the instruction "stream". */
diff --git a/sim/semcrisv32f-switch.c b/sim/semcrisv32f-switch.c
new file mode 100644
index 00000000000..8dd455c94e9
--- /dev/null
+++ b/sim/semcrisv32f-switch.c
@@ -0,0 +1,14120 @@
+/* Simulator instruction semantics for crisv32f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2023 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+ /* The labels have the case they have because the enum of insn types
+ is all uppercase and in the non-stdc case the insn symbol is built
+ into the enum name. */
+
+ static struct {
+ int index;
+ void *label;
+ } labels[] = {
+ { CRISV32F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+ { CRISV32F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+ { CRISV32F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+ { CRISV32F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+ { CRISV32F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+ { CRISV32F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+ { CRISV32F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
+ { CRISV32F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
+ { CRISV32F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
+ { CRISV32F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
+ { CRISV32F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
+ { CRISV32F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
+ { CRISV32F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
+ { CRISV32F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
+ { CRISV32F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
+ { CRISV32F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
+ { CRISV32F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
+ { CRISV32F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
+ { CRISV32F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
+ { CRISV32F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
+ { CRISV32F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
+ { CRISV32F_INSN_ADDQ, && case_sem_INSN_ADDQ },
+ { CRISV32F_INSN_SUBQ, && case_sem_INSN_SUBQ },
+ { CRISV32F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
+ { CRISV32F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
+ { CRISV32F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
+ { CRISV32F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
+ { CRISV32F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
+ { CRISV32F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
+ { CRISV32F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
+ { CRISV32F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
+ { CRISV32F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
+ { CRISV32F_INSN_CMPQ, && case_sem_INSN_CMPQ },
+ { CRISV32F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
+ { CRISV32F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
+ { CRISV32F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
+ { CRISV32F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
+ { CRISV32F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
+ { CRISV32F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
+ { CRISV32F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
+ { CRISV32F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
+ { CRISV32F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
+ { CRISV32F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
+ { CRISV32F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
+ { CRISV32F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
+ { CRISV32F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
+ { CRISV32F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
+ { CRISV32F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
+ { CRISV32F_INSN_MOVE_R_SPRV32, && case_sem_INSN_MOVE_R_SPRV32 },
+ { CRISV32F_INSN_MOVE_SPR_RV32, && case_sem_INSN_MOVE_SPR_RV32 },
+ { CRISV32F_INSN_MOVE_M_SPRV32, && case_sem_INSN_MOVE_M_SPRV32 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P2, && case_sem_INSN_MOVE_C_SPRV32_P2 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P3, && case_sem_INSN_MOVE_C_SPRV32_P3 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P5, && case_sem_INSN_MOVE_C_SPRV32_P5 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P6, && case_sem_INSN_MOVE_C_SPRV32_P6 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P7, && case_sem_INSN_MOVE_C_SPRV32_P7 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P9, && case_sem_INSN_MOVE_C_SPRV32_P9 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P10, && case_sem_INSN_MOVE_C_SPRV32_P10 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P11, && case_sem_INSN_MOVE_C_SPRV32_P11 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P12, && case_sem_INSN_MOVE_C_SPRV32_P12 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P13, && case_sem_INSN_MOVE_C_SPRV32_P13 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P14, && case_sem_INSN_MOVE_C_SPRV32_P14 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P15, && case_sem_INSN_MOVE_C_SPRV32_P15 },
+ { CRISV32F_INSN_MOVE_SPR_MV32, && case_sem_INSN_MOVE_SPR_MV32 },
+ { CRISV32F_INSN_MOVE_SS_R, && case_sem_INSN_MOVE_SS_R },
+ { CRISV32F_INSN_MOVE_R_SS, && case_sem_INSN_MOVE_R_SS },
+ { CRISV32F_INSN_MOVEM_R_M_V32, && case_sem_INSN_MOVEM_R_M_V32 },
+ { CRISV32F_INSN_MOVEM_M_R_V32, && case_sem_INSN_MOVEM_M_R_V32 },
+ { CRISV32F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
+ { CRISV32F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
+ { CRISV32F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
+ { CRISV32F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
+ { CRISV32F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
+ { CRISV32F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
+ { CRISV32F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
+ { CRISV32F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
+ { CRISV32F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
+ { CRISV32F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
+ { CRISV32F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
+ { CRISV32F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
+ { CRISV32F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
+ { CRISV32F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
+ { CRISV32F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
+ { CRISV32F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
+ { CRISV32F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
+ { CRISV32F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
+ { CRISV32F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
+ { CRISV32F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
+ { CRISV32F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
+ { CRISV32F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
+ { CRISV32F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
+ { CRISV32F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
+ { CRISV32F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
+ { CRISV32F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
+ { CRISV32F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
+ { CRISV32F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
+ { CRISV32F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
+ { CRISV32F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
+ { CRISV32F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
+ { CRISV32F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
+ { CRISV32F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
+ { CRISV32F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
+ { CRISV32F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
+ { CRISV32F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
+ { CRISV32F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
+ { CRISV32F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
+ { CRISV32F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
+ { CRISV32F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
+ { CRISV32F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
+ { CRISV32F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
+ { CRISV32F_INSN_ADDC_R, && case_sem_INSN_ADDC_R },
+ { CRISV32F_INSN_ADDC_M, && case_sem_INSN_ADDC_M },
+ { CRISV32F_INSN_ADDC_C, && case_sem_INSN_ADDC_C },
+ { CRISV32F_INSN_LAPC_D, && case_sem_INSN_LAPC_D },
+ { CRISV32F_INSN_LAPCQ, && case_sem_INSN_LAPCQ },
+ { CRISV32F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
+ { CRISV32F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
+ { CRISV32F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
+ { CRISV32F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
+ { CRISV32F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
+ { CRISV32F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
+ { CRISV32F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
+ { CRISV32F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
+ { CRISV32F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
+ { CRISV32F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
+ { CRISV32F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
+ { CRISV32F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
+ { CRISV32F_INSN_MULS_B, && case_sem_INSN_MULS_B },
+ { CRISV32F_INSN_MULS_W, && case_sem_INSN_MULS_W },
+ { CRISV32F_INSN_MULS_D, && case_sem_INSN_MULS_D },
+ { CRISV32F_INSN_MULU_B, && case_sem_INSN_MULU_B },
+ { CRISV32F_INSN_MULU_W, && case_sem_INSN_MULU_W },
+ { CRISV32F_INSN_MULU_D, && case_sem_INSN_MULU_D },
+ { CRISV32F_INSN_MCP, && case_sem_INSN_MCP },
+ { CRISV32F_INSN_DSTEP, && case_sem_INSN_DSTEP },
+ { CRISV32F_INSN_ABS, && case_sem_INSN_ABS },
+ { CRISV32F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
+ { CRISV32F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
+ { CRISV32F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
+ { CRISV32F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
+ { CRISV32F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
+ { CRISV32F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
+ { CRISV32F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
+ { CRISV32F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
+ { CRISV32F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
+ { CRISV32F_INSN_ANDQ, && case_sem_INSN_ANDQ },
+ { CRISV32F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
+ { CRISV32F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
+ { CRISV32F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
+ { CRISV32F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
+ { CRISV32F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
+ { CRISV32F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
+ { CRISV32F_INSN_ORCBR, && case_sem_INSN_ORCBR },
+ { CRISV32F_INSN_ORCWR, && case_sem_INSN_ORCWR },
+ { CRISV32F_INSN_ORCDR, && case_sem_INSN_ORCDR },
+ { CRISV32F_INSN_ORQ, && case_sem_INSN_ORQ },
+ { CRISV32F_INSN_XOR, && case_sem_INSN_XOR },
+ { CRISV32F_INSN_SWAP, && case_sem_INSN_SWAP },
+ { CRISV32F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
+ { CRISV32F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
+ { CRISV32F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
+ { CRISV32F_INSN_ASRQ, && case_sem_INSN_ASRQ },
+ { CRISV32F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
+ { CRISV32F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
+ { CRISV32F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
+ { CRISV32F_INSN_LSRQ, && case_sem_INSN_LSRQ },
+ { CRISV32F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
+ { CRISV32F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
+ { CRISV32F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
+ { CRISV32F_INSN_LSLQ, && case_sem_INSN_LSLQ },
+ { CRISV32F_INSN_BTST, && case_sem_INSN_BTST },
+ { CRISV32F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
+ { CRISV32F_INSN_SETF, && case_sem_INSN_SETF },
+ { CRISV32F_INSN_CLEARF, && case_sem_INSN_CLEARF },
+ { CRISV32F_INSN_RFE, && case_sem_INSN_RFE },
+ { CRISV32F_INSN_SFE, && case_sem_INSN_SFE },
+ { CRISV32F_INSN_RFG, && case_sem_INSN_RFG },
+ { CRISV32F_INSN_RFN, && case_sem_INSN_RFN },
+ { CRISV32F_INSN_HALT, && case_sem_INSN_HALT },
+ { CRISV32F_INSN_BCC_B, && case_sem_INSN_BCC_B },
+ { CRISV32F_INSN_BA_B, && case_sem_INSN_BA_B },
+ { CRISV32F_INSN_BCC_W, && case_sem_INSN_BCC_W },
+ { CRISV32F_INSN_BA_W, && case_sem_INSN_BA_W },
+ { CRISV32F_INSN_JAS_R, && case_sem_INSN_JAS_R },
+ { CRISV32F_INSN_JAS_C, && case_sem_INSN_JAS_C },
+ { CRISV32F_INSN_JUMP_P, && case_sem_INSN_JUMP_P },
+ { CRISV32F_INSN_BAS_C, && case_sem_INSN_BAS_C },
+ { CRISV32F_INSN_JASC_R, && case_sem_INSN_JASC_R },
+ { CRISV32F_INSN_JASC_C, && case_sem_INSN_JASC_C },
+ { CRISV32F_INSN_BASC_C, && case_sem_INSN_BASC_C },
+ { CRISV32F_INSN_BREAK, && case_sem_INSN_BREAK },
+ { CRISV32F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
+ { CRISV32F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
+ { CRISV32F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
+ { CRISV32F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
+ { CRISV32F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
+ { CRISV32F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
+ { CRISV32F_INSN_SCC, && case_sem_INSN_SCC },
+ { CRISV32F_INSN_LZ, && case_sem_INSN_LZ },
+ { CRISV32F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
+ { CRISV32F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
+ { CRISV32F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
+ { CRISV32F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
+ { CRISV32F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
+ { CRISV32F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
+ { CRISV32F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
+ { CRISV32F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
+ { CRISV32F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
+ { CRISV32F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
+ { CRISV32F_INSN_FIDXI, && case_sem_INSN_FIDXI },
+ { CRISV32F_INSN_FTAGI, && case_sem_INSN_FTAGI },
+ { CRISV32F_INSN_FIDXD, && case_sem_INSN_FIDXD },
+ { CRISV32F_INSN_FTAGD, && case_sem_INSN_FTAGD },
+ { 0, 0 }
+ };
+ int i;
+
+ for (i = 0; labels[i].label != 0; ++i)
+ {
+#if FAST_P
+ CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+ CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+ }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+ off frills like tracing and profiling. */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+ that can cause it to be optimized out. Another way would be to emit
+ special handlers into the instruction "stream". */
+
+#if FAST_P
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop. */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+ {
+
+ CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV32F
+ crisv32f_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV32F
+ crisv32f_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV32F
+#ifdef DEFINE_SWITCH
+ vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV32F
+ vpc = crisv32f_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV32F
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = crisv32f_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = crisv32f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = crisv32f_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_moveq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_newval;
+ tmp_newval = FLD (f_s6);
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
+SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_newval = EXTQISI (tmp_tmpops);
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_newval = EXTHISI (tmp_tmpops);
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_newval = ZEXTQISI (tmp_tmpops);
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_newval = ZEXTHISI (tmp_tmpops);
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_newval;
+ tmp_newval = FLD (f_indir_pc__byte);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_newval;
+ tmp_newval = FLD (f_indir_pc__word);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_newval;
+ tmp_newval = FLD (f_indir_pc__dword);
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_u6);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_u6);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_andq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_s6);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_SPRV32) : /* move ${Rs},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ SI tmp_rno;
+ tmp_tmp = GET_H_GR (FLD (f_operand1));
+ tmp_rno = FLD (f_operand2);
+if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
+cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
+}
+ else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_SR (FLD (f_operand2), opval);
+ written |= (1 << 2);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_SPR_RV32) : /* move ${Ps},${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_grno;
+ SI tmp_prno;
+ SI tmp_newval;
+ tmp_prno = FLD (f_operand2);
+ tmp_newval = GET_H_SR (FLD (f_operand2));
+if (EQSI (tmp_prno, 2)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 3)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 5)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 6)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 7)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 9)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 10)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 11)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 12)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 13)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 14)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 15)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 0)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 1)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 4)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 8)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else {
+cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_SPRV32) : /* move [${Rs}${inc}],${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_rno;
+ SI tmp_newval;
+ tmp_rno = FLD (f_operand2);
+if (EQSI (tmp_rno, 2)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 3)) {
+ tmp_newval = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+}
+ else if (EQSI (tmp_rno, 5)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 6)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 7)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 9)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 10)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 11)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 12)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 13)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 14)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 15)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else {
+cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
+}
+ {
+ SI opval = tmp_newval;
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P2) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P3) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P5) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P6) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P7) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P9) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P10) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P11) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P12) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P13) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P14) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P15) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_SPR_MV32) : /* move ${Ps},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_rno;
+ tmp_rno = FLD (f_operand2);
+if (EQSI (tmp_rno, 2)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 3)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 5)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 6)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 7)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 9)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 10)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 11)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 12)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 13)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 14)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 15)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 0)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 1)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 4)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 8)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+cgen_rtx_error (current_cpu, "write from unimplemented special register");
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_SS_R) : /* move ${Ss},${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GET_H_SUPR (FLD (f_operand2));
+ SET_H_GR (FLD (f_operand1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_SS) : /* move ${Rs},${Sd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GET_H_GR (FLD (f_operand1));
+ SET_H_SUPR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "supr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEM_R_M_V32) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+{
+ SI tmp_dummy;
+ tmp_dummy = GET_H_GR (FLD (f_operand2));
+}
+ tmp_addr = GET_H_GR (FLD (f_operand1));
+{
+if (GESI (FLD (f_operand2), 0)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 0));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 1)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 1));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 2)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 2));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 3)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 3));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 4)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 4));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 5)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 5));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 6)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 6));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 7)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 7));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 8)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 8));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 9)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 9));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 10)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 10));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 11)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 11));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 12)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 12));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 13)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 13));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 14)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 14));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 15)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 15));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+}
+if (NEBI (tmp_postinc, 0)) {
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 20);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEM_M_R_V32) : /* movem [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = GET_H_GR (FLD (f_operand1));
+{
+ SI tmp_dummy;
+ tmp_dummy = GET_H_GR (FLD (f_operand2));
+}
+{
+if (GESI (FLD (f_operand2), 0)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 0), opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 1)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 1), opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 2)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 2), opval);
+ written |= (1 << 14);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 3)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 3), opval);
+ written |= (1 << 15);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 4)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 4), opval);
+ written |= (1 << 16);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 5)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 5), opval);
+ written |= (1 << 17);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 6)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 6), opval);
+ written |= (1 << 18);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 7)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 7), opval);
+ written |= (1 << 19);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 8)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 8), opval);
+ written |= (1 << 20);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 9)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 9), opval);
+ written |= (1 << 21);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 10)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 10), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 11)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 11), opval);
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 12)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 12), opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 13)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 13), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 14)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 14), opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 15)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 15), opval);
+ written |= (1 << 13);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+}
+if (NEBI (tmp_postinc, 0)) {
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 5);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__byte);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__word);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__byte);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__word);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDC_R) : /* addc $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+CPU (h_xbit) = 1;
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDC_M) : /* addc [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+CPU (h_xbit) = 1;
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDC_C) : /* addc ${const32},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+CPU (h_xbit) = 1;
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LAPC_D) : /* lapc.d ${const32-pcrel},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lapc_d.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (i_const32_pcrel);
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LAPCQ) : /* lapcq ${qo},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lapcq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = FLD (i_qo);
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
+ SET_H_GR (FLD (f_operand1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
+ SET_H_GR (FLD (f_operand1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
+ SET_H_GR (FLD (f_operand1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = 0;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = 0;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = 0;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = 0;
+ tmp_tmpopd = tmp_tmpd;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = 0;
+ tmp_tmpopd = tmp_tmpd;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = 0;
+ tmp_tmpopd = tmp_tmpd;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = GET_H_GR (FLD (f_operand2));
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = tmp_tmpd;
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = tmp_tmpd;
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = GET_H_GR (FLD (f_operand2));
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ HI opval = tmp_tmpd;
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ HI opval = tmp_tmpd;
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = GET_H_GR (FLD (f_operand2));
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = tmp_tmpd;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = tmp_tmpd;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCP) : /* mcp $Ps,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+CPU (h_xbit) = 1;
+CPU (h_zbit) = 1;
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_SR (FLD (f_operand2));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand1));
+ tmp_carry = CPU (h_rbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_rbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "rbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ SI tmp_tmps;
+ SI tmp_tmpd;
+ tmp_tmps = GET_H_GR (FLD (f_operand1));
+ tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
+ tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_andq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_andq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmps;
+ SI tmp_tmpd;
+ tmp_tmps = GET_H_GR (FLD (f_operand1));
+ tmp_tmpd = ({ SI tmp_tmpcode;
+ SI tmp_tmpval;
+ SI tmp_tmpres;
+ tmp_tmpcode = FLD (f_operand2);
+; tmp_tmpval = tmp_tmps;
+; if (EQSI (tmp_tmpcode, 0)) {
+ tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
+}
+ else if (EQSI (tmp_tmpcode, 1)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = tmp_tmpval;
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 2)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 3)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 4)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+}
+ else if (EQSI (tmp_tmpcode, 5)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 6)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 7)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 8)) {
+ tmp_tmpres = INVSI (tmp_tmpval);
+}
+ else if (EQSI (tmp_tmpcode, 9)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = INVSI (tmp_tmpval);
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 10)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 11)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 12)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+}
+ else if (EQSI (tmp_tmpcode, 13)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 14)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 15)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+; tmp_tmpres; });
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ SI tmp_cnt1;
+ SI tmp_cnt2;
+ tmp_cnt1 = GET_H_GR (FLD (f_operand1));
+ tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
+ tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ SI tmp_cnt1;
+ SI tmp_cnt2;
+ tmp_cnt1 = GET_H_GR (FLD (f_operand1));
+ tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
+ tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt1;
+ SI tmp_cnt2;
+ tmp_cnt1 = GET_H_GR (FLD (f_operand1));
+ tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
+ tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST) : /* $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_setf.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = FLD (f_dstsrc);
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 1);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_vbit) = opval;
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
+ {
+ BI opval = 1;
+ SET_H_IBIT (opval);
+ written |= (1 << 2);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
+ {
+ BI opval = 1;
+ SET_H_UBIT (opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_pbit) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_setf.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = FLD (f_dstsrc);
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 1);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
+ {
+ BI opval = 0;
+ SET_H_IBIT (opval);
+ written |= (1 << 2);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
+ {
+ BI opval = 0;
+ SET_H_UBIT (opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_pbit) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RFE) : /* rfe */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rfe.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ USI tmp_oldccs;
+ USI tmp_samebits;
+ USI tmp_shiftbits;
+ USI tmp_keepmask;
+ BI tmp_p1;
+ tmp_oldccs = GET_H_SR (((UINT) 13));
+ tmp_keepmask = 0xc0000000;
+ tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
+ tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
+ tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
+ {
+ SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
+ SET_H_SR (((UINT) 13), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SFE) : /* sfe */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rfe.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_oldccs;
+ SI tmp_savemask;
+ tmp_savemask = 0xc0000000;
+ tmp_oldccs = GET_H_SR (((UINT) 13));
+ {
+ SI opval = ORSI (ANDSI (tmp_savemask, tmp_oldccs), ANDSI (INVSI (tmp_savemask), SLLSI (tmp_oldccs, 10)));
+ SET_H_SR (((UINT) 13), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RFG) : /* rfg */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+crisv32f_rfg_handler (current_cpu, pc);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RFN) : /* rfn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rfe.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ USI tmp_oldccs;
+ USI tmp_samebits;
+ USI tmp_shiftbits;
+ USI tmp_keepmask;
+ BI tmp_p1;
+ tmp_oldccs = GET_H_SR (((UINT) 13));
+ tmp_keepmask = 0xc0000000;
+ tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
+ tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
+ tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
+ {
+ SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
+ SET_H_SR (((UINT) 13), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+ {
+ BI opval = 1;
+ SET_H_MBIT (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_HALT) : /* halt */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = crisv32f_halt_handler (current_cpu, pc);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_truthval;
+ tmp_truthval = ({ SI tmp_tmpcond;
+ BI tmp_condres;
+ tmp_tmpcond = FLD (f_operand2);
+; if (EQSI (tmp_tmpcond, 0)) {
+ tmp_condres = NOTBI (CPU (h_cbit));
+}
+ else if (EQSI (tmp_tmpcond, 1)) {
+ tmp_condres = CPU (h_cbit);
+}
+ else if (EQSI (tmp_tmpcond, 2)) {
+ tmp_condres = NOTBI (CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 3)) {
+ tmp_condres = CPU (h_zbit);
+}
+ else if (EQSI (tmp_tmpcond, 4)) {
+ tmp_condres = NOTBI (CPU (h_vbit));
+}
+ else if (EQSI (tmp_tmpcond, 5)) {
+ tmp_condres = CPU (h_vbit);
+}
+ else if (EQSI (tmp_tmpcond, 6)) {
+ tmp_condres = NOTBI (CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 7)) {
+ tmp_condres = CPU (h_nbit);
+}
+ else if (EQSI (tmp_tmpcond, 8)) {
+ tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 9)) {
+ tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 10)) {
+ tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
+}
+ else if (EQSI (tmp_tmpcond, 11)) {
+ tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 12)) {
+ tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 13)) {
+ tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 14)) {
+ tmp_condres = 1;
+}
+ else if (EQSI (tmp_tmpcond, 15)) {
+ tmp_condres = CPU (h_pbit);
+}
+; tmp_condres; });
+crisv32f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+if (tmp_truthval) {
+{
+ {
+ USI opval = FLD (i_o_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_o_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ BI tmp_truthval;
+ tmp_truthval = ({ SI tmp_tmpcond;
+ BI tmp_condres;
+ tmp_tmpcond = FLD (f_operand2);
+; if (EQSI (tmp_tmpcond, 0)) {
+ tmp_condres = NOTBI (CPU (h_cbit));
+}
+ else if (EQSI (tmp_tmpcond, 1)) {
+ tmp_condres = CPU (h_cbit);
+}
+ else if (EQSI (tmp_tmpcond, 2)) {
+ tmp_condres = NOTBI (CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 3)) {
+ tmp_condres = CPU (h_zbit);
+}
+ else if (EQSI (tmp_tmpcond, 4)) {
+ tmp_condres = NOTBI (CPU (h_vbit));
+}
+ else if (EQSI (tmp_tmpcond, 5)) {
+ tmp_condres = CPU (h_vbit);
+}
+ else if (EQSI (tmp_tmpcond, 6)) {
+ tmp_condres = NOTBI (CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 7)) {
+ tmp_condres = CPU (h_nbit);
+}
+ else if (EQSI (tmp_tmpcond, 8)) {
+ tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 9)) {
+ tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 10)) {
+ tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
+}
+ else if (EQSI (tmp_tmpcond, 11)) {
+ tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 12)) {
+ tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 13)) {
+ tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 14)) {
+ tmp_condres = 1;
+}
+ else if (EQSI (tmp_tmpcond, 15)) {
+ tmp_condres = CPU (h_pbit);
+}
+; tmp_condres; });
+crisv32f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+if (tmp_truthval) {
+{
+ {
+ USI opval = FLD (i_o_word_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 8);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_o_word_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JAS_R) : /* jas ${Rs},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+if (ANDIF (EQSI (FLD (f_operand1), 1), EQSI (FLD (f_operand2), 11))) {
+cris_flush_simulator_decode_cache (current_cpu, pc);
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = GET_H_GR (FLD (f_operand1));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JAS_C) : /* jas ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = FLD (f_indir_pc__dword);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JUMP_P) : /* jump ${Ps} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_SR (FLD (f_operand2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BAS_C) : /* bas ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bas_c.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_const32_pcrel);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JASC_R) : /* jasc ${Rs},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = GET_H_GR (FLD (f_operand1));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JASC_C) : /* jasc ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 12);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = FLD (f_indir_pc__dword);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BASC_C) : /* basc ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bas_c.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 12);
+ SET_H_SR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_const32_pcrel);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BREAK) : /* break $n */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_break.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+ {
+ USI opval = crisv32f_break_handler (current_cpu, FLD (f_u4), pc);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_truthval;
+ tmp_truthval = ({ SI tmp_tmpcond;
+ BI tmp_condres;
+ tmp_tmpcond = FLD (f_operand2);
+; if (EQSI (tmp_tmpcond, 0)) {
+ tmp_condres = NOTBI (CPU (h_cbit));
+}
+ else if (EQSI (tmp_tmpcond, 1)) {
+ tmp_condres = CPU (h_cbit);
+}
+ else if (EQSI (tmp_tmpcond, 2)) {
+ tmp_condres = NOTBI (CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 3)) {
+ tmp_condres = CPU (h_zbit);
+}
+ else if (EQSI (tmp_tmpcond, 4)) {
+ tmp_condres = NOTBI (CPU (h_vbit));
+}
+ else if (EQSI (tmp_tmpcond, 5)) {
+ tmp_condres = CPU (h_vbit);
+}
+ else if (EQSI (tmp_tmpcond, 6)) {
+ tmp_condres = NOTBI (CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 7)) {
+ tmp_condres = CPU (h_nbit);
+}
+ else if (EQSI (tmp_tmpcond, 8)) {
+ tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 9)) {
+ tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 10)) {
+ tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
+}
+ else if (EQSI (tmp_tmpcond, 11)) {
+ tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 12)) {
+ tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 13)) {
+ tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 14)) {
+ tmp_condres = 1;
+}
+ else if (EQSI (tmp_tmpcond, 15)) {
+ tmp_condres = CPU (h_pbit);
+}
+; tmp_condres; });
+ {
+ SI opval = ZEXTBISI (tmp_truthval);
+ SET_H_GR (FLD (f_operand1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (FLD (f_operand1));
+ tmp_tmpd = 0;
+{
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+}
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
+ SET_H_PREFIXREG_V32 (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmps;
+ tmp_tmps = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
+ SET_H_PREFIXREG_V32 (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmps;
+ tmp_tmps = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
+ SET_H_PREFIXREG_V32 (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmps;
+ tmp_tmps = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
+ SET_H_PREFIXREG_V32 (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
+ SET_H_PREFIXREG_V32 (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
+ SET_H_PREFIXREG_V32 (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
+ SET_H_PREFIXREG_V32 (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
+ SET_H_PREFIXREG_V32 (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
+ SET_H_PREFIXREG_V32 (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
+ SET_H_PREFIXREG_V32 (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FIDXI) : /* fidxi [$Rs] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = crisv32f_fidxi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTAGI) : /* fidxi [$Rs] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = crisv32f_ftagi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FIDXD) : /* fidxd [$Rs] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = crisv32f_fidxd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTAGD) : /* ftagd [$Rs] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = crisv32f_ftagd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+
+ }
+ ENDSWITCH (sem) /* End of semantic switch. */
+
+ /* At this point `vpc' contains the next insn to execute. */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-08-19 0:26 UTC | newest]
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2023-08-14 13:39 sim regen Alan Modra
2023-08-18 16:40 ` Tom Tromey
2023-08-18 23:46 ` Alan Modra
2023-08-19 0:26 ` Tom Tromey
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2023-08-14 11:59 Alan Modra
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