[PATCH] Two patched to fix the spelling of "aligned" in various places

[PATCH] Two patched to fix the spelling of "aligned" in various places

[Reuben Thomas]

[-- Attachment #1: Type: text/plain, Size: 58 bytes --]

One patch for gas, one for sim.

-- 
https://rrt.sc3d.org

[-- Attachment #2: 0002-sim-fix-alligned-typos.patch --]
[-- Type: text/x-patch, Size: 2336 bytes --]

From 97bdb44ff4d85bfa2642573f953215ec7abdf8be Mon Sep 17 00:00:00 2001
From: Reuben Thomas <rrt@sc3d.org>
Date: Thu, 24 Mar 2022 12:05:21 +0000
Subject: [PATCH 2/2] =?UTF-8?q?sim:=20fix=20=E2=80=9Calligned=E2=80=9D=20t?=
 =?UTF-8?q?ypos?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

	* sim/common/sim-core.h, sim/ppc/hw_init.c, sim/ppc/std-config.h:
          Change “alligned” to “aligned”.
---
 sim/common/sim-core.h | 2 +-
 sim/ppc/hw_init.c     | 2 +-
 sim/ppc/std-config.h  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/sim/common/sim-core.h b/sim/common/sim-core.h
index 5f152ee0552..1f660e3d0c5 100644
--- a/sim/common/sim-core.h
+++ b/sim/common/sim-core.h
@@ -248,7 +248,7 @@ extern void *sim_core_trans_addr
    order (including xor endian).  Should the transfer fail, the
    operation shall abort (no return).
 
-   ALIGNED assumes yhat the specified ADDRESS is correctly alligned
+   ALIGNED assumes yhat the specified ADDRESS is correctly aligned
    for an N byte transfer (no alignment checks are made).  Passing an
    incorrectly aligned ADDRESS is erroneous.
 
diff --git a/sim/ppc/hw_init.c b/sim/ppc/hw_init.c
index 3d58833bb3d..66f205851d5 100644
--- a/sim/ppc/hw_init.c
+++ b/sim/ppc/hw_init.c
@@ -576,7 +576,7 @@ create_ppc_elf_stack_frame(device *me,
   const unsigned sizeof_argv = sizeof_arguments(argv);
   const unsigned_word start_argv = start_envp - sizeof_argv;
 
-  /* link register save address - alligned to a 16byte boundary */
+  /* link register save address - aligned to a 16byte boundary */
   const unsigned_word top_of_stack = ((start_argv
 				       - 2 * sizeof(unsigned_word))
 				      & ~0xf);
diff --git a/sim/ppc/std-config.h b/sim/ppc/std-config.h
index 0619d1dff19..e02d5946a73 100644
--- a/sim/ppc/std-config.h
+++ b/sim/ppc/std-config.h
@@ -183,7 +183,7 @@ extern int current_environment;
    This model.  Instead allows both little and big endian modes to
    either take exceptions or handle miss aligned transfers.
 
-   If 0 is specified then for big-endian mode miss alligned accesses
+   If 0 is specified then for big-endian mode miss aligned accesses
    are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
    processor will fault on them (STRICT_ALIGNMENT). */
 
-- 
2.25.1


[-- Attachment #3: 0001-gas-fix-typo-alligned.patch --]
[-- Type: text/x-patch, Size: 1906 bytes --]

From 8253f2e2438541ad648e9149a9ad0d5699e51f51 Mon Sep 17 00:00:00 2001
From: Reuben Thomas <rrt@sc3d.org>
Date: Thu, 24 Mar 2022 12:01:16 +0000
Subject: [PATCH 1/2] =?UTF-8?q?gas:=20fix=20typo=20=E2=80=9Calligned?=
 =?UTF-8?q?=E2=80=9D?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

	* gas/po/{fi,id,zh_CN}.po: change “alligned” to “aligned”
---
 gas/po/fi.po    | 2 +-
 gas/po/id.po    | 2 +-
 gas/po/zh_CN.po | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gas/po/fi.po b/gas/po/fi.po
index abe2d807152..80d24316ae1 100644
--- a/gas/po/fi.po
+++ b/gas/po/fi.po
@@ -2560,7 +2560,7 @@ msgid "can only load two consecutive registers"
 msgstr "voi ladata vain kaksi peräkkäistä rekisteriä"
 
 #: config/tc-arm.c:7930
-msgid "ldr to register 15 must be 4-byte alligned"
+msgid "ldr to register 15 must be 4-byte aligned"
 msgstr "ldr-käskyn rekisteriin 15 on oltava 4-tavutasattu"
 
 #: config/tc-arm.c:7953 config/tc-arm.c:7985
diff --git a/gas/po/id.po b/gas/po/id.po
index 265ef40836b..ca9ba9c6017 100644
--- a/gas/po/id.po
+++ b/gas/po/id.po
@@ -2546,7 +2546,7 @@ msgid "can only load two consecutive registers"
 msgstr "hanya dapat load dua register sekaligus"
 
 #: config/tc-arm.c:7930
-msgid "ldr to register 15 must be 4-byte alligned"
+msgid "ldr to register 15 must be 4-byte aligned"
 msgstr "'ldr untuk register 15 harus 4-byte aligned"
 
 #: config/tc-arm.c:7953 config/tc-arm.c:7985
diff --git a/gas/po/zh_CN.po b/gas/po/zh_CN.po
index e4fd32d006c..c744b240b4a 100644
--- a/gas/po/zh_CN.po
+++ b/gas/po/zh_CN.po
@@ -3605,7 +3605,7 @@ msgstr "动态分配 cc 寄存器"
 
 #: config/tc-arm.c:8096
 #, fuzzy
-msgid "ldr to register 15 must be 4-byte alligned"
+msgid "ldr to register 15 must be 4-byte aligned"
 msgstr "登记册必须 r0 和 r7 之间"
 
 #: config/tc-arm.c:8119 config/tc-arm.c:8151
-- 
2.25.1

Re: [PATCH] Two patched to fix the spelling of "aligned" in various places

[Reuben Thomas]

[-- Attachment #1: Type: text/plain, Size: 203 bytes --]

On Thu, 24 Mar 2022 at 12:07, Reuben Thomas <rrt@sc3d.org> wrote:

> One patch for gas, one for sim.
>

I have updated the patch for sim to fix a couple of other comment typos.

-- 
https://rrt.sc3d.org

[-- Attachment #2: 0001-gas-fix-typo-alligned.patch --]
[-- Type: text/x-patch, Size: 1906 bytes --]

From 8253f2e2438541ad648e9149a9ad0d5699e51f51 Mon Sep 17 00:00:00 2001
From: Reuben Thomas <rrt@sc3d.org>
Date: Thu, 24 Mar 2022 12:01:16 +0000
Subject: [PATCH 1/2] =?UTF-8?q?gas:=20fix=20typo=20=E2=80=9Calligned?=
 =?UTF-8?q?=E2=80=9D?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

	* gas/po/{fi,id,zh_CN}.po: change “alligned” to “aligned”
---
 gas/po/fi.po    | 2 +-
 gas/po/id.po    | 2 +-
 gas/po/zh_CN.po | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gas/po/fi.po b/gas/po/fi.po
index abe2d807152..80d24316ae1 100644
--- a/gas/po/fi.po
+++ b/gas/po/fi.po
@@ -2560,7 +2560,7 @@ msgid "can only load two consecutive registers"
 msgstr "voi ladata vain kaksi peräkkäistä rekisteriä"
 
 #: config/tc-arm.c:7930
-msgid "ldr to register 15 must be 4-byte alligned"
+msgid "ldr to register 15 must be 4-byte aligned"
 msgstr "ldr-käskyn rekisteriin 15 on oltava 4-tavutasattu"
 
 #: config/tc-arm.c:7953 config/tc-arm.c:7985
diff --git a/gas/po/id.po b/gas/po/id.po
index 265ef40836b..ca9ba9c6017 100644
--- a/gas/po/id.po
+++ b/gas/po/id.po
@@ -2546,7 +2546,7 @@ msgid "can only load two consecutive registers"
 msgstr "hanya dapat load dua register sekaligus"
 
 #: config/tc-arm.c:7930
-msgid "ldr to register 15 must be 4-byte alligned"
+msgid "ldr to register 15 must be 4-byte aligned"
 msgstr "'ldr untuk register 15 harus 4-byte aligned"
 
 #: config/tc-arm.c:7953 config/tc-arm.c:7985
diff --git a/gas/po/zh_CN.po b/gas/po/zh_CN.po
index e4fd32d006c..c744b240b4a 100644
--- a/gas/po/zh_CN.po
+++ b/gas/po/zh_CN.po
@@ -3605,7 +3605,7 @@ msgstr "动态分配 cc 寄存器"
 
 #: config/tc-arm.c:8096
 #, fuzzy
-msgid "ldr to register 15 must be 4-byte alligned"
+msgid "ldr to register 15 must be 4-byte aligned"
 msgstr "登记册必须 r0 和 r7 之间"
 
 #: config/tc-arm.c:8119 config/tc-arm.c:8151
-- 
2.25.1


[-- Attachment #3: 0002-sim-fix-alligned-typos.patch --]
[-- Type: text/x-patch, Size: 2777 bytes --]

From 52c4937c4310ded9ec04d2df67f62fbdac90d9d8 Mon Sep 17 00:00:00 2001
From: Reuben Thomas <rrt@sc3d.org>
Date: Thu, 24 Mar 2022 12:05:21 +0000
Subject: [PATCH 2/2] =?UTF-8?q?sim:=20fix=20=E2=80=9Calligned=E2=80=9D=20t?=
 =?UTF-8?q?ypos?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

	* sim/common/sim-core.h: Change “alligned” to “aligned”, and fix two
	other minor typos.
	* sim/ppc/hw_init.c, sim/ppc/std-config.h: Change “alligned” to
        “aligned”.
---
 sim/common/sim-core.h | 4 ++--
 sim/ppc/hw_init.c     | 2 +-
 sim/ppc/std-config.h  | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/sim/common/sim-core.h b/sim/common/sim-core.h
index 5f152ee0552..df4e3e17a7b 100644
--- a/sim/common/sim-core.h
+++ b/sim/common/sim-core.h
@@ -248,7 +248,7 @@ extern void *sim_core_trans_addr
    order (including xor endian).  Should the transfer fail, the
    operation shall abort (no return).
 
-   ALIGNED assumes yhat the specified ADDRESS is correctly alligned
+   ALIGNED assumes that the specified ADDRESS is correctly aligned
    for an N byte transfer (no alignment checks are made).  Passing an
    incorrectly aligned ADDRESS is erroneous.
 
@@ -256,7 +256,7 @@ extern void *sim_core_trans_addr
    of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
    taken should the check fail.
 
-   MISSALIGNED transfers the data regardless.
+   MISALIGNED transfers the data regardless.
 
    Misaligned xor-endian accesses are broken into a sequence of
    transfers each <= WITH_XOR_ENDIAN bytes */
diff --git a/sim/ppc/hw_init.c b/sim/ppc/hw_init.c
index 3d58833bb3d..66f205851d5 100644
--- a/sim/ppc/hw_init.c
+++ b/sim/ppc/hw_init.c
@@ -576,7 +576,7 @@ create_ppc_elf_stack_frame(device *me,
   const unsigned sizeof_argv = sizeof_arguments(argv);
   const unsigned_word start_argv = start_envp - sizeof_argv;
 
-  /* link register save address - alligned to a 16byte boundary */
+  /* link register save address - aligned to a 16byte boundary */
   const unsigned_word top_of_stack = ((start_argv
 				       - 2 * sizeof(unsigned_word))
 				      & ~0xf);
diff --git a/sim/ppc/std-config.h b/sim/ppc/std-config.h
index 0619d1dff19..e02d5946a73 100644
--- a/sim/ppc/std-config.h
+++ b/sim/ppc/std-config.h
@@ -183,7 +183,7 @@ extern int current_environment;
    This model.  Instead allows both little and big endian modes to
    either take exceptions or handle miss aligned transfers.
 
-   If 0 is specified then for big-endian mode miss alligned accesses
+   If 0 is specified then for big-endian mode miss aligned accesses
    are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
    processor will fault on them (STRICT_ALIGNMENT). */
 
-- 
2.25.1

Re: [PATCH] Two patched to fix the spelling of "aligned" in various places

[Simon Marchi]

On 2022-03-24 08:11, Reuben Thomas via Gdb-patches wrote:
> On Thu, 24 Mar 2022 at 12:07, Reuben Thomas <rrt@sc3d.org> wrote:
> 
>> One patch for gas, one for sim.
>>
> 
> I have updated the patch for sim to fix a couple of other comment typos.
> 
> -- 
> https://rrt.sc3d.org


Hi,

Please send the gas patch to binutils@sourceware.org.

I pushed the sim one - I am not a sim maintainer, but it seems obvious to me.

Simon

Re: [PATCH] Two patched to fix the spelling of "aligned" in various places

[Reuben Thomas]

Dear Simon,

Thanks for applying the patch, and apologies for the misdirected one, which
I'll resend appropriately.

I sent a similar comment typo fix yesterday (it fixes a reference to a
function parameter name); it's similarly in sim, and is hopefully similarly
obvious: https://sourceware.org/pipermail/gdb-patches/2022-March/186902.html

It was only on reading your reply that I realise I myself mistyped
"patches" in the email subject, oops!

Thanks,

Reuben

On Thu, 24 Mar 2022 at 14:36, Simon Marchi <simark@simark.ca> wrote:

> On 2022-03-24 08:11, Reuben Thomas via Gdb-patches wrote:
> > On Thu, 24 Mar 2022 at 12:07, Reuben Thomas <rrt@sc3d.org> wrote:
> >
> >> One patch for gas, one for sim.
> >>
> >
> > I have updated the patch for sim to fix a couple of other comment typos.
> >
> > --
> > https://rrt.sc3d.org
>
>
> Hi,
>
> Please send the gas patch to binutils@sourceware.org.
>
> I pushed the sim one - I am not a sim maintainer, but it seems obvious to
> me.
>
> Simon
>


-- 
https://rrt.sc3d.org