From: Luis Machado <luis.machado@arm.com>
To: Simon Marchi <simon.marchi@polymtl.ca>, gdb-patches@sourceware.org
Cc: thiago.bauermann@linaro.org
Subject: Re: [PATCH v5 06/16] [gdbserver/aarch64] refactor: Adjust expedited registers dynamically
Date: Fri, 8 Sep 2023 17:00:49 +0100 [thread overview]
Message-ID: <af899266-88bf-5314-0ddc-ed26765d4834@arm.com> (raw)
In-Reply-To: <770bbc82-3823-42e8-aabf-cec185c8c6ca@polymtl.ca>
On 9/8/23 16:35, Simon Marchi wrote:
> On 9/7/23 11:20, Luis Machado via Gdb-patches wrote:
>> Instead of using static arrays, build the list of expedited registers
>> dynamically using a std::vector.
>>
>> This refactor shouldn't cause any user-visible changes.
>>
>> Regression-tested for aarch64-linux Ubuntu 22.04/20.04.
>> ---
>> gdbserver/linux-aarch64-tdesc.cc | 21 ++++++++++++++-------
>> 1 file changed, 14 insertions(+), 7 deletions(-)
>>
>> diff --git a/gdbserver/linux-aarch64-tdesc.cc b/gdbserver/linux-aarch64-tdesc.cc
>> index 633134955e5..3c60e1a4db0 100644
>> --- a/gdbserver/linux-aarch64-tdesc.cc
>> +++ b/gdbserver/linux-aarch64-tdesc.cc
>> @@ -30,6 +30,8 @@
>> /* All possible aarch64 target descriptors. */
>> static std::unordered_map<aarch64_features, target_desc *> tdesc_aarch64_map;
>>
>> +static std::vector<const char *> expedited_registers;
>> +
>> /* Create the aarch64 target description. */
>>
>> const target_desc *
>> @@ -44,15 +46,20 @@ aarch64_linux_read_description (const aarch64_features &features)
>> if (tdesc == NULL)
>> {
>> tdesc = aarch64_create_target_description (features);
>> + expedited_registers.clear ();
>> +
>> + /* Configure the expedited registers. By default we include x29, sp and
>> + pc. */
>> + expedited_registers.push_back ("x29");
>> + expedited_registers.push_back ("sp");
>> + expedited_registers.push_back ("pc");
>> +
>> + if (features.vq > 0)
>> + expedited_registers.push_back ("vg");
>>
>> - static const char *expedite_regs_aarch64[] = { "x29", "sp", "pc", NULL };
>> - static const char *expedite_regs_aarch64_sve[] = { "x29", "sp", "pc",
>> - "vg", NULL };
>> + expedited_registers.push_back (nullptr);
>>
>> - if (features.vq == 0)
>> - init_target_desc (tdesc, expedite_regs_aarch64);
>> - else
>> - init_target_desc (tdesc, expedite_regs_aarch64_sve);
>> + init_target_desc (tdesc, (const char **) expedited_registers.data ());
>
> It seems weird to have a single std::vector instance. What happens if
> multiple target descriptions are created? Won't the second mess up the
> data of the first one?
Yeah. Well spotted. I think I'll need to have a map-based entry for the expedited registers, because init_target_desc
just copies the pointer instead of the contents.
Let me think about that.
Thanks,
Luis
next prev parent reply other threads:[~2023-09-08 16:01 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-07 15:20 [PATCH v5 00/16] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
2023-09-07 15:20 ` [PATCH v5 01/16] [gdb/aarch64] Fix register fetch/store order for native AArch64 Linux Luis Machado
2023-09-07 15:20 ` [PATCH v5 02/16] [gdb/aarch64] refactor: Rename SVE-specific files Luis Machado
2023-09-07 15:20 ` [PATCH v5 03/16] [gdb/gdbserver] refactor: Simplify SVE interface to read/write registers Luis Machado
2023-09-07 15:20 ` [PATCH v5 04/16] [gdb/aarch64] sve: Fix return command when using V registers in a SVE-enabled target Luis Machado
2023-09-07 15:20 ` [PATCH v5 05/16] [gdb/aarch64] sme: Enable SME registers and pseudo-registers Luis Machado
2023-09-07 15:20 ` [PATCH v5 06/16] [gdbserver/aarch64] refactor: Adjust expedited registers dynamically Luis Machado
2023-09-08 15:35 ` Simon Marchi
2023-09-08 16:00 ` Luis Machado [this message]
2023-09-08 16:52 ` Simon Marchi
2023-09-07 15:20 ` [PATCH v5 07/16] [gdbserver/aarch64] sme: Add support for SME Luis Machado
2023-09-07 15:20 ` [PATCH v5 08/16] [gdb/aarch64] sve: Fix signal frame z/v register restore Luis Machado
2023-09-07 15:20 ` [PATCH v5 09/16] [gdb/aarch64] sme: Signal frame support Luis Machado
2023-09-07 15:20 ` [PATCH v5 10/16] [gdb/aarch64] sme: Fixup sigframe gdbarch when vg/svg changes Luis Machado
2023-09-08 11:08 ` Luis Machado
2023-09-08 15:48 ` Simon Marchi
2023-09-08 15:51 ` Simon Marchi
2023-09-08 15:51 ` Luis Machado
2023-09-08 15:59 ` Simon Marchi
2023-09-07 15:20 ` [PATCH v5 11/16] [gdb/aarch64] sme: Support TPIDR2 signal frame context Luis Machado
2023-09-07 15:20 ` [PATCH v5 12/16] [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping register state to core files Luis Machado
2023-09-08 11:09 ` Luis Machado
2023-09-08 15:58 ` Simon Marchi
2023-09-08 16:02 ` Simon Marchi
2023-09-08 16:05 ` Luis Machado
2023-09-07 15:20 ` [PATCH v5 13/16] [gdb/generic] corefile/bug: Fixup (gcore) core file target description reading order Luis Machado
2023-09-08 11:10 ` Luis Machado
2023-09-08 17:10 ` Simon Marchi
2023-09-12 8:49 ` Luis Machado
2023-09-13 13:50 ` Simon Marchi
2023-09-13 13:57 ` Luis Machado
2023-09-07 15:20 ` [PATCH v5 14/16] [gdb/aarch64] sme: Core file support for Linux Luis Machado
2023-09-07 15:20 ` [PATCH v5 15/16] [gdb/testsuite] sme: Add SVE/SME testcases Luis Machado
2023-09-07 15:20 ` [PATCH v5 16/16] [gdb/docs] sme: Document SME registers and features Luis Machado
2023-09-13 3:03 ` [PATCH v5 00/16] SME support for AArch64 gdb/gdbserver on Linux Thiago Jung Bauermann
2023-09-13 10:20 ` Luis Machado
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