From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Andrew Burgess <aburgess@redhat.com>,
Mike Frysinger <vapier@gentoo.org>,
Nick Clifton <nickc@redhat.com>
Cc: gdb-patches@sourceware.org
Subject: [PATCH 20/40] sim/m32r: Prepare required functions
Date: Thu, 20 Oct 2022 09:32:25 +0000 [thread overview]
Message-ID: <c08bf674f03e0fd8433319335bb90336e1b1c57b.1666258361.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1666258361.git.research_trasio@irq.a4lg.com>
This commit includes necessary header files and creates duplicated
declarations from other header files.
Duplicated declarations are necessary on M32R because, despite that some
m32rbf functions are used by m32rx and m32r2, we cannot include two or more
CPU header files: "cpu.h", "cpux.h" and "cpu2.h".
---
sim/m32r/m32r2.c | 5 +++++
sim/m32r/m32rx.c | 5 +++++
sim/m32r/sim-if.c | 4 ++++
sim/m32r/traps.c | 15 +++++++++++++++
4 files changed, 29 insertions(+)
diff --git a/sim/m32r/m32r2.c b/sim/m32r/m32r2.c
index 9c8daa5b8c6..13c2990a6ab 100644
--- a/sim/m32r/m32r2.c
+++ b/sim/m32r/m32r2.c
@@ -26,6 +26,11 @@
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
+#include "decode.h"
+
+/* From cpu.h. */
+extern CPUREG_FETCH_FN m32rbf_fetch_register;
+extern CPUREG_STORE_FN m32rbf_store_register;
/* The contents of BUF are in target byte order. */
diff --git a/sim/m32r/m32rx.c b/sim/m32r/m32rx.c
index 07098036d02..2fde1bb043f 100644
--- a/sim/m32r/m32rx.c
+++ b/sim/m32r/m32rx.c
@@ -26,6 +26,11 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
+#include "decode.h"
+
+/* From cpu.h. */
+extern CPUREG_FETCH_FN m32rbf_fetch_register;
+extern CPUREG_STORE_FN m32rbf_store_register;
/* The contents of BUF are in target byte order. */
diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c
index 878a0d5f576..3530b8d711c 100644
--- a/sim/m32r/sim-if.c
+++ b/sim/m32r/sim-if.c
@@ -25,6 +25,7 @@
#include "sim/callback.h"
#include "sim-main.h"
+#include "sim-hw.h"
#include "sim-options.h"
#include "libiberty.h"
#include "bfd.h"
@@ -33,6 +34,9 @@
#define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */
+/* From cpu.h. */
+void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
+
static void free_state (SIM_DESC);
static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
\f
diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c
index 12a87b4a697..f0fb218a11d 100644
--- a/sim/m32r/traps.c
+++ b/sim/m32r/traps.c
@@ -55,6 +55,21 @@
#include <linux/unistd.h>
#endif
+/* From cpu.h, cpux.h and cpu2.h. */
+SI m32rbf_h_gr_get (SIM_CPU *, UINT);
+void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
+USI m32rbf_h_cr_get (SIM_CPU *, UINT);
+void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
+UQI m32rbf_h_psw_get (SIM_CPU *);
+void m32rbf_h_psw_set (SIM_CPU *, UQI);
+void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
+UQI m32rxf_h_psw_get (SIM_CPU *);
+void m32rxf_h_psw_set (SIM_CPU *, UQI);
+void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
+UQI m32r2f_h_psw_get (SIM_CPU *);
+void m32r2f_h_psw_set (SIM_CPU *, UQI);
+void m32r2f_h_bpsw_set (SIM_CPU *, UQI);
+
#define TRAP_LINUX_SYSCALL 2
#define TRAP_FLUSH_CACHE 12
/* The semantic code invokes this for invalid (unrecognized) instructions. */
--
2.34.1
next prev parent reply other threads:[~2022-10-20 9:36 UTC|newest]
Thread overview: 93+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 9:32 [PATCH 00/40] sim+gdb: Suppress warnings if built with Clang (big batch 1) Tsukasa OI
2022-10-20 9:32 ` [PATCH 01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib Tsukasa OI
2022-11-14 14:01 ` Simon Marchi
2022-10-20 9:32 ` [PATCH 02/40] sim: Check known getrusage declaration existence Tsukasa OI
2022-10-23 13:59 ` Mike Frysinger
2022-10-24 10:47 ` Tsukasa OI
2022-10-24 16:03 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 03/40] sim/aarch64: Remove unused functions Tsukasa OI
2022-10-23 14:02 ` Mike Frysinger
2022-10-24 10:55 ` Tsukasa OI
2022-10-20 9:32 ` [PATCH 04/40] cpu/cris: Initialize some variables on CRIS CPU Tsukasa OI
2022-10-20 9:32 ` [PATCH 05/40] cpu/cris: Add u-stall virtual unit to CRIS v32 Tsukasa OI
2022-10-20 9:32 ` [PATCH 06/40] sim/cris: Move declarations of f_specific_init Tsukasa OI
2022-10-23 14:26 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 07/40] sim/cris: Regenerate with CGEN Tsukasa OI
2022-10-23 14:27 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 08/40] sim/erc32: Insert void parameter Tsukasa OI
2022-10-23 14:04 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 09/40] sim/erc32: Use int32_t as event callback argument Tsukasa OI
2022-10-23 14:32 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 10/40] sim/erc32: Use int32_t as IRQ " Tsukasa OI
2022-10-23 14:33 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 11/40] cpu/frv: Initialize some variables Tsukasa OI
2022-10-20 9:32 ` [PATCH 12/40] sim/frv: Initialize nesr variable Tsukasa OI
2022-10-23 14:39 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 13/40] sim/frv: Initialize some variables Tsukasa OI
2022-10-23 14:34 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 14/40] sim/frv: Add explicit casts Tsukasa OI
2022-10-23 14:40 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 15/40] sim/h8300: Add "+ 0x0" to avoid self-assignments Tsukasa OI
2022-10-23 14:05 ` Mike Frysinger
2022-10-24 10:55 ` Tsukasa OI
2022-10-20 9:32 ` [PATCH 16/40] sim/lm32: fix some missing function declaration warnings Tsukasa OI
2022-10-23 14:41 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 17/40] sim/lm32: Add explicit casts Tsukasa OI
2022-10-23 14:42 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 18/40] sim/m32c: Stop using middle dot Tsukasa OI
2022-10-23 14:48 ` Mike Frysinger
2022-10-27 2:08 ` Tsukasa OI
2022-10-20 9:32 ` [PATCH 19/40] sim/m32r: Initialize "list" variable Tsukasa OI
2022-10-23 14:50 ` Mike Frysinger
2022-10-20 9:32 ` Tsukasa OI [this message]
2022-10-23 14:53 ` [PATCH 20/40] sim/m32r: Prepare required functions Mike Frysinger
2022-10-20 9:32 ` [PATCH 21/40] sim/m32r: Declare all " Tsukasa OI
2022-10-23 14:54 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 22/40] sim/m32r: Fixes to Linux emulator Tsukasa OI
2022-10-23 14:56 ` Mike Frysinger
2022-10-27 2:40 ` Tsukasa OI
2022-10-27 16:05 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 23/40] sim/m32r: Add explicit casts Tsukasa OI
2022-10-23 14:57 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 24/40] sim/mips: Fix enum type-related issues on cp1.c Tsukasa OI
2022-10-23 15:00 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 25/40] sim/mn10300: Add an explicit cast Tsukasa OI
2022-10-23 15:03 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 26/40] sim/ppc: Remove getrusage declarations if possible Tsukasa OI
2022-10-23 15:04 ` Mike Frysinger
2022-10-27 2:00 ` Tsukasa OI
2022-10-20 9:32 ` [PATCH 27/40] sim/ppc: Add extra parenthesis to avoid ambiguity Tsukasa OI
2022-10-23 15:05 ` Mike Frysinger
2022-10-24 10:59 ` Tsukasa OI
2022-10-20 9:32 ` [PATCH 28/40] sim/ppc: Initialize stat type buffer Tsukasa OI
2022-10-23 15:06 ` Mike Frysinger
2022-10-24 11:00 ` Tsukasa OI
2022-10-20 9:32 ` [PATCH 29/40] sim/ppc: Fix indentation on generated code Tsukasa OI
2022-10-23 15:07 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 30/40] sim/ppc: Use TRACE with initialized entry_point Tsukasa OI
2022-10-23 15:08 ` Mike Frysinger
2022-10-24 11:02 ` Tsukasa OI
2022-10-20 9:32 ` [PATCH 31/40] sim/ppc: Initialize help variables Tsukasa OI
2022-10-23 15:08 ` Mike Frysinger
2022-10-24 16:33 ` Andrew Burgess
2022-10-20 9:32 ` [PATCH 32/40] sim/ppc: Add an explicit cast Tsukasa OI
2022-10-23 15:10 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 33/40] sim/ppc: Initialize reg and control_nr Tsukasa OI
2022-10-23 15:14 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 34/40] sim/rx: Mark unused function Tsukasa OI
2022-10-23 15:14 ` Mike Frysinger
2022-10-24 16:30 ` Andrew Burgess
2022-10-29 11:58 ` Tsukasa OI
2022-10-20 9:32 ` [PATCH 35/40] sim/sh: Initialize some variables Tsukasa OI
2022-10-23 15:19 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 36/40] sim/sh: Use fabs instead of abs Tsukasa OI
2022-10-23 14:17 ` Mike Frysinger
2022-10-24 10:56 ` Tsukasa OI
2022-10-20 9:32 ` [PATCH 37/40] sim/sh: Remove redundant function declaration Tsukasa OI
2022-10-23 14:19 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 38/40] sim/bpf: Add explicit casts Tsukasa OI
2022-10-23 15:15 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 39/40] sim/iq2000: " Tsukasa OI
2022-10-23 15:16 ` Mike Frysinger
2022-10-20 9:32 ` [PATCH 40/40] sim/or1k: " Tsukasa OI
2022-10-23 15:16 ` Mike Frysinger
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