[PATCH v5 0/3] RISC-V: Add 'Zmmul' extension

[Tsukasa OI <research_trasio@irq.a4lg.com>]

Hi RISC-V folks,

'Zmmul' is a RISC-V extension consisting of only multiply instructions (a
subset of 'M'; multiply and divide instructions).

This patch is PATCH v5 of the Zmmul support patchset primarily for Binutils
but also contains some GDB changes (a simulator fix and a new testcase).

I completed the copyright assignment for my GDB contribution so minor
simulator changes are now safe enough to merge.

Changed Project(s):
PATCH 1/3: Binutils
PATCH 2/3: Binutils and GDB (not to make "temporally broken" revision)
PATCH 3/3: Binutils


Note:
To confirm that the simulator is fixed, it requires another patch.
<https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
Without the patch above, 'Zmmul' extension will still work perfectly
(even the simulator).  Still, testing whether the simulator works with this
extension (with `make check-sim') requires it.


Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_zmmul>
PATCH v1:
<https://sourceware.org/pipermail/binutils/2022-July/121685.html>
PATCH v2:
<https://sourceware.org/pipermail/binutils/2022-July/121791.html>
PATCH v3:
<https://sourceware.org/pipermail/binutils/2022-July/121810.html>
PATCH v4:
<https://sourceware.org/pipermail/binutils/2022-August/122300.html>


This is based on the ISA Manual, draft-20220707-f518c25:
<https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220707-f518c25>
<https://github.com/riscv/riscv-isa-manual/commit/f518c259c008f926eba4aba67804f62531b6e94b>

This patchset also contains generic 'M' extension testcases as PATCH 1/3 (it
also tests for existence of the symbol `zmmul' so that it can also be a
base of 'Zmmul' testcases).


[Changes: v4 -> v5]

-   Clarify that PATCH 1/3 (new 'M' extension testcases) contains
    preparation for the 'Zmmul' extension.


[BUG in PATCH v2 (fixed in v3): Simulator stopped working]

The cause was simple.  The RISC-V simulator supports I, M and A extensions
and the instruction is identified by those instruction classes:

-   INSN_CLASS_I (for 'I')
-   INSN_CLASS_M (for 'M')
-   INSN_CLASS_A (for 'A')

I forgot to add INSN_CLASS_ZMMUL (also for 'M') to that list and that caused
multiply instructions to cause failure.

PATCH v3 fixed that and I added a testcase (checks whether all RV32M
instructions run without any fault).


Thanks,
Tsukasa




Tsukasa OI (3):
  RISC-V: Add 'M' extension testcases
  RISC-V: Add 'Zmmul' extension
  RISC-V: Add 'Zmmul' failure testcases

 bfd/elfxx-riscv.c                             |  6 +++++
 gas/testsuite/gas/riscv/attribute-09.d        |  2 +-
 gas/testsuite/gas/riscv/m-ext-32.d            | 18 +++++++++++++
 gas/testsuite/gas/riscv/m-ext-64.d            | 23 ++++++++++++++++
 .../gas/riscv/m-ext-fail-noarch-64.d          |  4 +++
 .../gas/riscv/m-ext-fail-noarch-64.l          | 14 ++++++++++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d  |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l  |  6 +++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l |  5 ++++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d |  4 +++
 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l |  9 +++++++
 gas/testsuite/gas/riscv/m-ext.s               | 21 +++++++++++++++
 gas/testsuite/gas/riscv/option-arch-02.d      |  2 +-
 gas/testsuite/gas/riscv/zmmul-32.d            | 14 ++++++++++
 gas/testsuite/gas/riscv/zmmul-64.d            | 15 +++++++++++
 include/opcode/riscv.h                        |  1 +
 opcodes/riscv-opc.c                           | 26 +++++++++----------
 sim/riscv/sim-main.c                          |  1 +
 sim/testsuite/riscv/m-ext.s                   | 18 +++++++++++++
 20 files changed, 182 insertions(+), 15 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-noarch-64.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-32.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
 create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.l
 create mode 100644 gas/testsuite/gas/riscv/m-ext.s
 create mode 100644 gas/testsuite/gas/riscv/zmmul-32.d
 create mode 100644 gas/testsuite/gas/riscv/zmmul-64.d
 create mode 100644 sim/testsuite/riscv/m-ext.s


base-commit: 27d582267a1d06e94661979f8893799ac235a768
-- 
2.34.1