public inbox for gdb-patches@sourceware.org
 help / color / mirror / Atom feed
From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: gdb-patches@sourceware.org
Subject: [PING^3 PATCH 0/1] sim/riscv: PR29595, Fix broken RISC-V simulater after implementing 'Zmmul'
Date: Thu,  6 Oct 2022 10:32:59 +0000	[thread overview]
Message-ID: <cover.1665052334.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1663776070.git.research_trasio@irq.a4lg.com>

NOTE: the cover letter and subject may change each time I ping.

Hello,

As I describe later, this patchset fixes now-broken RISC-V instruction
simulator.  I hope this patchset is approved as fast as possible since it's
clearly a functional blocker for GDB 13.1.


The patch is a PING (3) of
<https://sourceware.org/pipermail/gdb-patches/2022-August/191609.html>.

Issue Tracker on Sourceware Bugzilla:
<https://sourceware.org/bugzilla/show_bug.cgi?id=29595>

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/sim_riscv_zmmul>
Previous: 'Zmmul' v5:
<https://sourceware.org/pipermail/gdb-patches/2022-August/191295.html>


Due to opcodes changes (to add the 'Zmmul' extension in the
commit 0938b032daa5 "RISC-V: Add 'Zmmul' extension in assembler."), the
instruction simulator for RISC-V is now broken.

For multiply/divide instructions in the 'M' extension, only division /
remainder instructions work and **multiply instructions cause a trap**.

This is because only one side of my 'Zmmul' patchset is applied and GDB-
part of my 'Zmmul' patchset (this) is not approved yet.

In the current master, multiply instructions of the RISC-V simulator doesn't
work.  The cause was simple.  The RISC-V simulator supports 'I', 'M' and 'A'
extensions and the instruction is identified by those instruction classes:

-   INSN_CLASS_I (for 'I')
-   INSN_CLASS_M (for 'M')
-   INSN_CLASS_A (for 'A')

After adding the 'Zmmul' extension, INSN_CLASS_M is splitted to:

-   INSN_CLASS_ZMMUL (multiply instructions)
-   INSN_CLASS_M     (division instructions)

So, the simulator must handle INSN_CLASS_ZMMUL separately.

My 'Zmmul' patchset fixed that and I added a testcase (checks whether all
RV32M instructions run without any fault) but only opcodes part is applied
so it's now broken state for the simulator.

This is the simulator part of the original 'Zmmul' patchset (from PATCH v5).


Note:
To confirm that the simulator is fixed, it requires another patch.
<https://sourceware.org/pipermail/gdb-patches/2022-August/191564.html>
Without the patch above, all multiply instructions will still work.
Still, testing whether the simulator works with this extension
(with `make check-sim') requires it.


Regards,
Tsukasa




Tsukasa OI (1):
  sim/riscv: PR29595, Fix multiply instructions

 sim/riscv/sim-main.c        |  1 +
 sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 sim/testsuite/riscv/m-ext.s


base-commit: 80e0c6dc91f52fad32c3ff3cf20da889d77013ac
-- 
2.34.1


  parent reply	other threads:[~2022-10-06 10:33 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <cover.1657793406.git.research_trasio@irq.a4lg.com>
2022-08-09  3:37 ` [PATCH v4 0/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-08-09  3:37   ` [PATCH v4 1/3] RISC-V: Add 'M' extension testcases Tsukasa OI
2022-08-09  3:37   ` [PATCH v4 2/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-08-09  3:37   ` [PATCH v4 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI
2022-08-29  1:58   ` [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-08-29  1:58     ` [PATCH v5 1/3] RISC-V: Add 'M' extension testcases Tsukasa OI
2022-08-29  1:58     ` [PATCH v5 2/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-08-29  1:58     ` [PATCH v5 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI
2022-08-30  9:55     ` [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension Nelson Chu
2022-09-01  7:47       ` Tsukasa OI
2022-08-31  1:46     ` [PATCH 0/1] sim: Fix RISC-V multiply instructions on simulator Tsukasa OI
2022-08-31  1:46       ` [PATCH 1/1] " Tsukasa OI
2022-09-14 10:55       ` [PING^1 PATCH 0/1] " Tsukasa OI
2022-09-14 10:55         ` [PING^1 PATCH 1/1] sim/riscv: Fix RISC-V multiply instructions on the simulator Tsukasa OI
2022-09-21 16:01         ` [PING^2 PATCH 0/1] sim/riscv: Fix broken RISC-V simulater after implementing 'Zmmul' Tsukasa OI
2022-09-21 16:01           ` [PING^2 PATCH 1/1] sim/riscv: Fix RISC-V multiply instructions on the simulator Tsukasa OI
2022-10-06 10:32           ` Tsukasa OI [this message]
2022-10-06 10:33             ` [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions Tsukasa OI
2022-10-06 15:58               ` Palmer Dabbelt
2022-10-06 16:14                 ` Tsukasa OI
2022-10-06 18:27                   ` Palmer Dabbelt
2022-10-11 11:43                     ` Andrew Burgess
2022-10-11 11:41               ` Andrew Burgess

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=cover.1665052334.git.research_trasio@irq.a4lg.com \
    --to=research_trasio@irq.a4lg.com \
    --cc=gdb-patches@sourceware.org \
    --cc=palmer@dabbelt.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).