[Bug sim/19447] mips sim fails some tests when using 64-bit address space

["fshahbazker at wavecomp dot com" <sourceware-bugzilla@sourceware.org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=19447

Faraz Shahbazker <fshahbazker at wavecomp dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |fshahbazker at wavecomp dot com,
                   |                            |macro@linux-mips.org

--- Comment #1 from Faraz Shahbazker <fshahbazker at wavecomp dot com> ---
The sign-extension logic modeled by BFD is an integral part of the MIPS64
architecture spec. It appears in the virtual address map, where sign extension
allows for 32-bit compatibility segments [1] with 64-bit addressing. Truncating
these addresses prematurely in PC space breaks 64-bit builds
(-DWITH_TARGET_WORD_BITSIZE=64).

In the ISA itself, direct addressing (Load-Upper-Immediate) and indirect
addressing (Load-Word) both automatically sign-extend their results. These
instructions regenerate the sign-extended addresses even if we don't start with
one. That's what causes the failures in the report above.

Moreover, some instructions like ADD*/SUB* have unpredictable behaviour when an
operand is not correctly sign extended [3]. This affects PC-relative addressing
in particular. So arithmetic on the link-address generated in the return
address register by a jump-and-link is no longer possible, neither is the use
of the PC-relative addressing instructions provided by MIPSR6. I am preparing
upstream submission for R6, which is
where I first hit the problem.

As you might have seen, if we undo the PC address truncation, the earlier
common-read/write commit becomes problematic. Simple stuff like setting a
software breakpoint is no longer possible without some address translation for
MIPS. Even though I agree with the general premise that there is no MMU based
mapping, there is still a translation happening when addressing 32-bit memory
from 64-bit mode. This might be as trivial in h/w as leaving the upper address
lines unconnected, but it must be explicitly modeled in software by masking, if
not by a call to AddressTranslation, then elsewhere.

We might be able to work-around this by creating shadow memory in the
sign-extended space, but I think that is to over-wrought a solution. IN the
immeidiate term, I'd like to remove truncation of PC address and re-instate the
truncation on pAddr prior to calling to load_memory and store_memory
(sim/mips/sim-main.h). I am open to better suggestions.


[1] "MIPS64 Architecture for Programmers Volume III: The MIPS64
    Privileged Resource Architecture", Document Number: MD00091,
    Revision 6.02, December 10, 2015, Section 4.3 "Virtual Address
    Spaces", pp. 29-31
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwjkk_jryv3vAhWDbysKHT4nDtIQFjACegQIAhAD&url=https%3A%2F%2Fs3-eu-west-1.amazonaws.com%2Fdownloads-mips%2Fdocuments%2FMD00091-2B-MIPS64PRA-AFP-06.03.pdf&usg=AOvVaw3bd2eW-vrsex-1URAFfeQT


[2] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64
    Instruction Set Reference Manual", Document Number: MD00087,
    Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical
    List of Instructions", pp. 321

[3] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64
    Instruction Set Reference Manual", Document Number: MD00087,
    Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical
    List of Instructions", pp. 56
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwje5dGMkf7vAhWEyDgGHU-jA8UQFjACegQIAxAD&url=https%3A%2F%2Fs3-eu-west-1.amazonaws.com%2Fdownloads-mips%2Fdocuments%2FMD00087-2B-MIPS64BIS-AFP-6.06.pdf&usg=AOvVaw2VR4VX1XSWo6efzaC6TxKH

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