[Bug gdb/26819] RISC-V: internal-error: int finish_step_over(execution_control_state*): Assertion

["jmatyas at codasip dot com" <sourceware-bugzilla@sourceware.org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=26819

--- Comment #2 from Jan Matyas <jmatyas at codasip dot com> ---
Hello Andrew,

thank you for taking the time to look at this.

I have re-run the scenario in question against the very latest spike and
openocd, and can confirm the assertion still gets triggered.

These are the revisions of Spike and RISC-V OpenOCD I have used. Both should be
the latest "trunk" code as of now:

riscv-openocd:
1ba1b8784 (HEAD -> riscv, origin/riscv, origin/HEAD) Fix build outside of a git
repo. (#551)

riscv-isa-sim:
641d7d0 (HEAD -> master, origin/master, origin/HEAD) Merge pull request #588
from kito-cheng/master

Riscv-gcc and riscv-gdb I have taken from this fresh build by Embecosm:
https://buildbot.embecosm.com/job/riscv32-gcc-ubuntu1804/25/

The OpenOCD deprecation warning about "-rtos riscv" shows in my setup, too, and
I believe it is of no consequence for this issue.

However, our results differ in the number of harts discovered by OpenOCD:

Your output:
 Info : Examined RISC-V core; found 1 harts
 Info :  hart 0: XLEN=64, misa=0x8000000000141129

My results:
 Info : Examined RISC-V core; found 2 harts
 Info :  hart 0: currently disabled
 Info :  hart 1: XLEN=64, misa=0x8000000000141129

Could it be that your spike is configured differently - with just a single
hart?

For reference, I am attaching "20201108-102839-spike64_2-PrivChange.log" which
shows logs from GDB, OpenOCD and Spike. Note that the exact GDB command
sequence may be slightly different from the original scenario, but showing the
same issue.

I'd be happy to provide further data on the issue, if needed.

Regards,
Jan

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