[Bug tdep/31681] [powerpc] presence of SPE disables VLE instruction decoding

["Tadej.Pecar@elaphe-ev.com" <sourceware-bugzilla@sourceware.org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=31681

--- Comment #3 from Tadej Pečar <Tadej.Pecar@elaphe-ev.com> ---
A quick hack that disables the SPE check, provides VLE variant & drops support
for VLE / non-VLE mixing in ppc-dis.c seems to get the disassembly going, but
this obviously can't be considered a final solution.

Need to clean it up.

diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 23397d0..6a2d943 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -3506,6 +3506,8 @@ static struct ppc_variant variants[] =
    bfd_mach_ppc_7400, &tdesc_powerpc_7400},
   {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
    bfd_mach_ppc_e500, &tdesc_powerpc_e500},
+  {"vle", "Motorola PowerPC VLE", bfd_arch_powerpc,
+   bfd_mach_ppc_vle, &tdesc_powerpc_e500},

   /* 64-bit */
   {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
@@ -7565,7 +7567,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct
gdbarch_list *arches)
      which looks at each instruction and determines which unit (and
      which version of it) can execute it.  Grovel through the section
      looking for relevant e500 APUs.  */
-
+#if 0
   if (bfd_uses_spe_extensions (info.abfd))
     {
       arch = info.bfd_arch_info->arch;
@@ -7573,7 +7575,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct
gdbarch_list *arches)
       bfd_default_set_arch_mach (&abfd, arch, mach);
       info.bfd_arch_info = bfd_get_arch_info (&abfd);
     }
-
+#endif
   /* Find a default target description which describes our register
      layout, if we do not already have one.  */
   if (! tdesc_has_registers (tdesc))
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index d97137d..a5694c4 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -297,14 +297,14 @@ get_powerpc_dialect (struct disassemble_info *info)
     dialect = private_data (info)->dialect;

   /* Disassemble according to the section headers flags for VLE-mode.  */
-  if (dialect & PPC_OPCODE_VLE
-      && info->section != NULL && info->section->owner != NULL
-      && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
-      && elf_object_id (info->section->owner) == PPC32_ELF_DATA
-      && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
+//  if (dialect & PPC_OPCODE_VLE
+//      && info->section != NULL && info->section->owner != NULL
+//      && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
+//      && elf_object_id (info->section->owner) == PPC32_ELF_DATA
+//      && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
     return dialect;
-  else
-    return dialect & ~ PPC_OPCODE_VLE;
+//  else
+//    return dialect & ~ PPC_OPCODE_VLE;
 }

 /* Handle -m and -M options that set cpu type, and .machine arg.  */

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