How to get past ebreak instruction on RISC-V

How to get past ebreak instruction on RISC-V

[Jan Vrany]

Hi, 

I'm working on RISC-V compiler. To ease debugging of compiled code
I'm inserting `ebreak` instruction to interesting place (entry/exit
points or as a placeholder for unimplemented features). 

For example, the code might look like:

(gdb) disas 0x0000003FD6A36024, 0x0000003FD6A36048
Dump of assembler code from 0x3fd6a36024 to 0x3fd6a36048:
=> 0x0000003fd6a36024:  ebreak
   0x0000003fd6a36028:  sd      ra,-8(s11)
   0x0000003fd6a3602c:  addi    s11,s11,-16
   0x0000003fd6a36030:  ld      t3,80(s10)
   0x0000003fd6a36034:  addiw   a0,zero,42
   0x0000003fd6a36038:  addi    s11,s11,16
   0x0000003fd6a3603c:  ret
   0x0000003fd6a36040:  blt     s11,t3,0x3fd6a36000
   0x0000003fd6a36044:  ebreak
End of assembler dump.
(gdb) 

When compiled function is (attempted to) run, it stops on `ebreak` 
as expected: 

Thread 2 "main" received signal SIGTRAP, Trace/breakpoint trap.
[Switching to Thread 0x3ff7e681e0 (LWP 428777)]
0x0000003fd6a36024 in ?? ()

How can I get past the `ebreak` so I can `stepi` thought the following
instructions and debug? Thanks! 

Best, Jan

Re: How to get past ebreak instruction on RISC-V

[Simon Marchi]

On 2021-01-12 11:07 a.m., Jan Vrany wrote:
> Hi, 
> 
> I'm working on RISC-V compiler. To ease debugging of compiled code
> I'm inserting `ebreak` instruction to interesting place (entry/exit
> points or as a placeholder for unimplemented features). 
> 
> For example, the code might look like:
> 
> (gdb) disas 0x0000003FD6A36024, 0x0000003FD6A36048
> Dump of assembler code from 0x3fd6a36024 to 0x3fd6a36048:
> => 0x0000003fd6a36024:  ebreak
>    0x0000003fd6a36028:  sd      ra,-8(s11)
>    0x0000003fd6a3602c:  addi    s11,s11,-16
>    0x0000003fd6a36030:  ld      t3,80(s10)
>    0x0000003fd6a36034:  addiw   a0,zero,42
>    0x0000003fd6a36038:  addi    s11,s11,16
>    0x0000003fd6a3603c:  ret
>    0x0000003fd6a36040:  blt     s11,t3,0x3fd6a36000
>    0x0000003fd6a36044:  ebreak
> End of assembler dump.
> (gdb) 
> 
> When compiled function is (attempted to) run, it stops on `ebreak` 
> as expected: 
> 
> Thread 2 "main" received signal SIGTRAP, Trace/breakpoint trap.
> [Switching to Thread 0x3ff7e681e0 (LWP 428777)]
> 0x0000003fd6a36024 in ?? ()
> 
> How can I get past the `ebreak` so I can `stepi` thought the following
> instructions and debug? Thanks! 

I suppose you could do "set $pc = 0x3fd6a36028".  But really this is
something that GDB should be doing automatically, adjusting the PC
after hitting that style of breakpoint.

Simon

Re: How to get past ebreak instruction on RISC-V

[Andrew Burgess]

* Simon Marchi via Gdb <gdb@sourceware.org> [2021-01-12 11:15:37 -0500]:

> 
> 
> On 2021-01-12 11:07 a.m., Jan Vrany wrote:
> > Hi, 
> > 
> > I'm working on RISC-V compiler. To ease debugging of compiled code
> > I'm inserting `ebreak` instruction to interesting place (entry/exit
> > points or as a placeholder for unimplemented features). 
> > 
> > For example, the code might look like:
> > 
> > (gdb) disas 0x0000003FD6A36024, 0x0000003FD6A36048
> > Dump of assembler code from 0x3fd6a36024 to 0x3fd6a36048:
> > => 0x0000003fd6a36024:  ebreak
> >    0x0000003fd6a36028:  sd      ra,-8(s11)
> >    0x0000003fd6a3602c:  addi    s11,s11,-16
> >    0x0000003fd6a36030:  ld      t3,80(s10)
> >    0x0000003fd6a36034:  addiw   a0,zero,42
> >    0x0000003fd6a36038:  addi    s11,s11,16
> >    0x0000003fd6a3603c:  ret
> >    0x0000003fd6a36040:  blt     s11,t3,0x3fd6a36000
> >    0x0000003fd6a36044:  ebreak
> > End of assembler dump.
> > (gdb) 
> > 
> > When compiled function is (attempted to) run, it stops on `ebreak` 
> > as expected: 
> > 
> > Thread 2 "main" received signal SIGTRAP, Trace/breakpoint trap.
> > [Switching to Thread 0x3ff7e681e0 (LWP 428777)]
> > 0x0000003fd6a36024 in ?? ()
> > 
> > How can I get past the `ebreak` so I can `stepi` thought the following
> > instructions and debug? Thanks! 
> 
> I suppose you could do "set $pc = 0x3fd6a36028".  But really this is
> something that GDB should be doing automatically, adjusting the PC
> after hitting that style of breakpoint.

If you place a breakpoint at the location of the ebreak then GDB will
spot that there is already an ebreak there and will do the right
thing.  That is, it will treat it like a breakpoint, including being
able to step over the breakpoint correctly, but will not get confused
by the fact that there's no "real" instruction to execute at this
address.

Here's a sample session:

  (gdb) target sim
  Connected to the simulator.
  (gdb) load
  Loading section .text, size 0x20 lma 0x10054
  Start address 0x10054
  Transfer rate: 256 bits in <1 sec.
  (gdb) x/10i 0x10054
     0x10054 <_start>:	nop
     0x10058 <_start+4>:	nop
     0x1005c <_start+8>:	nop
     0x10060 <_start+12>:	ebreak
     0x10064 <_start+16>:	nop
     0x10068 <_start+20>:	nop
     0x1006c <_start+24>:	nop
     0x10070 <_start+28>:	ebreak
     0x10074:	unimp
     0x10076:	unimp
  (gdb) break *0x10060
  Breakpoint 1 at 0x10060
  (gdb) r
  Starting program: /home/andrew/projects/riscv-gdb/tmp/test.x 
  
  Breakpoint 1, 0x00010060 in _start ()
  (gdb) c
  Continuing.
  
  Program received signal SIGTRAP, Trace/breakpoint trap.
  0x00010070 in _start ()
  (gdb) x/10i 0x10054
     0x10054 <_start>:	nop
     0x10058 <_start+4>:	nop
     0x1005c <_start+8>:	nop
     0x10060 <_start+12>:	ebreak
     0x10064 <_start+16>:	nop
     0x10068 <_start+20>:	nop
     0x1006c <_start+24>:	nop
  => 0x10070 <_start+28>:	ebreak
     0x10074:	unimp
     0x10076:	unimp
  (gdb) 

Thanks,
Andrew