Re: Hardware watchpoint for read

[Xin Tong <xerox.time.tech@gmail.com>]

On Thu, May 3, 2012 at 3:19 PM, Philippe Waroquiers
<philippe.waroquiers@skynet.be> wrote:
>>> what are the performance penalties of having a watchpoint on a memory
>>> location in the state of the art x86 processor. Because it might be
>>> implemented with a parallel circuitry in the processor, my guess is
>>> that it could be cheap.
>>
>>
>> Do you mean a hardware watchpoint? It's hard to say for sure without
>> looking at the processors inner workings, but the penalty is probably very
>> small.
>>
>> When the conditions are satisfied, a TRAP will be generated and it will
>> get through to the debugger via the kernel.
>>
>> Suppose we issue a continue command... For the debugger, the inferior will
>> run uninterrupted while the hardware watchpoint is active.
>>
>> This is not the case with software watchpoints, as the debugger will be
>> constantly touching the inferior while it runs.
>
> Which makes software watchpoints extremely slow, while hardware
> watchpoints have limitations (e.g. in nr or size).
> Note that the Valgrind gdbserver (in 3.7.0) provides "unlimited simulated
> hw watchpoints" : these are slower than real hw watchpoints, but "only"
> suffer from the Valgrind slowdown.
>
> Philippe
>

The breakpoint instructions (int 3 on x86) are inserted in the
translation process ?

Xin