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* [glibc/arm/morello/main] elf: add EF_AARCH64_CHERI_PURECAP
@ 2022-08-05 19:33 Szabolcs Nagy
  0 siblings, 0 replies; 4+ messages in thread
From: Szabolcs Nagy @ 2022-08-05 19:33 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=823a9cb203c3b13127db5b3e1f94a697e695735f

commit 823a9cb203c3b13127db5b3e1f94a697e695735f
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Fri Apr 29 14:27:32 2022 +0100

    elf: add EF_AARCH64_CHERI_PURECAP

Diff:
---
 elf/elf.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/elf/elf.h b/elf/elf.h
index f61eced554..4a5653c419 100644
--- a/elf/elf.h
+++ b/elf/elf.h
@@ -2906,6 +2906,9 @@ enum
 /* MTE memory tag segment type.  */
 #define PT_AARCH64_MEMTAG_MTE	(PT_LOPROC + 2)
 
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_AARCH64_CHERI_PURECAP 0x00010000
+
 /* AArch64 specific values for the Dyn d_tag field.  */
 #define DT_AARCH64_BTI_PLT	(DT_LOPROC + 1)
 #define DT_AARCH64_PAC_PLT	(DT_LOPROC + 3)


^ permalink raw reply	[flat|nested] 4+ messages in thread
* [glibc/arm/morello/main] elf: add EF_AARCH64_CHERI_PURECAP
@ 2022-11-23 14:44 Szabolcs Nagy
  0 siblings, 0 replies; 4+ messages in thread
From: Szabolcs Nagy @ 2022-11-23 14:44 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=61de2a5e8450060e014a61e9ff6ce88d2501ed97

commit 61de2a5e8450060e014a61e9ff6ce88d2501ed97
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Fri Apr 29 14:27:32 2022 +0100

    elf: add EF_AARCH64_CHERI_PURECAP

Diff:
---
 elf/elf.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/elf/elf.h b/elf/elf.h
index 1eff0704d4..55809e941e 100644
--- a/elf/elf.h
+++ b/elf/elf.h
@@ -2906,6 +2906,9 @@ enum
 /* MTE memory tag segment type.  */
 #define PT_AARCH64_MEMTAG_MTE	(PT_LOPROC + 2)
 
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_AARCH64_CHERI_PURECAP 0x00010000
+
 /* AArch64 specific values for the Dyn d_tag field.  */
 #define DT_AARCH64_BTI_PLT	(DT_LOPROC + 1)
 #define DT_AARCH64_PAC_PLT	(DT_LOPROC + 3)

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [glibc/arm/morello/main] elf: add EF_AARCH64_CHERI_PURECAP
@ 2022-10-27 13:54 Szabolcs Nagy
  0 siblings, 0 replies; 4+ messages in thread
From: Szabolcs Nagy @ 2022-10-27 13:54 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=841d63974f6fe56e6d91c67552f5833de13730bf

commit 841d63974f6fe56e6d91c67552f5833de13730bf
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Fri Apr 29 14:27:32 2022 +0100

    elf: add EF_AARCH64_CHERI_PURECAP

Diff:
---
 elf/elf.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/elf/elf.h b/elf/elf.h
index f61eced554..4a5653c419 100644
--- a/elf/elf.h
+++ b/elf/elf.h
@@ -2906,6 +2906,9 @@ enum
 /* MTE memory tag segment type.  */
 #define PT_AARCH64_MEMTAG_MTE	(PT_LOPROC + 2)
 
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_AARCH64_CHERI_PURECAP 0x00010000
+
 /* AArch64 specific values for the Dyn d_tag field.  */
 #define DT_AARCH64_BTI_PLT	(DT_LOPROC + 1)
 #define DT_AARCH64_PAC_PLT	(DT_LOPROC + 3)

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [glibc/arm/morello/main] elf: add EF_AARCH64_CHERI_PURECAP
@ 2022-10-26 15:15 Szabolcs Nagy
  0 siblings, 0 replies; 4+ messages in thread
From: Szabolcs Nagy @ 2022-10-26 15:15 UTC (permalink / raw)
  To: glibc-cvs

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=11e656b4b3ca2d71fe7ebb8845e03b082d82d805

commit 11e656b4b3ca2d71fe7ebb8845e03b082d82d805
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date:   Fri Apr 29 14:27:32 2022 +0100

    elf: add EF_AARCH64_CHERI_PURECAP

Diff:
---
 elf/elf.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/elf/elf.h b/elf/elf.h
index f61eced554..4a5653c419 100644
--- a/elf/elf.h
+++ b/elf/elf.h
@@ -2906,6 +2906,9 @@ enum
 /* MTE memory tag segment type.  */
 #define PT_AARCH64_MEMTAG_MTE	(PT_LOPROC + 2)
 
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_AARCH64_CHERI_PURECAP 0x00010000
+
 /* AArch64 specific values for the Dyn d_tag field.  */
 #define DT_AARCH64_BTI_PLT	(DT_LOPROC + 1)
 #define DT_AARCH64_PAC_PLT	(DT_LOPROC + 3)

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-11-23 14:44 UTC | newest]

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2022-10-27 13:54 Szabolcs Nagy
2022-11-23 14:44 Szabolcs Nagy

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