From: Shiqi Zhang <shiqi@isrc.iscas.ac.cn>
To: Andreas Schwab <schwab@linux-m68k.org>
Cc: libc-alpha@sourceware.org
Subject: Re: [PATCH] riscv: Add macros for FPUCW in fpu_control.h
Date: Sun, 12 Feb 2023 14:29:57 +0800 [thread overview]
Message-ID: <0e733efc-2f2a-bfb6-44e3-c053f2d41f34@isrc.iscas.ac.cn> (raw)
In-Reply-To: <87357cvtpo.fsf@igel.home>
>> +# define _FPU_RM_DYN (7 << 5)
> That is only valid in an insn encoding, not in the fcsr register.
Thank you very much for the tip!
>> +/* FPU accrued exception flags */
>> +# define _FPU_EXCEPT_NV (1 << 0)
>> +# define _FPU_EXCEPT_NZ (1 << 1)
>> +# define _FPU_EXCEPT_OF (1 << 2)
>> +# define _FPU_EXCEPT_UF (1 << 3)
>> +# define _FPU_EXCEPT_NX (1 << 4)
> You got them backwards.
Sorry for my carelessness. I mistakenly assumed that flags in table 11.2
was listed from lower to higher bits. Will send a v2 soon.
prev parent reply other threads:[~2023-02-12 6:30 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-11 17:49 Shiqi Zhang
2023-02-11 20:21 ` Andreas Schwab
2023-02-12 6:29 ` Shiqi Zhang [this message]
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