Re: [PATCH v2 0/3] RISC-V: ifunced memcpy using new kernel hwprobe interface

[Adhemerval Zanella Netto <adhemerval.zanella@linaro.org>]

On 30/03/23 03:20, Jeff Law wrote:
> 
> 
> On 3/29/23 13:45, Palmer Dabbelt wrote:
> 
>> It's not in for-next yet, but various patch sets / proposals have been on the lists for a few months and it seems like discussion on the kernel side has pretty much died down.  That's why I was pinging the glibc side of things, if anyone here has comments on the interface then it's time to chime in.  If there's no comments then we're likely to end up with this in the next release (so queue into for-next soon, Linus' master in a month or so).
> Right.  And I've suggested that we at least try to settle on the various mem* and str* implementations independently of the kernel->glibc interface question.
> 
> I don't much care how we break down the problem of selecting implementations, just that we get started.   That can and probably should be happening in parallel with the kernel->glibc API work.
> 
> I've got some performance testing to do in this space (primarily of the VRULL implementations).  It's just going to take a long time to get the data.  And that implementation probably needs some revamping after all the work on the mem* and str* infrastructure that landed earlier this year.
> 

I don't think glibc is the right place for code dump, specially for implementations
that does not have representative performance numbers in real hardware and might
require further tuning.  It can be even tricky if you require different build config 
to testing as used to have for some ABI (for instance on powerpc with --with-cpu),
at least for ifunc we have some mechanism to test multiple variants assuming the 
chips at least support (which should be case for unaligned).

For ARM we have the optimize-routines [1] project, where we use as testbed for 
multiple implementations and also, due its license mechanism, make it easier to 
implement the optimized routines on different projects.  We used to have a similar 
project, cortex-strings, on Linaro.

So for experimental routines, where you expect to have frequent tuning based on
once you have tested and benchmarks on different chips; an external project
might a better idea; and sync with glibc once the routines are tested and validate.
And these RISCV does seemed to be still very experimental, where performance numbers 
are still synthetic ones from emulators.

Another possibility might to improve the generic implementation, as we have done
recently where RISCV bitmanip was a matter to add just 2 files and 4 functions
to optimize multiple string functions [2].  I have some WIP patches to add support
for unaligned memcpy/memmove with a very simple strategy.

[1] https://github.com/ARM-software/optimized-routines
[2] https://sourceware.org/git/?p=glibc.git;a=commit;h=25788431c0f5264c4830415de0cdd4d9926cbad9