[PATCH 1/2] Document cache information sysconf variables

[PATCH 1/2] Document cache information sysconf variables

[Siddhesh Poyarekar]

Write short one line descriptions for each of the cache information sysconf
variables.

	* manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE,
	_SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE,
	_SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC,
	_SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL2_CACHE_SIZE,
	_SC_LEVEL2_CACHE_ASSOC, _SC_LEVEL2_CACHE_LINESIZE,
	_SC_LEVEL3_CACHE_SIZE, _SC_LEVEL3_CACHE_ASSOC,
	_SC_LEVEL3_CACHE_LINESIZE, _SC_LEVEL4_CACHE_SIZE,
	_SC_LEVEL4_CACHE_ASSOC, _SC_LEVEL4_CACHE_LINESIZE): New
	variables.
---
 manual/conf.texi | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/manual/conf.texi b/manual/conf.texi
index 875862c..503b240 100644
--- a/manual/conf.texi
+++ b/manual/conf.texi
@@ -678,6 +678,67 @@ Inquire about the number of available physical pages in the system.
 Inquire about the number of functions which can be registered as termination
 functions for @code{atexit}; @pxref{Cleanups on Exit}.
 
+@item _SC_LEVEL1_ICACHE_SIZE
+@standards{GNU, unistd.h}
+Inquire about the size of the Level 1 instruction cache.
+
+@item _SC_LEVEL1_ICACHE_ASSOC
+@standards{GNU, unistd.h}
+Inquire about associativity of the Level 1 instruction cache.
+
+@item _SC_LEVEL1_ICACHE_LINESIZE
+@standards{GNU, unistd.h}
+Inquire about the line length of the Level 1 instruction cache.
+
+@item _SC_LEVEL1_DCACHE_SIZE
+@standards{GNU, unistd.h}
+Inquire about the size of the Level 1 data cache.
+
+@item _SC_LEVEL1_DCACHE_ASSOC
+@standards{GNU, unistd.h}
+Inquire about associativity of the Level 1 data cache.
+
+@item _SC_LEVEL1_DCACHE_LINESIZE
+@standards{GNU, unistd.h}
+Inquire about the line length of the Level 1 data cache.
+
+@item _SC_LEVEL2_CACHE_SIZE
+@standards{GNU, unistd.h}
+Inquire about the size of the Level 2 cache.
+
+@item _SC_LEVEL2_CACHE_ASSOC
+@standards{GNU, unistd.h}
+Inquire about associativity of the Level 2 cache.
+
+@item _SC_LEVEL2_CACHE_LINESIZE
+@standards{GNU, unistd.h}
+Inquire about the line length of the Level 2 cache.
+
+@item _SC_LEVEL3_CACHE_SIZE
+@standards{GNU, unistd.h}
+Inquire about the size of the Level 3 cache.
+
+@item _SC_LEVEL3_CACHE_ASSOC
+@standards{GNU, unistd.h}
+Inquire about associativity of the Level 3 cache.
+
+@item _SC_LEVEL3_CACHE_LINESIZE
+@standards{GNU, unistd.h}
+Inquire about the line length of the Level 3 cache.
+
+@item _SC_LEVEL4_CACHE_SIZE
+@standards{GNU, unistd.h}
+Inquire about the size of the Level 4 cache.
+
+@item _SC_LEVEL4_CACHE_ASSOC
+@standards{GNU, unistd.h}
+Inquire about associativity of the Level 4 cache.
+
+@item _SC_LEVEL4_CACHE_LINESIZE
+@standards{GNU, unistd.h}
+Inquire about the line length of the Level 4 cache.
+
+
 @item _SC_XOPEN_VERSION
 @standards{X/Open, unistd.h}
 Inquire about the parameter corresponding to @code{_XOPEN_VERSION}.
-- 
2.7.4

[PATCH 2/2] aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat

[Siddhesh Poyarekar]

The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the
ctr_el0 register, which tells us the minimum observable cache line
size by userspace.  This typically is the same as the L1 cache line
size, but that may not always be true.  It could be a higher level
cache line size as long as cache cleaning and invalidation work
correctly with that line size in userspace.  The falkor core for
example reports the L2 line size as the dcache line size in CTR_EL0
while also reporting the correct L1 dcache line size via CCSIDR_EL1.

	* manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE,
	_SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat.
---
 manual/conf.texi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/manual/conf.texi b/manual/conf.texi
index 503b240..66a7f35 100644
--- a/manual/conf.texi
+++ b/manual/conf.texi
@@ -690,6 +690,12 @@ Inquire about associativity of the Level 1 instruction cache.
 @standards{GNU, unistd.h}
 Inquire about the line length of the Level 1 instruction cache.
 
+On aarch64, the cache line size returned is the minimum instruction cache line
+size observeable by userspace.  This is typically the same as the L1 icache
+size but on some cores it may not be so.  It is specified in the architecture
+however that operations such as cache line invalidation are consistent with the
+size reported with this variable.
+
 @item _SC_LEVEL1_DCACHE_SIZE
 @standards{GNU, unistd.h}
 Inquire about the size of the Level 1 data cache.
@@ -702,6 +708,12 @@ Inquire about associativity of the Level 1 data cache.
 @standards{GNU, unistd.h}
 Inquire about the line length of the Level 1 data cache.
 
+On aarch64, the cache line size returned is the minimum data cache line size
+observeable by userspace.  This is typically the same as the L1 dcache size but
+on some cores it may not be so.  It is specified in the architecture however
+that operations such as cache line invalidation are consistent with the size
+reported with this variable.
+
 @item _SC_LEVEL2_CACHE_SIZE
 @standards{GNU, unistd.h}
 Inquire about the size of the Level 2 cache.
-- 
2.7.4

Re: [PATCH 2/2] aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat

[Szabolcs Nagy]

On 11/10/17 12:53, Siddhesh Poyarekar wrote:
> The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the
> ctr_el0 register, which tells us the minimum observable cache line
> size by userspace.  This typically is the same as the L1 cache line
> size, but that may not always be true.  It could be a higher level
> cache line size as long as cache cleaning and invalidation work
> correctly with that line size in userspace.  The falkor core for
> example reports the L2 line size as the dcache line size in CTR_EL0
> while also reporting the correct L1 dcache line size via CCSIDR_EL1.
> 
> 	* manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE,
> 	_SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat.

looks ok with the typo fixed below

> ---
>  manual/conf.texi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/manual/conf.texi b/manual/conf.texi
> index 503b240..66a7f35 100644
> --- a/manual/conf.texi
> +++ b/manual/conf.texi
> @@ -690,6 +690,12 @@ Inquire about associativity of the Level 1 instruction cache.
>  @standards{GNU, unistd.h}
>  Inquire about the line length of the Level 1 instruction cache.
>  
> +On aarch64, the cache line size returned is the minimum instruction cache line
> +size observeable by userspace.  This is typically the same as the L1 icache

*observable

> +size but on some cores it may not be so.  It is specified in the architecture
> +however that operations such as cache line invalidation are consistent with the
> +size reported with this variable.
> +
>  @item _SC_LEVEL1_DCACHE_SIZE
>  @standards{GNU, unistd.h}
>  Inquire about the size of the Level 1 data cache.
> @@ -702,6 +708,12 @@ Inquire about associativity of the Level 1 data cache.
>  @standards{GNU, unistd.h}
>  Inquire about the line length of the Level 1 data cache.
>  
> +On aarch64, the cache line size returned is the minimum data cache line size
> +observeable by userspace.  This is typically the same as the L1 dcache size but
> +on some cores it may not be so.  It is specified in the architecture however
> +that operations such as cache line invalidation are consistent with the size
> +reported with this variable.
> +
>  @item _SC_LEVEL2_CACHE_SIZE
>  @standards{GNU, unistd.h}
>  Inquire about the size of the Level 2 cache.
> 

Re: [PATCH 1/2] Document cache information sysconf variables

[Rical Jasan]

On 10/11/2017 04:53 AM, Siddhesh Poyarekar wrote:
> Write short one line descriptions for each of the cache information sysconf
> variables.
> 
> 	* manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE,
> 	_SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE,
> 	_SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC,
> 	_SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL2_CACHE_SIZE,
> 	_SC_LEVEL2_CACHE_ASSOC, _SC_LEVEL2_CACHE_LINESIZE,
> 	_SC_LEVEL3_CACHE_SIZE, _SC_LEVEL3_CACHE_ASSOC,
> 	_SC_LEVEL3_CACHE_LINESIZE, _SC_LEVEL4_CACHE_SIZE,
> 	_SC_LEVEL4_CACHE_ASSOC, _SC_LEVEL4_CACHE_LINESIZE): New
> 	variables.
> ---
>  manual/conf.texi | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 61 insertions(+)
> 
> diff --git a/manual/conf.texi b/manual/conf.texi
> index 875862c..503b240 100644
> --- a/manual/conf.texi
> +++ b/manual/conf.texi
> @@ -678,6 +678,67 @@ Inquire about the number of available physical pages in the system.
>  Inquire about the number of functions which can be registered as termination
>  functions for @code{atexit}; @pxref{Cleanups on Exit}.
>  
> +@item _SC_LEVEL1_ICACHE_SIZE
> +@standards{GNU, unistd.h}
> +Inquire about the size of the Level 1 instruction cache.
> +
> +@item _SC_LEVEL1_ICACHE_ASSOC
> +@standards{GNU, unistd.h}
> +Inquire about associativity of the Level 1 instruction cache.

I think this should be "the associativity".

> +
> +@item _SC_LEVEL1_ICACHE_LINESIZE
> +@standards{GNU, unistd.h}
> +Inquire about the line length of the Level 1 instruction cache.
> +
> +@item _SC_LEVEL1_DCACHE_SIZE
> +@standards{GNU, unistd.h}
> +Inquire about the size of the Level 1 data cache.
> +
> +@item _SC_LEVEL1_DCACHE_ASSOC
> +@standards{GNU, unistd.h}
> +Inquire about associativity of the Level 1 data cache.
> +
> +@item _SC_LEVEL1_DCACHE_LINESIZE
> +@standards{GNU, unistd.h}
> +Inquire about the line length of the Level 1 data cache.
> +
> +@item _SC_LEVEL2_CACHE_SIZE
> +@standards{GNU, unistd.h}
> +Inquire about the size of the Level 2 cache.
> +
> +@item _SC_LEVEL2_CACHE_ASSOC
> +@standards{GNU, unistd.h}
> +Inquire about associativity of the Level 2 cache.
> +
> +@item _SC_LEVEL2_CACHE_LINESIZE
> +@standards{GNU, unistd.h}
> +Inquire about the line length of the Level 2 cache.
> +
> +@item _SC_LEVEL3_CACHE_SIZE
> +@standards{GNU, unistd.h}
> +Inquire about the size of the Level 3 cache.
> +
> +@item _SC_LEVEL3_CACHE_ASSOC
> +@standards{GNU, unistd.h}
> +Inquire about associativity of the Level 3 cache.
> +
> +@item _SC_LEVEL3_CACHE_LINESIZE
> +@standards{GNU, unistd.h}
> +Inquire about the line length of the Level 3 cache.
> +
> +@item _SC_LEVEL4_CACHE_SIZE
> +@standards{GNU, unistd.h}
> +Inquire about the size of the Level 4 cache.
> +
> +@item _SC_LEVEL4_CACHE_ASSOC
> +@standards{GNU, unistd.h}
> +Inquire about associativity of the Level 4 cache.
> +
> +@item _SC_LEVEL4_CACHE_LINESIZE
> +@standards{GNU, unistd.h}
> +Inquire about the line length of the Level 4 cache.
> +
> +

Don't need the extra newline.

>  @item _SC_XOPEN_VERSION
>  @standards{X/Open, unistd.h}
>  Inquire about the parameter corresponding to @code{_XOPEN_VERSION}.

Otherwise, LGTM.

Rical

Re: [PATCH 2/2] aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat

[Rical Jasan]

I can't speak for the content, but the patch looks OK, save a couple
minor issues.

On 10/11/2017 04:53 AM, Siddhesh Poyarekar wrote:
> The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the
> ctr_el0 register, which tells us the minimum observable cache line
> size by userspace.  This typically is the same as the L1 cache line
> size, but that may not always be true.  It could be a higher level
> cache line size as long as cache cleaning and invalidation work
> correctly with that line size in userspace.  The falkor core for
> example reports the L2 line size as the dcache line size in CTR_EL0
> while also reporting the correct L1 dcache line size via CCSIDR_EL1.
> 
> 	* manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE,
> 	_SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat.
> ---
>  manual/conf.texi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/manual/conf.texi b/manual/conf.texi
> index 503b240..66a7f35 100644
> --- a/manual/conf.texi
> +++ b/manual/conf.texi
> @@ -690,6 +690,12 @@ Inquire about associativity of the Level 1 instruction cache.
>  @standards{GNU, unistd.h}
>  Inquire about the line length of the Level 1 instruction cache.
>  
> +On aarch64, the cache line size returned is the minimum instruction cache line
> +size observeable by userspace.  This is typically the same as the L1 icache

observable

> +size but on some cores it may not be so.  It is specified in the architecture
> +however that operations such as cache line invalidation are consistent with the

I would write, "...architecture, however, ...", or begin the sentence
with "However, ...".

> +size reported with this variable.
> +
>  @item _SC_LEVEL1_DCACHE_SIZE
>  @standards{GNU, unistd.h}
>  Inquire about the size of the Level 1 data cache.
> @@ -702,6 +708,12 @@ Inquire about associativity of the Level 1 data cache.
>  @standards{GNU, unistd.h}
>  Inquire about the line length of the Level 1 data cache.
>  
> +On aarch64, the cache line size returned is the minimum data cache line size
> +observeable by userspace.  This is typically the same as the L1 dcache size but

observable

> +on some cores it may not be so.  It is specified in the architecture however

Commas here too.

> +that operations such as cache line invalidation are consistent with the size
> +reported with this variable.
> +
>  @item _SC_LEVEL2_CACHE_SIZE
>  @standards{GNU, unistd.h}
>  Inquire about the size of the Level 2 cache.

Rical

Re: [PATCH 2/2] aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat

[Siddhesh Poyarekar]

Thanks, pushed with nits fixed.

Siddhesh

Re: [PATCH 1/2] Document cache information sysconf variables

[Siddhesh Poyarekar]

On Wednesday 18 October 2017 11:19 AM, Rical Jasan wrote:
>>  @item _SC_XOPEN_VERSION
>>  @standards{X/Open, unistd.h}
>>  Inquire about the parameter corresponding to @code{_XOPEN_VERSION}.
> 
> Otherwise, LGTM.

Thanks, pushed with nits fixed.

Siddhesh