From: Raoni Fassina Firmino <raoni@linux.ibm.com>
To: Florian Weimer <fweimer@redhat.com>
Cc: libc-alpha@sourceware.org, tuliom@linux.ibm.com,
rzinsly@linux.ibm.com, anton@ozlabs.org
Subject: Re: [PATCH v2] powerpc64le: Optimize memset for POWER10
Date: Fri, 30 Apr 2021 09:16:33 -0300 [thread overview]
Message-ID: <20210430121633.kqfheh2tidgyiyap@work-tp> (raw)
In-Reply-To: <87sg38cr1h.fsf@oldenburg.str.redhat.com>
On Fri, Apr 30, 2021 at 06:52:42AM +0200, AL glibc-alpha wrote:
> * Raoni Fassina Firmino via Libc-alpha:
>
> > +L(dcbz_loop):
> > + /* Sets 512 bytes to zero in each iteration, the loop unrolling shows
> > + a throughput boost for large sizes (2048 bytes or higher). */
> > + dcbz 0,r6
> > + dcbz r9,r6
> > + dcbz r10,r6
> > + dcbz r11,r6
> > + addi r6,r6,512
> > + bdnz L(dcbz_loop)
>
> > +# ifdef __LITTLE_ENDIAN__
> > + (hwcap2 & (PPC_FEATURE2_ARCH_3_1 | PPC_FEATURE2_HAS_ISEL)
> > + && hwcap & PPC_FEATURE_HAS_VSX)
> > + ? __memset_power10 :
> > +# endif
>
> Should the IFUNC resolver check that the cache line size is 128 bytes?
I'm not sure, this part was taken from power8 version and for that it
does not check the cache line size. In fact I looked all other memset
versions (power7, power6, power4 and ppc), and only the ppc version does
not assume a 128 bytes cache line. And none has this check (and all of
them uses dcbz). So I don't know.
next prev parent reply other threads:[~2021-04-30 12:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-29 23:45 Raoni Fassina Firmino
2021-04-30 4:52 ` Florian Weimer
2021-04-30 12:16 ` Raoni Fassina Firmino [this message]
2021-04-30 12:21 ` Florian Weimer
2021-04-30 12:23 ` Florian Weimer
2021-04-30 13:02 ` Matheus Castanho
2021-04-30 21:15 ` Tulio Magno Quites Machado Filho
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