* [PATCH 1/4] MIPS: rework local_t operation on MIPS64
@ 2021-11-18 9:29 Huang Pei
2021-11-18 9:29 ` [PATCH 2/4] MIPS: fix tx39_flush_cache_page Huang Pei
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Huang Pei @ 2021-11-18 9:29 UTC (permalink / raw)
To: Joseph Myers, ambrosehua; +Cc: libc-alpha, Huacai Chen, Chenghua Xu
+. Use daddu/dsubu for long int on MIPS64.
+. remove "asm/war.h" since R10000_LLSC_WAR became a config option
+. clean up, no function changed
Suggested-by: "Maciej W. Rozycki" <macro@orcam.me.uk>
Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
arch/mips/include/asm/asm.h | 18 ++++++++++
arch/mips/include/asm/local.h | 62 +++++++++--------------------------
2 files changed, 33 insertions(+), 47 deletions(-)
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 2f8ce94ebaaf..f3302b13d3e0 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -19,6 +19,7 @@
#include <asm/sgidefs.h>
#include <asm/asm-eva.h>
+#include <asm/isa-rev.h>
#ifndef __VDSO__
/*
@@ -211,6 +212,8 @@ symbol = value
#define LONG_SUB sub
#define LONG_SUBU subu
#define LONG_L lw
+#define LONG_LL ll
+#define LONG_SC sc
#define LONG_S sw
#define LONG_SP swp
#define LONG_SLL sll
@@ -236,6 +239,8 @@ symbol = value
#define LONG_SUB dsub
#define LONG_SUBU dsubu
#define LONG_L ld
+#define LONG_LL lld
+#define LONG_SC scd
#define LONG_S sd
#define LONG_SP sdp
#define LONG_SLL dsll
@@ -320,6 +325,19 @@ symbol = value
#define SSNOP sll zero, zero, 1
+/*
+ * Using a branch-likely instruction to check the result of an sc instruction
+ * works around a bug present in R10000 CPUs prior to revision 3.0 that could
+ * cause ll-sc sequences to execute non-atomically.
+ */
+#ifdef CONFIG_WAR_R10000_LLSC
+# define SC_BEQZ beqzl
+#elif MIPS_ISA_REV >= 6
+# define SC_BEQZ beqzc
+#else
+# define SC_BEQZ beqz
+#endif
+
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h>
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index ecda7295ddcd..c1e109357110 100644
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -7,7 +7,7 @@
#include <linux/atomic.h>
#include <asm/cmpxchg.h>
#include <asm/compiler.h>
-#include <asm/war.h>
+#include <asm/asm.h>
typedef struct
{
@@ -31,34 +31,18 @@ static __inline__ long local_add_return(long i, local_t * l)
{
unsigned long result;
- if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set push \n"
- " .set arch=r4000 \n"
- __SYNC(full, loongson3_war) " \n"
- "1:" __LL "%1, %2 # local_add_return \n"
- " addu %0, %1, %3 \n"
- __SC "%0, %2 \n"
- " beqzl %0, 1b \n"
- " addu %0, %1, %3 \n"
- " .set pop \n"
- : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
- : "Ir" (i), "m" (l->a.counter)
- : "memory");
- } else if (kernel_uses_llsc) {
+ if (kernel_uses_llsc) {
unsigned long temp;
__asm__ __volatile__(
" .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
- __SYNC(full, loongson3_war) " \n"
- "1:" __LL "%1, %2 # local_add_return \n"
- " addu %0, %1, %3 \n"
- __SC "%0, %2 \n"
- " beqz %0, 1b \n"
- " addu %0, %1, %3 \n"
+ __SYNC(full, loongson3_war) " \n"
+ "1:" __stringify(LONG_LL) " %1, %2 \n"
+ " "__stringify(LONG_ADDU) " %0, %1, %3 \n"
+ " "__stringify(LONG_SC) " %0, %2 \n"
+ " "__stringify(SC_BEQZ) " %0, 1b \n"
+ " "__stringify(LONG_ADDU) " %0, %1, %3 \n"
" .set pop \n"
: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
: "Ir" (i), "m" (l->a.counter)
@@ -80,34 +64,18 @@ static __inline__ long local_sub_return(long i, local_t * l)
{
unsigned long result;
- if (kernel_uses_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) {
- unsigned long temp;
-
- __asm__ __volatile__(
- " .set push \n"
- " .set arch=r4000 \n"
- __SYNC(full, loongson3_war) " \n"
- "1:" __LL "%1, %2 # local_sub_return \n"
- " subu %0, %1, %3 \n"
- __SC "%0, %2 \n"
- " beqzl %0, 1b \n"
- " subu %0, %1, %3 \n"
- " .set pop \n"
- : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
- : "Ir" (i), "m" (l->a.counter)
- : "memory");
- } else if (kernel_uses_llsc) {
+ if (kernel_uses_llsc) {
unsigned long temp;
__asm__ __volatile__(
" .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
- __SYNC(full, loongson3_war) " \n"
- "1:" __LL "%1, %2 # local_sub_return \n"
- " subu %0, %1, %3 \n"
- __SC "%0, %2 \n"
- " beqz %0, 1b \n"
- " subu %0, %1, %3 \n"
+ __SYNC(full, loongson3_war) " \n"
+ "1:" __stringify(LONG_LL) " %1, %2 \n"
+ " "__stringify(LONG_SUBU) " %0, %1, %3 \n"
+ " "__stringify(LONG_SC) " %0, %2 \n"
+ " "__stringify(SC_BEQZ) " %0, 1b \n"
+ " "__stringify(LONG_SUBU) " %0, %1, %3 \n"
" .set pop \n"
: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
: "Ir" (i), "m" (l->a.counter)
--
2.20.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/4] MIPS: fix tx39_flush_cache_page
2021-11-18 9:29 [PATCH 1/4] MIPS: rework local_t operation on MIPS64 Huang Pei
@ 2021-11-18 9:29 ` Huang Pei
2021-11-18 9:29 ` [PATCH 3/4] MIPS: use 3-level pgtable for 64KB page size on MIPS_VA_BITS_48 Huang Pei
2021-11-18 9:29 ` [PATCH 4/4] MIPS: fix FTLB configuration Huang Pei
2 siblings, 0 replies; 4+ messages in thread
From: Huang Pei @ 2021-11-18 9:29 UTC (permalink / raw)
To: Joseph Myers, ambrosehua; +Cc: libc-alpha, Huacai Chen, Chenghua Xu
Indexed cache operation need KSEG0 address for safety and assume
that no dcache alias nor high memory
Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
arch/mips/mm/c-tx39.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 03dfbb40ec73..49e4a16186ce 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -170,6 +170,7 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
struct mm_struct *mm = vma->vm_mm;
pmd_t *pmdp;
pte_t *ptep;
+ unsigned long vaddr = phys_to_virt(pfn_to_phys(pfn));
/*
* If ownes no valid ASID yet, cannot possibly have gotten
@@ -207,11 +208,14 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
/*
* Do indexed flush, too much work to get the (possible) TLB refills
* to work correctly.
+ *
+ * Assuming that tx39 family do not support high memory, nor has
+ * dcache alias, vaddr can index dcache directly and correctly
*/
if (cpu_has_dc_aliases || exec)
- tx39_blast_dcache_page_indexed(page);
+ tx39_blast_dcache_page_indexed(vaddr);
if (exec)
- tx39_blast_icache_page_indexed(page);
+ tx39_blast_icache_page_indexed(vaddr);
}
static void local_tx39_flush_data_cache_page(void * addr)
--
2.20.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 3/4] MIPS: use 3-level pgtable for 64KB page size on MIPS_VA_BITS_48
2021-11-18 9:29 [PATCH 1/4] MIPS: rework local_t operation on MIPS64 Huang Pei
2021-11-18 9:29 ` [PATCH 2/4] MIPS: fix tx39_flush_cache_page Huang Pei
@ 2021-11-18 9:29 ` Huang Pei
2021-11-18 9:29 ` [PATCH 4/4] MIPS: fix FTLB configuration Huang Pei
2 siblings, 0 replies; 4+ messages in thread
From: Huang Pei @ 2021-11-18 9:29 UTC (permalink / raw)
To: Joseph Myers, ambrosehua; +Cc: libc-alpha, Huacai Chen, Chenghua Xu
It hangup when booting Loongson 3A1000 with BOTH
CONFIG_PAGE_SIZE_64KB and CONFIG_MIPS_VA_BITS_48, that it turn
out to use 2-level pgtable instead of 3-level. 64KB page size
with 2-level pgtable only cover 42 bits VA, use 3-level pgtable
to cover all 48 bits VA(55 bits)
Fixes: 1e321fa917fb ("MIPS64: Support of at least 48 bits of SEGBITS)
Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
arch/mips/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index de60ad190057..0215dc1529e9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3097,7 +3097,7 @@ config STACKTRACE_SUPPORT
config PGTABLE_LEVELS
int
default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
- default 3 if 64BIT && !PAGE_SIZE_64KB
+ default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
default 2
config MIPS_AUTO_PFN_OFFSET
--
2.20.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 4/4] MIPS: fix FTLB configuration
2021-11-18 9:29 [PATCH 1/4] MIPS: rework local_t operation on MIPS64 Huang Pei
2021-11-18 9:29 ` [PATCH 2/4] MIPS: fix tx39_flush_cache_page Huang Pei
2021-11-18 9:29 ` [PATCH 3/4] MIPS: use 3-level pgtable for 64KB page size on MIPS_VA_BITS_48 Huang Pei
@ 2021-11-18 9:29 ` Huang Pei
2 siblings, 0 replies; 4+ messages in thread
From: Huang Pei @ 2021-11-18 9:29 UTC (permalink / raw)
To: Joseph Myers, ambrosehua; +Cc: libc-alpha, Huacai Chen, Chenghua Xu
Commit "da1bd29742b1" makes 'set_ftlb_enable' called under
c->cputype unset, which leaves FTLB disabled on BOTH 3A2000
and 3A3000
Fixes: da1bd29742b1 ("MIPS: Loongson64: Probe CPU features via CPUCFG")
Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
arch/mips/kernel/cpu-probe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ac0e2cfc6d57..24a529c6c4be 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1734,8 +1734,6 @@ static inline void decode_cpucfg(struct cpuinfo_mips *c)
static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
{
- decode_configs(c);
-
/* All Loongson processors covered here define ExcCode 16 as GSExc. */
c->options |= MIPS_CPU_GSEXCEX;
@@ -1796,6 +1794,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
panic("Unknown Loongson Processor ID!");
break;
}
+
+ decode_configs(c);
}
#else
static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
--
2.20.1
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-11-18 9:29 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-11-18 9:29 [PATCH 1/4] MIPS: rework local_t operation on MIPS64 Huang Pei
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2021-11-18 9:29 ` [PATCH 3/4] MIPS: use 3-level pgtable for 64KB page size on MIPS_VA_BITS_48 Huang Pei
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