[PATCH 0/4] riscv: Vectorized mem*/str* function

[PATCH 0/4] riscv: Vectorized mem*/str* function

[Vincent Chen]

This patch proposes implementations of memchr, memcmp, memcpy, memmove,
memset, strcat, strchr, strcmp, strcpy, strlen, strncat, strncmp,
strncpy and strnlen that leverage the RISC-V V extension (RVV), version
1.0 (https://github.com/riscv/riscv-v-spec/releases/tag/v1.0). These
routines are from https://github.com/sifive/sifive-libc, which we agree
to be contributed to the Free Software Foundation. With regards to
IFUNC, some details concerning `hwcap` are still under discussion in the
community. For the purposes of reviewing this patch, we have temporarily
opted for RVV delegation at compile time. Once the `hwcap` mechanism is
ready, we’ll rebase on it.

These routines assume VLEN is at least 32 bits, as is required by all
currently defined vector extensions, and they support arbitrarily large
VLEN. All implementations work for both RV32 and RV64 platforms, and
make no assumptions about page size.

The `mem*` (known-length) routines use LMUL=8 to minimize dynamic code
size, while the `str*` (unknown-length) routines use LMUL=1 instead.
Longer LMUL will still minimize dynamic code size for the latter
routines, but it will also increase the cost of the remainder/tail loop:
more data loaded and comparisons performed past the `\0`. This overhead
will be particularly pronounced for smaller strings.

Measured performance improvements of the vectorized ("rvv")
implementations vs. the existing Glibc ("scalar") implementations are as
follows:
memchr: 85% time savings (i.e., if scalar is 100ms, then rvv is 15ms)
memcmp: 55%
memcpy: 88%
memmove: 80%
memset: 88%
strcmp: 85%
strlen: 70%
strcat: 53%
strchr: 85%
strcpy: 70%
strncmp 90%
strncat: 50%
strncpy: 60%
strnlen: 80%
Above data are collected on SiFive X280 (FPGA simulation), across a wide
range of problem sizes.


Jerry Shih (2):
  riscv: vectorized mem* functions
  riscv: vectorized str* functions

Nick Knight (1):
  riscv: vectorized strchr and strnlen functions

Vincent Chen (1):
  riscv: Enabling vectorized mem*/str* functions in build time

 scripts/build-many-glibcs.py   |  10 +++
 sysdeps/riscv/preconfigure     |  19 +++++
 sysdeps/riscv/preconfigure.ac  |  18 +++++
 sysdeps/riscv/rv32/rvv/Implies |   2 +
 sysdeps/riscv/rv64/rvv/Implies |   2 +
 sysdeps/riscv/rvv/memchr.S     |  63 +++++++++++++++
 sysdeps/riscv/rvv/memcmp.S     |  75 ++++++++++++++++++
 sysdeps/riscv/rvv/memcpy.S     |  51 +++++++++++++
 sysdeps/riscv/rvv/memmove.S    |  72 ++++++++++++++++++
 sysdeps/riscv/rvv/memset.S     |  51 +++++++++++++
 sysdeps/riscv/rvv/strcat.S     |  72 ++++++++++++++++++
 sysdeps/riscv/rvv/strchr.S     |  53 +++++++++++++
 sysdeps/riscv/rvv/strcmp.S     | 135 +++++++++++++++++++++++++++++++++
 sysdeps/riscv/rvv/strcpy.S     |  56 ++++++++++++++
 sysdeps/riscv/rvv/strlen.S     |  54 +++++++++++++
 sysdeps/riscv/rvv/strncat.S    |  83 ++++++++++++++++++++
 sysdeps/riscv/rvv/strncmp.S    |  85 +++++++++++++++++++++
 sysdeps/riscv/rvv/strncpy.S    |  86 +++++++++++++++++++++
 sysdeps/riscv/rvv/strnlen.S    |  56 ++++++++++++++
 19 files changed, 1043 insertions(+)
 create mode 100644 sysdeps/riscv/rv32/rvv/Implies
 create mode 100644 sysdeps/riscv/rv64/rvv/Implies
 create mode 100644 sysdeps/riscv/rvv/memchr.S
 create mode 100644 sysdeps/riscv/rvv/memcmp.S
 create mode 100644 sysdeps/riscv/rvv/memcpy.S
 create mode 100644 sysdeps/riscv/rvv/memmove.S
 create mode 100644 sysdeps/riscv/rvv/memset.S
 create mode 100644 sysdeps/riscv/rvv/strcat.S
 create mode 100644 sysdeps/riscv/rvv/strchr.S
 create mode 100644 sysdeps/riscv/rvv/strcmp.S
 create mode 100644 sysdeps/riscv/rvv/strcpy.S
 create mode 100644 sysdeps/riscv/rvv/strlen.S
 create mode 100644 sysdeps/riscv/rvv/strncat.S
 create mode 100644 sysdeps/riscv/rvv/strncmp.S
 create mode 100644 sysdeps/riscv/rvv/strncpy.S
 create mode 100644 sysdeps/riscv/rvv/strnlen.S

-- 
2.25.1

[PATCH 1/4] riscv: Enabling vectorized mem*/str* functions in build time

[Vincent Chen]

Let the build selects the vectorized mem*/str* functions when it detects
the compiler supports RISC-V V extension and enables it in this build.

We agree that the these vectorized mem*/str* functions should be
selected by IFUNC. Therefore, this patch is intended as a
**temporary solution** to enable reviewers to evaluate the effectiveness
of these vectorized mem*/str* functions.
---
 scripts/build-many-glibcs.py   | 10 ++++++++++
 sysdeps/riscv/preconfigure     | 19 +++++++++++++++++++
 sysdeps/riscv/preconfigure.ac  | 18 ++++++++++++++++++
 sysdeps/riscv/rv32/rvv/Implies |  2 ++
 sysdeps/riscv/rv64/rvv/Implies |  2 ++
 5 files changed, 51 insertions(+)
 create mode 100644 sysdeps/riscv/rv32/rvv/Implies
 create mode 100644 sysdeps/riscv/rv64/rvv/Implies

diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py
index bd212dbc82..8ac86c50f6 100755
--- a/scripts/build-many-glibcs.py
+++ b/scripts/build-many-glibcs.py
@@ -381,6 +381,11 @@ class Context(object):
                         variant='rv32imafdc-ilp32d',
                         gcc_cfg=['--with-arch=rv32imafdc', '--with-abi=ilp32d',
                                  '--disable-multilib'])
+        self.add_config(arch='riscv32',
+                        os_name='linux-gnu',
+                        variant='rv32imafdcv-ilp32d',
+                        gcc_cfg=['--with-arch=rv32imafdcv', '--with-abi=ilp32d',
+                                 '--disable-multilib'])
         self.add_config(arch='riscv64',
                         os_name='linux-gnu',
                         variant='rv64imac-lp64',
@@ -396,6 +401,11 @@ class Context(object):
                         variant='rv64imafdc-lp64d',
                         gcc_cfg=['--with-arch=rv64imafdc', '--with-abi=lp64d',
                                  '--disable-multilib'])
+        self.add_config(arch='riscv64',
+                        os_name='linux-gnu',
+                        variant='rv64imafdcv-lp64d',
+                        gcc_cfg=['--with-arch=rv64imafdcv', '--with-abi=lp64d',
+                                 '--disable-multilib'])
         self.add_config(arch='s390x',
                         os_name='linux-gnu',
                         glibcs=[{},
diff --git a/sysdeps/riscv/preconfigure b/sysdeps/riscv/preconfigure
index 4dedf4b0bb..5ddc195b46 100644
--- a/sysdeps/riscv/preconfigure
+++ b/sysdeps/riscv/preconfigure
@@ -7,6 +7,7 @@ riscv*)
     flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'`
     float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'`
     atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2`
+    vector=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_vector' | cut -d' ' -f2`
 
     case "$xlen" in
     64 | 32)
@@ -32,6 +33,24 @@ riscv*)
 	;;
     esac
 
+    case "$vector" in
+    __riscv_vector)
+        case "$flen" in
+        64)
+        float_machine=rvv
+        ;;
+        *)
+        # V 1.0 spec requires both F and D extensions, but this may be an older version. Degrade to scalar only.
+        ;;
+        esac
+    ;;
+    *)
+    ;;
+    esac
+
+    { $as_echo "$as_me:${as_lineno-$LINENO}: vector $vector flen $flen float_machine $float_machine" >&5
+$as_echo "$as_me: vector $vector flen $flen float_machine $float_machine" >&6;}
+
     case "$float_abi" in
     soft)
 	abi_flen=0
diff --git a/sysdeps/riscv/preconfigure.ac b/sysdeps/riscv/preconfigure.ac
index a5c30e0dbf..b6b8bb46e4 100644
--- a/sysdeps/riscv/preconfigure.ac
+++ b/sysdeps/riscv/preconfigure.ac
@@ -7,6 +7,7 @@ riscv*)
     flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'`
     float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'`
     atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2`
+    vector=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_vector' | cut -d' ' -f2`
 
     case "$xlen" in
     64 | 32)
@@ -32,6 +33,23 @@ riscv*)
 	;;
     esac
 
+    case "$vector" in
+    __riscv_vector)
+        case "$flen" in
+        64)
+        float_machine=rvv
+        ;;
+        *)
+        # V 1.0 spec requires both F and D extensions, but this may be an older version. Degrade to scalar only.
+        ;;
+        esac
+    ;;
+    *)
+    ;;
+    esac
+
+    AC_MSG_NOTICE([vector $vector flen $flen float_machine $float_machine])
+
     case "$float_abi" in
     soft)
 	abi_flen=0
diff --git a/sysdeps/riscv/rv32/rvv/Implies b/sysdeps/riscv/rv32/rvv/Implies
new file mode 100644
index 0000000000..25ce1df222
--- /dev/null
+++ b/sysdeps/riscv/rv32/rvv/Implies
@@ -0,0 +1,2 @@
+riscv/rv32/rvd
+riscv/rvv
diff --git a/sysdeps/riscv/rv64/rvv/Implies b/sysdeps/riscv/rv64/rvv/Implies
new file mode 100644
index 0000000000..9993bb30e3
--- /dev/null
+++ b/sysdeps/riscv/rv64/rvv/Implies
@@ -0,0 +1,2 @@
+riscv/rv64/rvd
+riscv/rvv
-- 
2.25.1

[PATCH 2/4] riscv: vectorized mem* functions

[Vincent Chen]

From: Jerry Shih <jerry.shih@sifive.com>

This patch proposes implementations of memchr, memcmp, memcpy, memmove,
and memset that leverage the RISC-V V extension (RVV), version 1.0.
These routines assumes VLEN is at least 32 bits, as is required by all
currently defined vector extensions, and they support arbitrarily large
VLEN. All implementations work for both RV32 and RV64 platforms, and
make no assumptions about page size.
---
 sysdeps/riscv/rvv/memchr.S  | 63 +++++++++++++++++++++++++++++++
 sysdeps/riscv/rvv/memcmp.S  | 75 +++++++++++++++++++++++++++++++++++++
 sysdeps/riscv/rvv/memcpy.S  | 51 +++++++++++++++++++++++++
 sysdeps/riscv/rvv/memmove.S | 72 +++++++++++++++++++++++++++++++++++
 sysdeps/riscv/rvv/memset.S  | 51 +++++++++++++++++++++++++
 5 files changed, 312 insertions(+)
 create mode 100644 sysdeps/riscv/rvv/memchr.S
 create mode 100644 sysdeps/riscv/rvv/memcmp.S
 create mode 100644 sysdeps/riscv/rvv/memcpy.S
 create mode 100644 sysdeps/riscv/rvv/memmove.S
 create mode 100644 sysdeps/riscv/rvv/memset.S

diff --git a/sysdeps/riscv/rvv/memchr.S b/sysdeps/riscv/rvv/memchr.S
new file mode 100644
index 0000000000..6981a9f8b0
--- /dev/null
+++ b/sysdeps/riscv/rvv/memchr.S
@@ -0,0 +1,63 @@
+/* RVV versions memchr.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define iResult a0
+
+#define pSrc a0
+#define iValue a1
+#define iNum a2
+
+#define iVL a3
+#define iTemp a4
+
+#define ELEM_LMUL_SETTING m8
+#define vData v0
+#define vMask v8
+
+ENTRY(memchr)
+
+L(loop):
+    vsetvli zero, iNum, e8, ELEM_LMUL_SETTING, ta, ma
+
+    vle8ff.v vData, (pSrc)
+    /* Find the iValue inside the loaded data.  */
+    vmseq.vx vMask, vData, iValue
+    vfirst.m iTemp, vMask
+
+    /* Skip the loop if we find the matched value.  */
+    bgez iTemp, L(found)
+
+    csrr iVL, vl
+    sub iNum, iNum, iVL
+    add pSrc, pSrc, iVL
+
+    bnez iNum, L(loop)
+
+    li iResult, 0
+    ret
+
+L(found):
+    add iResult, pSrc, iTemp
+    ret
+
+END(memchr)
+libc_hidden_builtin_def (memchr)
diff --git a/sysdeps/riscv/rvv/memcmp.S b/sysdeps/riscv/rvv/memcmp.S
new file mode 100644
index 0000000000..b156ec524c
--- /dev/null
+++ b/sysdeps/riscv/rvv/memcmp.S
@@ -0,0 +1,75 @@
+/* RVV versions memcmp.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define iResult a0
+
+#define pSrc1 a0
+#define pSrc2 a1
+#define iNum a2
+
+#define iVL a3
+#define iTemp a4
+#define iTemp1 a5
+#define iTemp2 a6
+
+#define ELEM_LMUL_SETTING m8
+#define vData1 v0
+#define vData2 v8
+#define vMask v16
+
+ENTRY(memcmp)
+
+L(loop):
+    vsetvli iVL, iNum, e8, ELEM_LMUL_SETTING, ta, ma
+
+    vle8.v vData1, (pSrc1)
+    vle8.v vData2, (pSrc2)
+
+    vmsne.vv vMask, vData1, vData2
+    sub iNum, iNum, iVL
+    vfirst.m iTemp, vMask
+
+    /* Skip the loop if we find the different value between pSrc1 and pSrc2.  */
+    bgez iTemp, L(found)
+
+    add pSrc1, pSrc1, iVL
+    add pSrc2, pSrc2, iVL
+
+    bnez iNum, L(loop)
+
+    li iResult, 0
+    ret
+
+L(found):
+    add pSrc1, pSrc1, iTemp
+    add pSrc2, pSrc2, iTemp
+    lbu iTemp1, 0(pSrc1)
+    lbu iTemp2, 0(pSrc2)
+    sub iResult, iTemp1, iTemp2
+    ret
+
+END(memcmp)
+libc_hidden_builtin_def (memcmp)
+weak_alias (memcmp,bcmp)
+strong_alias (memcmp, __memcmpeq)
+libc_hidden_def (__memcmpeq)
+
diff --git a/sysdeps/riscv/rvv/memcpy.S b/sysdeps/riscv/rvv/memcpy.S
new file mode 100644
index 0000000000..de790fbe51
--- /dev/null
+++ b/sysdeps/riscv/rvv/memcpy.S
@@ -0,0 +1,51 @@
+/* RVV versions memcpy.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define pDst a0
+#define pSrc a1
+#define iNum a2
+
+#define iVL a3
+#define pDstPtr a4
+
+#define ELEM_LMUL_SETTING m8
+#define vData v0
+
+ENTRY(memcpy)
+
+    mv pDstPtr, pDst
+
+L(loop):
+    vsetvli iVL, iNum, e8, ELEM_LMUL_SETTING, ta, ma
+
+    vle8.v vData, (pSrc)
+    sub iNum, iNum, iVL
+    add pSrc, pSrc, iVL
+    vse8.v vData, (pDstPtr)
+    add pDstPtr, pDstPtr, iVL
+
+    bnez iNum, L(loop)
+
+    ret
+
+END(memcpy)
+libc_hidden_builtin_def (memcpy)
diff --git a/sysdeps/riscv/rvv/memmove.S b/sysdeps/riscv/rvv/memmove.S
new file mode 100644
index 0000000000..ed12744064
--- /dev/null
+++ b/sysdeps/riscv/rvv/memmove.S
@@ -0,0 +1,72 @@
+/* RVV versions memmove.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define pDst a0
+#define pSrc a1
+#define iNum a2
+
+#define iVL a3
+#define pDstPtr a4
+#define pSrcBackwardPtr a5
+#define pDstBackwardPtr a6
+
+#define ELEM_LMUL_SETTING m8
+#define vData v0
+
+ENTRY(memmove)
+
+    mv pDstPtr, pDst
+
+    /* If pSrc is equal or after pDst, all data in pSrc will be loaded before
+       overwrited for the overlapping case. We could use faster `forward-copy`.  */
+    bgeu pSrc, pDst, L(forward_copy_loop)
+    add pSrcBackwardPtr, pSrc, iNum
+    add pDstBackwardPtr, pDst, iNum
+    /* If pDst inside source data range, we need to use `backward_copy_loop` to
+       handle the overlapping issue.  */
+    bltu pDst, pSrcBackwardPtr, L(backward_copy_loop)
+
+L(forward_copy_loop):
+    vsetvli iVL, iNum, e8, ELEM_LMUL_SETTING, ta, ma
+
+    vle8.v vData, (pSrc)
+    sub iNum, iNum, iVL
+    add pSrc, pSrc, iVL
+    vse8.v vData, (pDstPtr)
+    add pDstPtr, pDstPtr, iVL
+
+    bnez iNum, L(forward_copy_loop)
+    ret
+
+L(backward_copy_loop):
+    vsetvli iVL, iNum, e8, ELEM_LMUL_SETTING, ta, ma
+
+    sub pSrcBackwardPtr, pSrcBackwardPtr, iVL
+    vle8.v vData, (pSrcBackwardPtr)
+    sub iNum, iNum, iVL
+    sub pDstBackwardPtr, pDstBackwardPtr, iVL
+    vse8.v vData, (pDstBackwardPtr)
+    bnez iNum, L(backward_copy_loop)
+    ret
+
+END(memmove)
+libc_hidden_builtin_def (memmove)
diff --git a/sysdeps/riscv/rvv/memset.S b/sysdeps/riscv/rvv/memset.S
new file mode 100644
index 0000000000..3a6c3d0afd
--- /dev/null
+++ b/sysdeps/riscv/rvv/memset.S
@@ -0,0 +1,51 @@
+/* RVV versions memset.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define pDst a0
+#define iValue a1
+#define iNum a2
+
+#define iVL a3
+#define iTemp a4
+#define pDstPtr a5
+
+#define ELEM_LMUL_SETTING m8
+#define vData v0
+
+ENTRY(memset)
+
+    mv pDstPtr, pDst
+
+    vsetvli iVL, iNum, e8, ELEM_LMUL_SETTING, ta, ma
+    vmv.v.x vData, iValue
+
+L(loop):
+    vse8.v vData, (pDstPtr)
+    sub iNum, iNum, iVL
+    add pDstPtr, pDstPtr, iVL
+    vsetvli iVL, iNum, e8, ELEM_LMUL_SETTING, ta, ma
+    bnez iNum, L(loop)
+
+    ret
+
+END(memset)
+libc_hidden_builtin_def (memset)
-- 
2.25.1

[PATCH 3/4] riscv: vectorized str* functions

[Vincent Chen]

From: Jerry Shih <jerry.shih@sifive.com>

This patch proposes implementations of strcat, strcmp, strcpy, strlen,
strncat, strncmp and strncpy that leverage the RISC-V V extension (RVV),
version 1.0. These routines assumes VLEN is at least 32 bits, as is
required by all currently defined vector extensions, and they support
arbitrarily large VLEN. All implementations work for both RV32 and RV64
platforms, and make no assumptions about page size.
---
 sysdeps/riscv/rvv/strcat.S  |  72 +++++++++++++++++++
 sysdeps/riscv/rvv/strcmp.S  | 135 ++++++++++++++++++++++++++++++++++++
 sysdeps/riscv/rvv/strcpy.S  |  56 +++++++++++++++
 sysdeps/riscv/rvv/strlen.S  |  54 +++++++++++++++
 sysdeps/riscv/rvv/strncat.S |  83 ++++++++++++++++++++++
 sysdeps/riscv/rvv/strncmp.S |  85 +++++++++++++++++++++++
 sysdeps/riscv/rvv/strncpy.S |  86 +++++++++++++++++++++++
 7 files changed, 571 insertions(+)
 create mode 100644 sysdeps/riscv/rvv/strcat.S
 create mode 100644 sysdeps/riscv/rvv/strcmp.S
 create mode 100644 sysdeps/riscv/rvv/strcpy.S
 create mode 100644 sysdeps/riscv/rvv/strlen.S
 create mode 100644 sysdeps/riscv/rvv/strncat.S
 create mode 100644 sysdeps/riscv/rvv/strncmp.S
 create mode 100644 sysdeps/riscv/rvv/strncpy.S

diff --git a/sysdeps/riscv/rvv/strcat.S b/sysdeps/riscv/rvv/strcat.S
new file mode 100644
index 0000000000..8a7779fd3c
--- /dev/null
+++ b/sysdeps/riscv/rvv/strcat.S
@@ -0,0 +1,72 @@
+/* RVV versions strcat.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define pDst a0
+#define pSrc a1
+#define pDstPtr a2
+
+#define iVL a3
+#define iCurrentVL a4
+#define iActiveElemPos a5
+
+#define ELEM_LMUL_SETTING m1
+#define vMask1 v0
+#define vMask2 v1
+#define vStr1 v8
+#define vStr2 v16
+
+ENTRY(strcat)
+
+    mv pDstPtr, pDst
+
+    /* Perform `strlen(dst)`.  */
+L(strlen_loop):
+    vsetvli iVL, zero, e8, ELEM_LMUL_SETTING, ta, ma
+
+    vle8ff.v vStr1, (pDstPtr)
+    vmseq.vx vMask1, vStr1, zero
+    csrr iCurrentVL, vl
+    vfirst.m iActiveElemPos, vMask1
+    add pDstPtr, pDstPtr, iCurrentVL
+    bltz iActiveElemPos, L(strlen_loop)
+
+    sub pDstPtr, pDstPtr, iCurrentVL
+    add pDstPtr, pDstPtr, iActiveElemPos
+
+    /* Perform `strcpy(dst, src)`.  */
+L(strcpy_loop):
+    vsetvli iVL, zero, e8, ELEM_LMUL_SETTING, ta, ma
+
+    vle8ff.v vStr1, (pSrc)
+    vmseq.vx vMask2, vStr1, zero
+    csrr iCurrentVL, vl
+    vfirst.m iActiveElemPos, vMask2
+    vmsif.m vMask1, vMask2
+    add pSrc, pSrc, iCurrentVL
+    vse8.v vStr1, (pDstPtr), vMask1.t
+    add pDstPtr, pDstPtr, iCurrentVL
+    bltz iActiveElemPos, L(strcpy_loop)
+
+    ret
+
+END(strcat)
+libc_hidden_builtin_def (strcat)
diff --git a/sysdeps/riscv/rvv/strcmp.S b/sysdeps/riscv/rvv/strcmp.S
new file mode 100644
index 0000000000..ff5bb252f3
--- /dev/null
+++ b/sysdeps/riscv/rvv/strcmp.S
@@ -0,0 +1,135 @@
+/* RVV versions strcmp.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http:/*www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define iResult a0
+
+#define pStr1 a0
+#define pStr2 a1
+
+#define iVL a2
+#define iTemp1 a3
+#define iTemp2 a4
+#define iLMUL1 a5
+#define iLMUL2 a6
+#define iLMUL4 a7
+
+#define iLMUL t0
+
+#define vStr1 v0
+#define vStr2 v8
+#define vMask1 v16
+#define vMask2 v17
+
+ENTRY(strcmp)
+
+    /* Increase the lmul using the following sequences:
+       1/2, 1/2, 1, 2, 4, 4, 4, ... .  */
+
+    /* lmul=1/2.  */
+    vsetvli iVL, zero, e8, mf2, ta, ma
+
+    vle8ff.v vStr1, (pStr1)
+    /* check if vStr1[i] == 0.  */
+    vmseq.vx vMask1, vStr1, zero
+
+    vle8ff.v vStr2, (pStr2)
+    /* check if vStr1[i] != vStr2[i].  */
+    vmsne.vv vMask2, vStr1, vStr2
+
+    /* find the index x for vStr1[x]==0.  */
+    vfirst.m iTemp1, vMask1
+    /* find the index x for vStr1[x]!=vStr2[x].  */
+    vfirst.m iTemp2, vMask2
+
+    bgez iTemp1, L(check1)
+    bgez iTemp2, L(check2)
+
+    /* get the current vl updated by vle8ff.  */
+    csrr iVL, vl
+    add pStr1, pStr1, iVL
+    add pStr2, pStr2, iVL
+
+    vsetvli iVL, zero, e8, mf2, ta, ma
+    addi iLMUL1, zero, 1
+    addi iLMUL, zero, 1
+    j L(loop)
+L(m1):
+    vsetvli iVL, zero, e8, m1, ta, ma
+    addi iLMUL2, zero, 2
+    addi iLMUL, zero, 2
+    j L(loop)
+L(m2):
+    vsetvli iVL, zero, e8, m2, ta, ma
+    addi iLMUL4, zero, 4
+    addi iLMUL, zero, 4
+    j L(loop)
+L(m4):
+    vsetvli iVL, zero, e8, m4, ta, ma
+
+L(loop):
+    vle8ff.v vStr1, (pStr1)
+    vmseq.vx vMask1, vStr1, zero
+
+    vle8ff.v vStr2, (pStr2)
+    vmsne.vv vMask2, vStr1, vStr2
+
+    vfirst.m iTemp1, vMask1
+    vfirst.m iTemp2, vMask2
+
+    bgez iTemp1, L(check1)
+    bgez iTemp2, L(check2)
+
+    csrr iVL, vl
+    add pStr1, pStr1, iVL
+    add pStr2, pStr2, iVL
+
+    beq iLMUL, iLMUL1, L(m1)
+    beq iLMUL, iLMUL2, L(m2)
+    beq iLMUL, iLMUL4, L(m4)
+    j L(loop)
+
+    /* iTemp1>=0.  */
+L(check1):
+    bltz iTemp2, 1f
+    blt iTemp2, iTemp1, L(check2)
+1:
+    /* iTemp2<0
+       iTemp2>=0 && iTemp1<iTemp2.  */
+    add pStr1, pStr1, iTemp1
+    add pStr2, pStr2, iTemp1
+    lbu iTemp1, 0(pStr1)
+    lbu iTemp2, 0(pStr2)
+    sub iResult, iTemp1, iTemp2
+    ret
+
+    /* iTemp1<0
+       iTemp2>=0.  */
+L(check2):
+    add pStr1, pStr1, iTemp2
+    add pStr2, pStr2, iTemp2
+    lbu iTemp1, 0(pStr1)
+    lbu iTemp2, 0(pStr2)
+    sub iResult, iTemp1, iTemp2
+    ret
+
+END(strcmp)
+libc_hidden_builtin_def (strcmp)
diff --git a/sysdeps/riscv/rvv/strcpy.S b/sysdeps/riscv/rvv/strcpy.S
new file mode 100644
index 0000000000..8fb754ee23
--- /dev/null
+++ b/sysdeps/riscv/rvv/strcpy.S
@@ -0,0 +1,56 @@
+/* RVV versions strcpy.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define pDst a0
+#define pSrc a1
+#define pDstPtr a2
+
+#define iVL a3
+#define iCurrentVL a4
+#define iActiveElemPos a5
+
+#define ELEM_LMUL_SETTING m1
+#define vMask1 v0
+#define vMask2 v1
+#define vStr1 v8
+#define vStr2 v16
+
+ENTRY(strcpy)
+
+    mv pDstPtr, pDst
+
+L(strcpy_loop):
+    vsetvli iVL, zero, e8, ELEM_LMUL_SETTING, ta, ma
+    vle8ff.v vStr1, (pSrc)
+    vmseq.vx vMask2, vStr1, zero
+    csrr iCurrentVL, vl
+    vfirst.m iActiveElemPos, vMask2
+    vmsif.m vMask1, vMask2
+    add pSrc, pSrc, iCurrentVL
+    vse8.v vStr1, (pDstPtr), vMask1.t
+    add pDstPtr, pDstPtr, iCurrentVL
+    bltz iActiveElemPos, L(strcpy_loop)
+
+    ret
+
+END(strcpy)
+libc_hidden_builtin_def (strcpy)
diff --git a/sysdeps/riscv/rvv/strlen.S b/sysdeps/riscv/rvv/strlen.S
new file mode 100644
index 0000000000..eb456b094b
--- /dev/null
+++ b/sysdeps/riscv/rvv/strlen.S
@@ -0,0 +1,54 @@
+/* RVV versions strlen.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define iResult a0
+#define pStr a0
+#define pCopyStr a1
+#define iVL a2
+#define iCurrentVL a2
+#define iEndOffset a3
+
+#define ELEM_LMUL_SETTING m2
+#define vStr v0
+#define vMaskEnd v2
+
+ENTRY(strlen)
+
+    mv pCopyStr, pStr
+L(loop):
+    vsetvli iVL, zero, e8, ELEM_LMUL_SETTING, ta, ma
+    vle8ff.v vStr, (pCopyStr)
+    csrr iCurrentVL, vl
+    vmseq.vi vMaskEnd, vStr, 0
+    vfirst.m iEndOffset, vMaskEnd
+    add pCopyStr, pCopyStr, iCurrentVL
+    bltz iEndOffset, L(loop)
+
+    add pStr, pStr, iCurrentVL
+    add pCopyStr, pCopyStr, iEndOffset
+    sub iResult, pCopyStr, iResult
+
+    ret
+
+END(strlen)
+
+libc_hidden_builtin_def (strlen)
diff --git a/sysdeps/riscv/rvv/strncat.S b/sysdeps/riscv/rvv/strncat.S
new file mode 100644
index 0000000000..7847c4f008
--- /dev/null
+++ b/sysdeps/riscv/rvv/strncat.S
@@ -0,0 +1,83 @@
+/* RVV versions strncat.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define pDst a0
+#define pSrc a1
+#define iLength a2
+#define pDstPtr a3
+
+#define iVL a4
+#define iCurrentVL a5
+#define iActiveElemPos a6
+
+#define ELEM_LMUL_SETTING m1
+#define vMask1 v0
+#define vMask2 v1
+#define vStr1 v8
+#define vStr2 v16
+
+ENTRY(strncat)
+
+    mv pDstPtr, pDst
+
+    /* the strlen of dst.  */
+L(strlen_loop):
+    vsetvli iVL, zero, e8, ELEM_LMUL_SETTING, ta, ma
+
+    vle8ff.v vStr1, (pDstPtr)
+    /* find the '\0'.  */
+    vmseq.vx vMask1, vStr1, zero
+    csrr iCurrentVL, vl
+    vfirst.m iActiveElemPos, vMask1
+    add pDstPtr, pDstPtr, iCurrentVL
+    bltz iActiveElemPos, L(strlen_loop)
+
+    sub pDstPtr, pDstPtr, iCurrentVL
+    add pDstPtr, pDstPtr, iActiveElemPos
+
+    /* copy pSrc to pDstPtr.  */
+L(strcpy_loop):
+    vsetvli zero, iLength, e8, ELEM_LMUL_SETTING, ta, ma
+
+    vle8ff.v vStr1, (pSrc)
+    vmseq.vx vMask2, vStr1, zero
+    csrr iCurrentVL, vl
+    vfirst.m iActiveElemPos, vMask2
+    vmsif.m vMask1, vMask2
+    add pSrc, pSrc, iCurrentVL
+    sub iLength, iLength, iCurrentVL
+    vse8.v vStr1, (pDstPtr), vMask1.t
+    add pDstPtr, pDstPtr, iCurrentVL
+    beqz iLength, L(fill_zero)
+    bltz iActiveElemPos, L(strcpy_loop)
+
+    ret
+
+L(fill_zero):
+    bgez iActiveElemPos, L(fill_zero_end)
+    sb zero, (pDstPtr)
+
+L(fill_zero_end):
+    ret
+
+END(strncat)
+libc_hidden_builtin_def (strncat)
diff --git a/sysdeps/riscv/rvv/strncmp.S b/sysdeps/riscv/rvv/strncmp.S
new file mode 100644
index 0000000000..168dbb07ce
--- /dev/null
+++ b/sysdeps/riscv/rvv/strncmp.S
@@ -0,0 +1,85 @@
+/* RVV versions strncmp.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http:/*www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define iResult a0
+
+#define pStr1 a0
+#define pStr2 a1
+#define iLength a2
+
+#define iVL a3
+#define iTemp1 a4
+#define iTemp2 a5
+
+#define ELEM_LMUL_SETTING m1
+#define vStr1 v0
+#define vStr2 v4
+#define vMask1 v8
+#define vMask2 v9
+
+ENTRY(strncmp)
+
+    beqz iLength, L(zero_length)
+
+L(loop):
+    vsetvli zero, iLength, e8, ELEM_LMUL_SETTING, ta, ma
+
+    vle8ff.v vStr1, (pStr1)
+    /* vStr1[i] == 0.  */
+    vmseq.vx vMask1, vStr1, zero
+
+    vle8ff.v vStr2, (pStr2)
+    /* vStr1[i] != vStr2[i].  */
+    vmsne.vv vMask2, vStr1, vStr2
+
+    csrr iVL, vl
+
+    /* r = mask1 | mask2
+       We could use vfirst.m to get the first zero char or the
+       first different char between str1 and str2.  */
+    vmor.mm vMask1, vMask1, vMask2
+
+    sub iLength, iLength, iVL
+
+    vfirst.m iTemp1, vMask1
+
+    bgez iTemp1, L(end_loop)
+
+    add pStr1, pStr1, iVL
+    add pStr2, pStr2, iVL
+    bnez iLength, L(loop)
+L(end_loop):
+
+    add pStr1, pStr1, iTemp1
+    add pStr2, pStr2, iTemp1
+    lbu iTemp1, 0(pStr1)
+    lbu iTemp2, 0(pStr2)
+
+    sub iResult, iTemp1, iTemp2
+    ret
+
+L(zero_length):
+    li iResult, 0
+    ret
+
+END(strncmp)
+libc_hidden_builtin_def (strncmp)
diff --git a/sysdeps/riscv/rvv/strncpy.S b/sysdeps/riscv/rvv/strncpy.S
new file mode 100644
index 0000000000..e8d9450448
--- /dev/null
+++ b/sysdeps/riscv/rvv/strncpy.S
@@ -0,0 +1,86 @@
+/* RVV versions strncpy.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Jerry Shih <jerry.shih@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define pDst a0
+#define pSrc a1
+#define iLength a2
+#define pDstPtr a3
+
+#define iVL a4
+#define iCurrentVL a5
+#define iActiveElemPos a6
+#define iTemp a7
+
+#define ELEM_LMUL_SETTING m1
+#define vMask1 v0
+#define vMask2 v1
+#define ZERO_FILL_ELEM_LMUL_SETTING m8
+#define vStr1 v8
+#define vStr2 v16
+
+ENTRY(strncpy)
+
+    mv pDstPtr, pDst
+
+    /* Copy pSrc to pDstPtr.  */
+L(strcpy_loop):
+    vsetvli zero, iLength, e8, ELEM_LMUL_SETTING, ta, ma
+    vle8ff.v vStr1, (pSrc)
+    vmseq.vx vMask2, vStr1, zero
+    csrr iCurrentVL, vl
+    vfirst.m iActiveElemPos, vMask2
+    vmsif.m vMask1, vMask2
+    add pSrc, pSrc, iCurrentVL
+    sub iLength, iLength, iCurrentVL
+    vse8.v vStr1, (pDstPtr), vMask1.t
+    add pDstPtr, pDstPtr, iCurrentVL
+    bgez iActiveElemPos, L(fill_zero)
+    bnez iLength, L(strcpy_loop)
+    ret
+
+    /* Fill the tail zero.  */
+L(fill_zero):
+    /* We already copy the `\0` to dst. But we use `vfirst.m` to
+       get the `index` of `\0` position. We need to adjust `-1`
+       to get the correct remaining iLength for zero filling.  */
+    sub iTemp, iCurrentVL, iActiveElemPos
+    addi iTemp, iTemp, -1
+    add iLength, iLength, iTemp
+    /* Have an earily return for `strlen(src) + 1 == count` case.  */
+    bnez iLength, 1f
+    ret
+1:
+    sub pDstPtr, pDstPtr, iTemp
+    vsetvli zero, iLength, e8, ZERO_FILL_ELEM_LMUL_SETTING, ta, ma
+    vmv.v.x vStr2, zero
+
+L(fill_zero_loop):
+    vsetvli iVL, iLength, e8, ZERO_FILL_ELEM_LMUL_SETTING, ta, ma
+    vse8.v vStr2, (pDstPtr)
+    sub iLength, iLength, iVL
+    add pDstPtr, pDstPtr, iVL
+    bnez iLength, L(fill_zero_loop)
+
+    ret
+
+END(strncpy)
+libc_hidden_builtin_def (strncpy)
-- 
2.25.1

[PATCH 4/4] riscv: vectorized strchr and strnlen functions

[Vincent Chen]

From: Nick Knight <nick.knight@sifive.com>

This patch proposes implementations of strcat, strcmp, strcpy, strlen,
strncat, strncmp and strncpy that leverage the RISC-V V extension (RVV),
version 1.0. These routines assumes VLEN is at least 32 bits, as is
required by all currently defined vector extensions, and they support
arbitrarily large VLEN. All implementations work for both RV32 and RV64
platforms, and make no assumptions about page size.
---
 sysdeps/riscv/rvv/strchr.S  | 53 +++++++++++++++++++++++++++++++++++
 sysdeps/riscv/rvv/strnlen.S | 56 +++++++++++++++++++++++++++++++++++++
 2 files changed, 109 insertions(+)
 create mode 100644 sysdeps/riscv/rvv/strchr.S
 create mode 100644 sysdeps/riscv/rvv/strnlen.S

diff --git a/sysdeps/riscv/rvv/strchr.S b/sysdeps/riscv/rvv/strchr.S
new file mode 100644
index 0000000000..4a660200c3
--- /dev/null
+++ b/sysdeps/riscv/rvv/strchr.S
@@ -0,0 +1,53 @@
+/* RISC-V multiarch strchr, V-extension version.
+   Copyright (C) 2022 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by Nick Knight <nick.knight@sifive.com>.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+
+
+
+ENTRY(strchr)
+0:
+    vsetvli t0, zero, e8, m8, ta, ma
+    vle8ff.v v0, (a0)
+    vmseq.vi v8, v0, 0
+    vmseq.vx v9, v0, a1
+    vfirst.m a2, v8 /* first occurrence of \0 */
+    vfirst.m a3, v9 /* first occurrence of ch */
+    addi a4, a3, 1
+    seqz a4, a4
+    sltu a5, a2, a3
+    or a4, a4, a5
+    beqz a4, 1f /* Found ch, not preceded by \0? */
+    li a6, -1
+    csrr a5, vl
+    add a0, a0, a5
+    beq a2, a6, 0b /* Didn't find \0? */
+    li a0, 0
+    ret
+1:
+    add a0, a0, a3
+    ret
+
+END(strchr)
+weak_alias (strchr, index)
+libc_hidden_builtin_def (strchr)
+
+
diff --git a/sysdeps/riscv/rvv/strnlen.S b/sysdeps/riscv/rvv/strnlen.S
new file mode 100644
index 0000000000..c1ce12baa5
--- /dev/null
+++ b/sysdeps/riscv/rvv/strnlen.S
@@ -0,0 +1,56 @@
+/* RVV versions strnlen.  RISC-V version.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+   Contributed by: Nick Knight <nick.knight@sifive.com>
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+#define pStr a0
+#define pCopyStr a2
+#define iRetValue a0
+#define iMaxlen a1
+#define iCurrentVL a3
+#define iEndOffset a4
+
+#define ELEM_LMUL_SETTING m1
+#define vStr v0
+#define vMaskEnd v8
+
+ENTRY(__strnlen)
+
+    mv pCopyStr, pStr
+    mv iRetValue, iMaxlen
+L(strnlen_loop):
+    beqz iMaxlen, L(end_strnlen_loop)
+    vsetvli zero, iMaxlen, e8, ELEM_LMUL_SETTING, ta, ma
+    vle8ff.v vStr, (pCopyStr)
+    vmseq.vi vMaskEnd, vStr, 0
+    vfirst.m iEndOffset, vMaskEnd /* first occurence of \0 */
+    csrr iCurrentVL, vl
+    add pCopyStr, pCopyStr, iCurrentVL
+    sub iMaxlen, iMaxlen, iCurrentVL
+    bltz iEndOffset, L(strnlen_loop)
+    add iMaxlen, iMaxlen, iCurrentVL
+    sub iRetValue, iRetValue, iMaxlen
+    add iRetValue, iRetValue, iEndOffset
+L(end_strnlen_loop):
+    ret
+END(__strnlen)
+weak_alias (__strnlen, strnlen)
+libc_hidden_builtin_def (strnlen)
+libc_hidden_builtin_def (__strnlen)
-- 
2.25.1

Re: [PATCH 2/4] riscv: vectorized mem* functions

[Sergei Lewis]

[-- Attachment #1: Type: text/plain, Size: 1020 bytes --]

I note this memcpy implementation performs a vsetvli, load, store, three
ALU ops and a branch per loop.

If, instead, you start by copying just enough bytes to align the
destination pointer to vlen*lmul, you can pull the vsetvli out of the loop,
since you know the number of bytes remaining is a multiple of the operation
size - essentially, you've done the tail handling up front. Then, since you
no longer need to track the number of bytes remaining in order to feed it
to vsetvli, you can also calculate the expected buffer end outside the
loop, have the conditional branch compare current destination with that
instead of comparing number of bytes remaining with 0, and therefore also
lose an ALU op from the loop.

You can see this pattern in the vectorised mem* patchset I posted a while
back. In my testing I found this can improve performance by 10-15% compared
to the naive approach (depending on chosen LMUL, operation size and L1
size).

The other mem* functions can also similarly benefit from this pattern.

Re: [PATCH 2/4] riscv: vectorized mem* functions

[Yun Hsiang]

On Thu, Mar 02, 2023 at 10:37:04AM +0000, Sergei Lewis wrote:
> 
> I note this memcpy implementation performs a vsetvli, load, store, three
> ALU ops and a branch per loop.
> 
> If, instead, you start by copying just enough bytes to align the
> destination pointer to vlen*lmul, you can pull the vsetvli out of the loop,
> since you know the number of bytes remaining is a multiple of the operation
> size - essentially, you've done the tail handling up front. Then, since you
> no longer need to track the number of bytes remaining in order to feed it
> to vsetvli, you can also calculate the expected buffer end outside the
> loop, have the conditional branch compare current destination with that
> instead of comparing number of bytes remaining with 0, and therefore also
> lose an ALU op from the loop.
> 
> You can see this pattern in the vectorised mem* patchset I posted a while
> back. In my testing I found this can improve performance by 10-15% compared
> to the naive approach (depending on chosen LMUL, operation size and L1
> size).
I've run glibc benchtests and rtl simulation to evaluate the performance between https://patchwork.sourceware.org/project/glibc/patch/20230201095232.15942-2-slewis@rivosinc.com/ and this implementation. In my test, the implementations in this thread have less instruction/cycle count in most test cases.
> 
> The other mem* functions can also similarly benefit from this pattern.