From: Adhemerval Zanella Netto <adhemerval.zanella@linaro.org>
To: Hau Hsu <hau.hsu@sifive.com>,
libc-alpha@sourceware.org, hongrong.hsu@sifive.com,
jerry.shih@sifive.com, nick.knight@sifive.com,
kito.cheng@sifive.com
Cc: greentime.hu@sifive.com, alice.chan@sifive.com,
andrew@sifive.com, vincent.chen@sifive.com
Subject: Re: [PATCH v2 3/5] riscv: vectorized str* functions
Date: Fri, 21 Apr 2023 09:14:23 -0300 [thread overview]
Message-ID: <47132985-a373-ae03-ec50-4ddd47ffa0e3@linaro.org> (raw)
In-Reply-To: <20230421075405.14892-4-hau.hsu@sifive.com>
On 21/04/23 04:54, Hau Hsu via Libc-alpha wrote:
> diff --git a/sysdeps/riscv/rvv/strcmp.S b/sysdeps/riscv/rvv/strcmp.S
> new file mode 100644
> index 0000000000..c5f525bbe9
> --- /dev/null
> +++ b/sysdeps/riscv/rvv/strcmp.S
> @@ -0,0 +1,93 @@
> +// Copyright (c) 2023 SiFive, Inc. -- Proprietary and Confidential All Rights
> +// Reserved.
> +//
This is not acceptable by glibc, it requires to follow the 'Copyright and license'
as decribed by [1].
Also, no C99 one line comment.
[1] https://sourceware.org/glibc/wiki/Contribution%20checklist#Copyright_and_license
> +// NOTICE: All information contained herein is, and remains the property of
> +// SiFive, Inc. The intellectual and technical concepts contained herein are
> +// proprietary to SiFive, Inc. and may be covered by U.S. and Foreign Patents,
> +// patents in process, and are protected by trade secret or copyright law.
> +//
> +// This work may not be copied, modified, re-published, uploaded, executed, or
> +// distributed in any way, in any medium, whether in whole or in part, without
> +// prior written permission from SiFive, Inc.
> +//
> +// The copyright notice above does not evidence any actual or intended
> +// publication or disclosure of this source code, which includes information
> +// that is confidential and/or proprietary, and is a trade secret, of SiFive,
> +// Inc.
> +//===----------------------------------------------------------------------===//
> +
> +// Contributed by: Jerry Shih <jerry.shih@sifive.com>
> +
> +// Prototype:
> +// int strcmp(const char *lhs, const char *rhs)
> +
> +#include <sysdep.h>
> +#include <sys/asm.h>
> +
> +#define iResult a0
> +
> +#define pStr1 a0
> +#define pStr2 a1
> +
> +#define iVL a2
> +#define iTemp1 a3
> +#define iTemp2 a4
> +
> +#define vStr1 v0
> +#define vStr2 v8
> +#define vMask1 v16
> +#define vMask2 v17
> +
> +ENTRY(strcmp)
> + // lmul=1
> +
> +L(Loop):
> + vsetvli iVL, zero, e8, m1, ta, ma
> + vle8ff.v vStr1, (pStr1)
> + // check if vStr1[i] == 0
> + vmseq.vx vMask1, vStr1, zero
> +
> + vle8ff.v vStr2, (pStr2)
> + // check if vStr1[i] != vStr2[i]
> + vmsne.vv vMask2, vStr1, vStr2
> +
> + // find the index x for vStr1[x]==0
> + vfirst.m iTemp1, vMask1
> + // find the index x for vStr1[x]!=vStr2[x]
> + vfirst.m iTemp2, vMask2
> +
> + bgez iTemp1, L(check1)
> + bgez iTemp2, L(check2)
> +
> + // get the current vl updated by vle8ff.
> + csrr iVL, vl
> + add pStr1, pStr1, iVL
> + add pStr2, pStr2, iVL
> + j L(Loop)
> +
> + // iTemp1>=0
> +L(check1):
> + bltz iTemp2, 1f
> + blt iTemp2, iTemp1, L(check2)
> +1:
> + // iTemp2<0
> + // iTemp2>=0 && iTemp1<iTemp2
> + add pStr1, pStr1, iTemp1
> + add pStr2, pStr2, iTemp1
> + lbu iTemp1, 0(pStr1)
> + lbu iTemp2, 0(pStr2)
> + sub iResult, iTemp1, iTemp2
> + ret
> +
> + // iTemp1<0
> + // iTemp2>=0
> +L(check2):
> + add pStr1, pStr1, iTemp2
> + add pStr2, pStr2, iTemp2
> + lbu iTemp1, 0(pStr1)
> + lbu iTemp2, 0(pStr2)
> + sub iResult, iTemp1, iTemp2
> + ret
> +
> +END(strcmp)
> +libc_hidden_builtin_def (strcmp)
next prev parent reply other threads:[~2023-04-21 12:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-21 7:54 [PATCH v2 0/5] riscv: Vectorized mem*/str* function Hau Hsu
2023-04-21 7:54 ` [PATCH v2 1/5] riscv: Enabling vectorized mem*/str* functions in build time Hau Hsu
2023-04-21 7:54 ` [PATCH v2 2/5] riscv: vectorized mem* functions Hau Hsu
2023-04-21 12:12 ` Adhemerval Zanella Netto
2023-04-21 7:54 ` [PATCH v2 3/5] riscv: vectorized str* functions Hau Hsu
2023-04-21 12:14 ` Adhemerval Zanella Netto [this message]
2023-04-21 7:54 ` [PATCH v2 4/5] riscv: vectorized strchr and strnlen functions Hau Hsu
2023-04-21 7:54 ` [PATCH v2 5/5] riscv: add vectorized __memcmpeq Hau Hsu
2023-04-21 12:09 ` [PATCH v2 0/5] riscv: Vectorized mem*/str* function Adhemerval Zanella Netto
2023-04-26 3:11 ` Hau Hsu
-- strict thread matches above, loose matches on Subject: below --
2023-04-21 7:31 [PATCH v2 3/5] riscv: vectorized str* functions Hau Hsu
2023-04-21 7:30 Hau Hsu
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