From: Hau Hsu <hau.hsu@sifive.com>
To: libc-alpha@sourceware.org, hongrong.hsu@sifive.com,
jerry.shih@sifive.com, nick.knight@sifive.com,
kito.cheng@sifive.com
Cc: greentime.hu@sifive.com, alice.chan@sifive.com,
andrew@sifive.com, vincent.chen@sifive.com, hau.hsu@sifive.com
Subject: [PATCH v2 0/5] riscv: Vectorized mem*/str* function
Date: Fri, 21 Apr 2023 15:54:00 +0800 [thread overview]
Message-ID: <20230421075405.14892-1-hau.hsu@sifive.com> (raw)
I am submitting version 2 of the patch for adding vectorized mem*/str*
functions for RISC-V. This patch builds upon the previous version (v1)
available at
https://patchwork.sourceware.org/project/glibc/list/?series=17710.
In this version, we have included the __memcmpeq function and set lmul=1
for memcmp, which improves its generality.
Jerry Shih (2):
riscv: vectorized mem* functions
riscv: vectorized str* functions
Nick Knight (1):
riscv: vectorized strchr and strnlen functions
Vincent Chen (1):
riscv: Enabling vectorized mem*/str* functions in build time
Yun Hsiang (1):
riscv: add vectorized __memcmpeq
scripts/build-many-glibcs.py | 10 ++++
sysdeps/riscv/preconfigure | 19 +++++++
sysdeps/riscv/preconfigure.ac | 18 +++++++
sysdeps/riscv/rv32/rvv/Implies | 2 +
sysdeps/riscv/rv64/rvv/Implies | 2 +
sysdeps/riscv/rvv/memchr.S | 63 +++++++++++++++++++++++
sysdeps/riscv/rvv/memcmp.S | 71 ++++++++++++++++++++++++++
sysdeps/riscv/rvv/memcmpeq.S | 69 +++++++++++++++++++++++++
sysdeps/riscv/rvv/memcpy.S | 51 +++++++++++++++++++
sysdeps/riscv/rvv/memmove.S | 72 ++++++++++++++++++++++++++
sysdeps/riscv/rvv/memset.S | 51 +++++++++++++++++++
sysdeps/riscv/rvv/strcat.S | 72 ++++++++++++++++++++++++++
sysdeps/riscv/rvv/strchr.S | 53 +++++++++++++++++++
sysdeps/riscv/rvv/strcmp.S | 93 ++++++++++++++++++++++++++++++++++
sysdeps/riscv/rvv/strcpy.S | 56 ++++++++++++++++++++
sysdeps/riscv/rvv/strlen.S | 54 ++++++++++++++++++++
sysdeps/riscv/rvv/strncat.S | 83 ++++++++++++++++++++++++++++++
sysdeps/riscv/rvv/strncmp.S | 85 +++++++++++++++++++++++++++++++
sysdeps/riscv/rvv/strncpy.S | 86 +++++++++++++++++++++++++++++++
sysdeps/riscv/rvv/strnlen.S | 56 ++++++++++++++++++++
20 files changed, 1066 insertions(+)
create mode 100644 sysdeps/riscv/rv32/rvv/Implies
create mode 100644 sysdeps/riscv/rv64/rvv/Implies
create mode 100644 sysdeps/riscv/rvv/memchr.S
create mode 100644 sysdeps/riscv/rvv/memcmp.S
create mode 100644 sysdeps/riscv/rvv/memcmpeq.S
create mode 100644 sysdeps/riscv/rvv/memcpy.S
create mode 100644 sysdeps/riscv/rvv/memmove.S
create mode 100644 sysdeps/riscv/rvv/memset.S
create mode 100644 sysdeps/riscv/rvv/strcat.S
create mode 100644 sysdeps/riscv/rvv/strchr.S
create mode 100644 sysdeps/riscv/rvv/strcmp.S
create mode 100644 sysdeps/riscv/rvv/strcpy.S
create mode 100644 sysdeps/riscv/rvv/strlen.S
create mode 100644 sysdeps/riscv/rvv/strncat.S
create mode 100644 sysdeps/riscv/rvv/strncmp.S
create mode 100644 sysdeps/riscv/rvv/strncpy.S
create mode 100644 sysdeps/riscv/rvv/strnlen.S
--
2.37.1
next reply other threads:[~2023-04-21 7:54 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-21 7:54 Hau Hsu [this message]
2023-04-21 7:54 ` [PATCH v2 1/5] riscv: Enabling vectorized mem*/str* functions in build time Hau Hsu
2023-04-21 7:54 ` [PATCH v2 2/5] riscv: vectorized mem* functions Hau Hsu
2023-04-21 12:12 ` Adhemerval Zanella Netto
2023-04-21 7:54 ` [PATCH v2 3/5] riscv: vectorized str* functions Hau Hsu
2023-04-21 12:14 ` Adhemerval Zanella Netto
2023-04-21 7:54 ` [PATCH v2 4/5] riscv: vectorized strchr and strnlen functions Hau Hsu
2023-04-21 7:54 ` [PATCH v2 5/5] riscv: add vectorized __memcmpeq Hau Hsu
2023-04-21 12:09 ` [PATCH v2 0/5] riscv: Vectorized mem*/str* function Adhemerval Zanella Netto
2023-04-26 3:11 ` Hau Hsu
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